AD_AD603

Low Noise, 90 MHz Variable Gain Amplifier AD603 Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES Linear-in-dB gain control Pin-programmable gain ranges −11 dB to +31 dB with 90 MHz bandwidth 9 dB to 51 dB with 9 MHz bandwidth Any intermediate range, for example −1 dB to +41 dB with 30 MHz bandwidth Bandwidth independent of variable gain 1.3 nV/√Hz input noise spectral density ±0.5 dB typical gain accuracy APPLICATIONS RF/IF AGC amplifiers Video gain controls A/D range extensions Signal measurements GENERAL DESCRIPTION The AD603 is a low noise, voltage-controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin-selectable gains of −11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to 51+ dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor. The input referred noise spectral density is only 1.3 nV/√Hz, and power consumption is 125 mW at the recommended ±5 V supplies. The decibel gain is linear in dB, accurately calibrated, and stable over temperature and supply. The gain is controlled at a high impedance (50 MΩ), low bias (200 nA) differential input; the scaling is 25 mV/dB, requiring a gain control voltage of only 1 V to span the central 40 dB of the gain range. An overrange and underrange of 1 dB is provided whatever the selected range. The gain control response time is less than 1 μs for a 40 dB change. The differential gain control interface allows the use of either differential or single-ended positive or negative control voltages. Several of these amplifiers may be cascaded and their gain control gains offset to optimize the system SNR. The AD603 can drive a load impedance as low as 100 Ω with low distortion. For a 500 Ω load in shunt with 5 pF, the total harmonic distortion for a ±1 V sinusoidal output at 10 MHz is typically −60 dBc. The peak specified output is ±2.5 V minimum into a 500 Ω load. The AD603 uses a patented proprietary circuit topology—the X-AMP®. The X-AMP comprises a variable attenuator of 0 dB to −42.14 dB followed by a fixed-gain amplifier. Because of the attenuator, the amplifier never has to cope with large inputs and can use negative feedback to define its (fixed) gain and dynamic performance. The attenuator has an input resistance of 100 Ω, laser trimmed to ±3%, and comprises a 7-stage R-2R ladder network, resulting in an attenuation between tap points of 6.021 dB. A proprietary interpolation technique provides a continuous gain control function that is linear in dB. The AD603 is specified for operation from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM SCALING REFERENCE VG GAIN- CONTROL INTERFACE AD603 PRECISION PASSIVE INPUT ATTENUATOR FIXED-GAIN AMPLIFIER *NOMINAL VALUES. R-2R LADDER NETWORK VPOS VNEG GPOS GNEG VINP COMM 0dB –6.02dB –12.04dB –18.06dB –24.08dB –30.1dB –36.12dB –42.14dB R R R R R R R 2R 2R 2R 2R 2R 2R R 20Ω* 694Ω* 6.44kΩ* VOUT FDBK 00 53 9- 00 1 8 6 1 2 5 7 4 3 Figure 1. AD603 Rev. H | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configurations and Function Descriptions ........................... 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 11 Noise Performance ..................................................................... 11 The Gain Control Interface....................................................... 12 Programming the Fixed-Gain Amplifier Using Pin Strapping............................................................................... 12 Using the AD603 in Cascade ........................................................ 14 Sequential Mode (Optimal SNR) ............................................. 14 Parallel Mode (Simplest Gain Control Interface) .................. 16 Low Gain Ripple Mode (Minimum Gain Error) ................... 16 Applications Information .............................................................. 17 A Low Noise AGC Amplifier.................................................... 17 Caution ........................................................................................ 18 Evaluation Board ............................................................................ 19 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 REVISION HISTORY 5/07—Rev. G to Rev. H Changes to Layout ...........................................................................14 Changes to Layout ...........................................................................15 Changes to Layout ...........................................................................16 Inserted Evaluation Board Section, and Figure 48 to Figure 51 ...........................................................................................19 Inserted Figure 52 and Table 4.......................................................20 Changes to Ordering Guide ...........................................................21 3/05—Rev. F to Rev. G Updated Format.................................................................. Universal Change to Features ............................................................................1 Changes to General Description .....................................................1 Change to Figure 1 ............................................................................1 Changes to Specifications .................................................................3 New Figure 4 and Renumbering Subsequent Figures...................6 Change to Figure 10 ..........................................................................7 Change to Figure 23 ..........................................................................9 Change to Figure 29 ........................................................................12 Updated Outline Dimensions ........................................................20 4/04—Rev. E to Rev. F Changes to Specifications.................................................................2 Changes to Ordering Guide .............................................................3 8/03—Rev. D to Rev E Updated Format.................................................................. Universal Changes to Specifications.................................................................2 Changes to TPCs 2, 3, 4 ....................................................................4 Changes to Sequential Mode (Optimal S/N Ratio) section.........9 Change to Figure 8 ..........................................................................10 Updated Outline Dimensions........................................................14 AD603 Rev. H | Page 3 of 24 SPECIFICATIONS @ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance Pin 3 to Pin 4 97 100 103 Ω Input Capacitance 2 pF Input Noise Spectral Density1 Input short-circuited 1.3 nV/√Hz Noise Figure f = 10 MHz, gain = maximum, RS = 10 Ω 8.8 dB 1 dB Compression Point f = 10 MHz, gain = maximum, RS = 10 Ω −11 dBm Peak Input Voltage ±1.4 ±2 V OUTPUT CHARACTERISTICS −3 dB Bandwidth VOUT = 100 mV rms 90 MHz Slew Rate RL ≥ 500 Ω 275 V/μs Peak Output2 RL ≥ 500 Ω ±2.5 ±3.0 V Output Impedance f ≤ 10 MHz 2 Ω Output Short-Circuit Current 50 mA Group Delay Change vs. Gain f = 3 MHz; full gain range ±2 ns Group Delay Change vs. Frequency VG = 0 V; f = 1 MHz to 10 MHz ±2 ns Differential Gain 0.2 % Differential Phase 0.2 Degree Total Harmonic Distortion f = 10 MHz, VOUT = 1 V rms −60 dBc Third-Order Intercept f = 40 MHz, gain = maximum, RS = 50 Ω 15 dBm ACCURACY Gain Accuracy, f = 100 kHz; Gain (dB) = (40 VG + 10) dB −500 mV ≤ VG ≤ +500 mV −1 ±0.5 +1 dB TMIN to TMAX −1.5 +1.5 dB Gain, f = 10.7 MHz VG = -0.5 V −10.3 −9.0 −8.0 dB VG = 0.0 V +9.5 +10.5 +11.5 dB VG = 0.5 V +29.3 +30.3 +31.3 dB Output Offset Voltage3 VG = 0 V −20 +20 mV TMIN to TMAX −30 +30 mV Output Offset Variation vs. VG −500 mV ≤ VG ≤ +500 mV −20 +20 mV TMIN to TMAX −30 +30 mV GAIN CONTROL INTERFACE Gain Scaling Factor 100 kHz 39.4 40 40.6 dB/V TMIN to TMAX 38 42 dB/V 10.7 MHz 38.7 39.3 39.9 dB/V GNEG, GPOS Voltage Range4 −1.2 +2.0 V Input Bias Current 200 nA Input Offset Current 10 nA Differential Input Resistance Pin 1 to Pin 2 50 MΩ Response Rate Full 40 dB gain change 80 dB/μs POWER SUPPLY Specified Operating Range ±4.75 ±6.3 V Quiescent Current 12.5 17 mA TMIN to TMAX 20 mA 1 Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage and current noise sources. 2 Using resistive loads of 500 Ω or greater or with the addition of a 1 kΩ pull-down resistor when driving lower loads. 3 The dc gain of the main amplifier in the AD603 is ×35.7; therefore, an input offset of 100 μV becomes a 3.57 mV output offset. 4 GNEG and GPOS, gain control, and voltage range are guaranteed to be within the range of −VS + 4.2 V to +VS − 3.4 V over the full temperature range of −40°C to +85°C. AD603 Rev. H | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage ±VS ±7.5 V Internal Voltage VINP (Pin 3) ±2 V Continuous ±VS for 10 ms GPOS, GNEG (Pin 1 and Pin2) ±VS Internal Power Dissipation 400 mW Operating Temperature Range AD603A −40°C to +85°C AD603S −55°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Thermal Characteristics Package Type θJA θJC Unit 8-Lead SOIC 155 33 °C/W 8-Lead CERDIP 140 15 °C/W ESD CAUTION AD603 Rev. H | Page 5 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GPOS 1 GNEG 2 VINP 3 COMM 4 VPOS8 VOUT7 VNEG6 FDBK5 AD603 TOP VIEW (Not to Scale) 00 53 9- 00 2 Figure 2. 8-Lead SOIC Pin Configuration 00 53 9- 00 3 GPOS 1 GNEG 2 VINP 3 COMM 4 VPOS8 VOUT7 VNEG6 FDBK5 AD603 TOP VIEW (Not to Scale) Figure 3. 8-Lead CERDIP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 GPOS Gain Control Input High (Positive Voltage Increases Gain). 2 GNEG Gain Control Input Low (Negative Voltage Increases Gain). 3 VINP Amplifier Input. 4 COMM Amplifier Ground. 5 FDBK Connection to Feedback Network. 6 VNEG Negative Supply Input. 7 VOUT Amplifier Output. 8 VPOS Positive Supply Input. AD603 Rev. H | Page 6 of 24 TYPICAL PERFORMANCE CHARACTERISTICS @ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unless otherwise noted. 00 53 9- 00 4 VG (V) 0.6–0.6 –0.4 –0.2 0 0.2 0.4 G A IN (d B ) 40 30 20 10 0 –10 10.7MHz 100kHz Figure 4. Gain vs. VG at 100 kHz and 10.7 MHz 00 53 9- 00 5 GAIN VOLTAGE (V) 0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 G A IN E R R O R (d B ) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 45MHz 70MHz 10.7MHz 455kHz 70MHz Figure 5. Gain Error vs. Gain Control Voltage at 455 kHz, 10.7 MHz, 45 MHz, 70 MHz 00 53 9- 00 6 PH A SE (D eg re es ) –225 225 45 90 135 180 0 –45 –90 –135 –180 FREQUENCY (Hz) 100k 1M 10M 100M G A IN (d B ) 4 2 3 0 1 –2 –1 –4 –5 –3 –6 GAIN PHASE Figure 6. Frequency and Phase Response vs. Gain (Gain = −10 dB, PIN = −30 dBm) 00 53 9- 00 7–225 225 180 135 90 45 0 –45 –90 –180 –135 PH A SE (D eg re es ) FREQUENCY (Hz) 100k 1M 10M 100M G A IN (d B ) 4 2 1 3 0 –1 –2 –3 –4 –5 –6 GAIN PHASE Figure 7. Frequency and Phase Response vs. Gain (Gain = 10 dB, PIN = −30 dBm) 00 53 9- 00 8 PH A SE (D eg re es ) –225 225 45 90 135 180 0 –45 –90 –135 –180 FREQUENCY (Hz) 100k 1M 10M 100M G A IN (d B ) 4 2 3 0 1 –2 –1 –4 –3 –6 –5 GAIN PHASE Figure 8. Frequency and Phase Response vs. Gain (Gain = 30 dB, PIN = −30 dBm) 00 53 9- 00 9 GAIN CONTROL VOLTAGE (V) 0.6–0.6 –0.4 –0.2 0 0.2 0.4 G R O U P D EL AY (n s) 7.6 7.4 7.2 7.0 6.8 6.6 6.4 Figure 9. Group Delay vs. Gain Control Voltage AD603 Rev. H | Page 7 of 24 DATEL DVC 8500 HP3326A DUAL- CHANNEL SYNTHESIZER 100Ω +5V 511Ω 10× PROBE HP3585A SPECTRUM ANALYZER 0.1µF 00 53 9- 01 0 AD603 8 5 4 7 3 6 1 2 –5V 0.1µF Figure 10. Third-Order Intermodulation Distortion Test Setup 00 53 9- 01 1 10dB/DIV Figure 11. Third-Order Intermodulation Distortion at 455 kHz (10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm) 00 53 9- 01 2 10dB/DIV Figure 12. Third-Order Intermodulation Distortion at 10.7 MHz (10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm) 00 53 9- 01 3 LOAD RESISTANCE (Ω) 0 50 100 200 500 1000 2000 N EG AT IV E O U TP U T VO LT A G E (V ) –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –2.2 –2.4 –2.6 –2.8 –3.0 –3.2 –3.4 Figure 13. Typical Output Voltage Swing vs. Load Resistance (Negative Output Swing Limits First) 00 53 9- 01 4 FREQUENCY (Hz) 100M100k 1M 10M IN PU T IM PE D A N C E (Ω ) 102 100 98 94 96 Figure 14. Input Impedance vs. Frequency (Gain = −10 dB) 00 53 9- 01 5 FREQUENCY (Hz) 100M100k 1M 10M IN PU T IM PE D A N C E (Ω ) 100 102 98 96 94 Figure 15. Input Impedance vs. Frequency (Gain = 10 dB) AD603 Rev. H | Page 8 of 24 00 53 9- 01 6 FREQUENCY (Hz) 100M100k 1M 10M IN PU T IM PE D A N C E (Ω ) 100 102 98 96 94 Figure 16. Input Impedance vs. Frequency (Gain = 30 dB) 00 53 9- 01 7 1V 200ns 1V 10 0% 100 90 Figure 17. Gain Control Channel Response Time 00 53 9- 01 8 451ns–49ns 50ns 4.5V 500mV –500mV INPUT GND 1V/DIV OUTPUT GND 500mV/DIV Figure 18. Input Stage Overload Recovery Time (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) 00 53 9- 01 9 451ns–49ns 50ns 3V 1V –2V INPUT GND 100MV/DIV OUTPUT GND 1V/DIV Figure 19. Output Stage Overload Recovery Time (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) 00 53 9- 02 0 GND GND 456ns–44ns 50ns 3.5V 500mV –1.5V INPUT 500mV/DIV OUTPUT 500mV/DIV Figure 20. Transient Response, G = 0 dB (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) 00 53 9- 02 1 456ns–44ns 50ns 3.5V 500mV –1.5V INPUT GND 100mV/DIV OUTPUT GND 500mV/DIV Figure 21. Transient Response, G = 20 dB (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) AD603 Rev. H | Page 9 of 24 00 53 9- 02 2 FREQUENCY (Hz) 100M100k 1M 10M PS R R (d B ) 0 –10 –20 –30 –40 –50 –60 Figure 22. PSRR vs. Frequency (Worst Case Is Negative Supply PSRR, Shown Here) DATEL DVC 8500 HP3326A DUAL- CHANNEL SYNTHESIZER 100Ω +5V 50Ω HP3585A SPECTRUM ANALYZER 0.1µF AD603 8 5 4 7 3 6 1 2 –5V 0.1µF 00 53 9- 02 3 Figure 23. Test Setup Used for: Noise Figure, Third-Order Intercept, and 1 dB Compression Point Measurements 00 53 9- 02 4 GAIN (dB) 3020 21 22 23 24 25 26 27 28 29 N O IS E FI G U R E (d B ) 23 21 19 17 15 13 11 9 7 5 TA = 25°C RS = 50V TEST SETUP FIGURE 2370MHz 30MHz 50MHz 10MHz Figure 24. Noise Figure in −10 dB/+30 dB Mode 00 53 9- 02 5 GAIN (dB) 4030 31 32 33 34 35 36 37 38 39 N O IS E FI G U R E (d B ) 21 17 19 15 11 13 7 9 5 TA = 25°C RS = 50Ω TEST SETUP FIGURE 23 20MHz 10MHz Figure 25. Noise Figure in 0 dB/40 dB Mode 00 53 9- 02 6 INPUT FREQUENCY (MHz) 7010 30 50 IN PU T LE VE L (d B m ) 0 –5 –10 –15 –20 –25 TA = 25°C TEST SETUP FIGURE 23 Figure 26. 1 dB Compression Point, −10 dB/+30 dB Mode, Gain = 30 dB 00 53 9- 02 7 INPUT LEVEL (dBm) 0–20 –10 O U TP U T LE VE L (d B m ) 20 18 16 12 14 10 0 TA = 25°C TEST SETUP FIGURE 23 30MHz 40MHz 70MHz Figure 27. Third-Order Intercept −10 dB/+30 dB Mode, Gain = 10 dB AD603 Rev. H | Page 10 of 24 00 53 9- 02 8 INPUT LEVEL (dBm) –20–40 –30 O U TP U T LE VE L (d B m ) 20 16 18 14 12 10 8 TA = 25°C RS = 50Ω RIN = 50Ω RL = 100Ω TEST SETUP FIGURE 2330MHz 40MHz 70MHz Figure 28. Third-Order Intercept −10 dB/+30 dB Mode, Gain = 30 dB AD603 Rev. H | Page 11 of 24 THEORY OF OPERATION The AD603 comprises a fixed-gain amplifier, preceded by a broadband passive attenuator of 0 dB to 42.14 dB, having a gain control scaling factor of 40 dB per volt. The fixed gain is laser- trimmed in two ranges, to either 31.07 dB (×35.8) or 50 dB (×358), or it may be set to any range in between using one external resistor between Pin 5 and Pin 7. Somewhat higher gain can be obtained by connecting the resistor from Pin 5 to common, but the increase in output offset voltage limits the maximum gain to about 60 dB. For any given range, the bandwidth is independent of the voltage-controlled gain. This system provides an underrange and overrange of 1.07 dB in all cases; for example, the overall gain is −11.07 dB to +31.07 dB in the maximum bandwidth mode (Pin 5 and Pin 7 strapped). This X-AMP structure has many advantages over former methods of gain control based on nonlinear elements. Most importantly, the fixed-gain amplifier can use negative feedback to increase its accuracy. Because large inputs are first attenuated, the amplifier input is always small. For example, to deliver