IPC-7525A(Stencil Design Guidelines)

IPC-7525A Stencil Design Guidelines ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES ® 3000 Lakeside Drive, Suite 309S, Bannockburn, IL 60015-1249 Tel. 847.615.7100 Fax 847.615.7105 www.ipc.org IPC-7525A February 2007 A standard developed by IPC Supersedes IPC-7525 May 2000 The Principles of Standardization In May 1995 the IPC’s Technical Activities Executive Committee (TAEC) adopted Principles of Standardization as a guiding principle of IPC’s standardization efforts. Standards Should: • Show relationship to Design for Manufacturability (DFM) and Design for the Environment (DFE) • Minimize time to market • Contain simple (simplified) language • Just include spec information • Focus on end product performance • Include a feedback system on use and problems for future improvement Standards Should Not: • Inhibit innovation • Increase time-to-market • Keep people out • Increase cycle time • Tell you how to make something • Contain anything that cannot be defended with data Notice IPC Standards and Publications are designed to serve the public interest through eliminating mis- understandings between manufacturers and purchasers, facilitating interchangeability and improve- ment of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of IPC from manufacturing or selling products not conforming to such Standards and Publication, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than IPC members, whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by IPC without regard to whether their adop- tion may involve patents on articles, materials, or processes. By such action, IPC does not assume any liability to any patent owner, nor do they assume any obligation whatever to parties adopting the Recommended Standard or Publication. Users are also wholly responsible for protecting them- selves against all claims of liabilities for patent infringement. IPC Position Statement on Specification Revision Change It is the position of IPC’s Technical Activities Executive Committee that the use and implementation of IPC publications is voluntary and is part of a relationship entered into by customer and supplier. When an IPC publication is updated and a new revision is published, it is the opinion of the TAEC that the use of the new revision as part of an existing relationship is not automatic unless required by the contract. The TAEC recommends the use of the latest revision. Adopted October 6, 1998 Why is there a charge for this document? Your purchase of this document contributes to the ongoing development of new and updated industry standards and publications. Standards allow manufacturers, customers, and suppliers to understand one another better. Standards allow manufacturers greater efficiencies when they can set up their processes to meet industry standards, allowing them to offer their customers lower costs. IPC spends hundreds of thousands of dollars annually to support IPC’s volunteers in the standards and publications development process. There are many rounds of drafts sent out for review and the committees spend hundreds of hours in review and development. IPC’s staff attends and par- ticipates in committee activities, typesets and circulates document drafts, and follows all necessary procedures to qualify for ANSI approval. IPC’s membership dues have been kept low to allow as many companies as possible to participate. Therefore, the standards and publications revenue is necessary to complement dues revenue. The price schedule offers a 50% discount to IPC members. If your company buys IPC standards and publications, why not take advantage of this and the many other benefits of IPC membership as well? For more information on membership in IPC, please visit www.ipc.org or call 847/597-2872. Thank you for your continued support. ©Copyright 2007. IPC, Bannockburn, Illinois. All rights reserved under both international and Pan-American copyright conventions. Any copying, scanning or other reproduction of these materials without the prior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copyright Law of the United States. IPC-7525A Stencil Design Guidelines Developed by the Stencil Design Task Group (5-21e) of the Assembly and Joining Processes Committee (5-20) of IPC Users of this publication are encouraged to participate in the development of future revisions. Contact: IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249 Tel 847 615.7100 Fax 847 615.7105 Supersedes: IPC-7525 - May 2000 ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES ® Acknowledgment Any document involving a complex technology draws material from a vast number of sources. While the principal members of the Stencil Design Task Group (5-21e) of the Assembly and Joining Processes Committee (5-20) are shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them, the members of the IPC extend their gratitude. Assembly and Joining Processes Committee Stencil Design Task Group Technical Liaisons of the IPC Board of Directors Chair Leo Lambert EPTAC Corporation Co-Chairs William E. Coleman, Ph.D Photo Stencil Inc. Kathy Jenczewski MicroScreen, LLC Peter Bigelow IMI Inc. Sammy Yi Flextronics International Stencil Design Task Group Charles Dal Currier, Ambitech Inc. Christopher Sattler, AQS - All Quality & Services, Inc. Jay B. Hinerman, BAE Systems CNI Div. Gary M. Carabetta, Bose Corporation Richard Lieske, DEK USA Inc. Ricky Bennett, DEK USA Inc. Glenn Dody, Dody Consulting Ahne Oosterhof, Fine Line Stencil / A-Laser, Inc. Michael W. Yuen, Foxconn EMS, Inc. Frank V. Grano, GE Fanuc Embedded Systems Deepak K. Pai, C.I.D.+, General Dynamics-Advanced Information Richard R. Lathrop, Jr., Heraeus, Inc. JD Brown, Hewlett-Packard Co-ProCurve Networking Rongxiang (Davis) Yang, Huawei Technologies Co., Ltd. Tim Jensen, Indium Corporation of America Kantesh Doss, Ph.D., Intel Corporation David P. Torp, Kester Maureen A. Brown, Kester Barry R. Goukler, Metal Etching Technology Bill Kunkle, Metal Etching Technology Holly Wise, MicroScreen, LLC Kathy Jenczewski, MicroScreen, LLC William Dean May, NSWC Crane Michael R. Burgess, Photo Stencil Inc. William E. Coleman, Ph.D., Photo Stencil Inc. Dale Kratz, Plexus Corp. Denis Jean, Plexus Corp. Timothy M. Pitsch, Plexus Corp. Charlie Davis, RadiSys Corporation Robert Rowland, RadiSys Corporation David R. Nelson, Raytheon Company Jeff Shubrooks, Raytheon Company Mark J. Quealy, Schneider Automation Inc. Narinder Kumar, C.I.D., Solectron Invotronics George Oxx, Solectron Technology Inc. Sagid Quiroz, Sony Guillermo Velazquez, Sony de Tijuana Este S.A. de C.V. Vanessa Lopez, Sony de Tijuana Este S.A. de C.V. Steve Sangillo, Swemco Daan Terstegge, Thales Communications Jerry Cupples, VLSIP Technologies IPC-7525A February 2007 ii Table of Contents 1 PURPOSE ................................................................. 1 1.1 Terms and Definitions ......................................... 1 1.1.1 *Aperture ............................................................. 1 1.1.2 *Aspect Ratio ....................................................... 1 1.1.3 *Area Ratio .......................................................... 1 1.1.4 Border ................................................................... 1 1.1.5 Contained Paste Transfer Head ........................... 1 1.1.6 Etch Factor ........................................................... 1 1.1.7 Fiducials ............................................................... 1 1.1.8 Fine-Pitch BGA/Chip Scale Package (CSP) ....... 1 1.1.9 *Fine-Pitch Technology (FPT) ............................ 1 1.1.10 Foil ....................................................................... 1 1.1.11 Frame ................................................................... 1 1.1.12 *Intrusive Soldering ............................................. 1 1.1.13 *Land ................................................................... 1 1.1.14 Modification ......................................................... 1 1.1.15 *Overprinting ....................................................... 1 1.1.16 *Pad ...................................................................... 1 1.1.17 *Squeegee ............................................................ 1 1.1.18 Standard BGA ...................................................... 1 1.1.19 *Stencil ................................................................. 1 1.1.20 Step Stencil .......................................................... 1 1.1.21 *Surface-Mount Technology (SMT) ................... 1 1.1.22 *Through-Hole Technology (THT) ..................... 1 1.1.23 Ultra-Fine Pitch Technology ............................... 2 2 APPLICABLE DOCUMENTS .................................... 2 2.1 IPC ....................................................................... 2 3 STENCIL DESIGN ..................................................... 2 3.1 Stencil Data .......................................................... 2 3.1.1 Data Format ......................................................... 2 3.1.2 Gerber® Format ................................................... 2 3.1.3 Aperture List ........................................................ 2 3.1.4 Solder Paste Layer ............................................... 2 3.1.5 Data Transfer ....................................................... 2 3.1.6 Panelized Stencils ................................................ 2 3.1.7 Step-and-Repeat ................................................... 2 3.1.8 Image Orientation/Rotation ................................. 2 3.1.9 Image Location .................................................... 2 3.1.10 Identification ........................................................ 3 3.2 Aperture Design ................................................... 3 3.2.1 Aperture Size ....................................................... 3 3.2.2 Aperture Size Versus Board Land Size for Tin Lead Solder Paste ......................................... 6 3.2.3 Aperture Size versus Board Land Size for Lead Free Solder Paste ........................................ 7 3.2.4 Glue Aperture Chip Component ......................... 8 3.2.5 Glue Apertures for Combination of Chip Components and Leaded Devices ....................... 8 3.3 Mixed Technology Surface-Mount/Through- Hole (Intrusive Reflow) ....................................... 8 3.3.1 Solder Paste Volume ............................................ 9 3.4 Mixed Technology Surface-Mount/Flip Chip ... 10 3.4.1 Two-Print Stencil for Surface-Mount/ Flip Chip ............................................................ 11 3.5 Step Stencil Design ........................................... 11 3.5.1 Step-Down Stencil ............................................. 11 3.5.2 Step-Up Stencil .................................................. 11 3.5.3 Step Stencil for Contained Paste Transfer Heads .................................................................. 11 3.5.4 Relief-Etch Stencil ............................................. 11 3.6 Fiducials ............................................................. 12 3.6.1 Global Fiducials ................................................. 12 3.6.2 Local Fiducials ................................................... 12 4 STENCIL FABRICATION ........................................ 12 4.1 Foils .................................................................... 12 4.2 Frames ................................................................ 12 4.3 Stencil Border .................................................... 12 4.4 Stencil Fabrication Technologies ...................... 12 4.4.1 Chemical Etch .................................................... 12 4.4.2 Laser-Cut Stencils .............................................. 12 4.4.3 Electroform ........................................................ 12 4.4.4 Hybrid ................................................................ 12 4.4.5 Trapezoidal Apertures ........................................ 12 4.4.6 Additional Options ............................................. 12 5 STENCIL MOUNTING ............................................. 13 5.1 Location of Image on Metal ............................. 13 5.2 Centering ............................................................ 13 5.3 Additional Design Guidelines ........................... 13 6 STENCIL ORDERING ............................................. 13 7 STENCIL USER’S INSPECTION/VERIFICATION .. 13 8 STENCIL CLEANING .............................................. 13 9 END OF LIFE .......................................................... 13 APPENDIX A EXAMPLE ORDER FORM .................. 14 February 2007 IPC-7525A iii Figures Figure 3-1 Area Ratio Chart Showing Recommendations for a 4 mil Thick Stencil .................................... 4 Figure 3-2 Area Ratio Chart Showing Recommendations for a 5 mil Thick Stencil .................................... 5 Figure 3-3 Area Ratio Chart Showing Recommendations for a 6 mil Thick Stencil .................................... 5 Figure 3-4 Area Ratio Chart Showing Recommendations for a 8 mil Thick Stencil .................................... 6 Figure 3-5 Cross-Sectional View of A Stencil .................... 6 Figure 3-6 Home Plate Aperture Design ............................ 7 Figure 3-7 Bow Tie Aperture Design .................................. 7 Figure 3-8 Oblong Aperture Design ................................... 7 Figure 3-9 Aperture Design for MELF Components and Chip Components ............................................. 7 Figure 3-10 Window Pane Design for Ground Plane .......... 7 Figure 3-11 Glue Stencil Aperture Design ........................... 8 Figure 3-12 Chip Component and SOIC Present on Board ........................................................... 8 Figure 3-13 Print Only Mode 15 mil Thick Stencil ............... 8 Figure 3-14 Glue Stencil with Glue Reservoir ..................... 9 Figure 3-15 Through-Hole Solder Paste Volume ................. 9 Figure 3-16 Overprint without Step .................................... 10 Figure 3-17 Overprint with Step (Squeegee Side) ............ 10 Figure 3-18 Overprint with Step (Contact/Board Side) ...... 10 Figure 3-19 Two-Print Through-Hole Stencil ...................... 10 Figure 3-20 Two-Print Stencil for Mixed Technology ......... 11 Figure 4-1 Trapezoidal Apertures ..................................... 12 Tables Table 3-1 General Aperture Design Guideline Examples for Selective Surface-Mount Devices (Tin Lead Solder Paste) ...................................................... 3 Table 3-2 Process Window for Intrusive Soldering - Maximum Limits Desirable .................................. 3 IPC-7525A February 2007 iv Stencil Design Guidelines 1 PURPOSE This document provides guides for the design and fabrica- tion of stencils for solder paste and surface-mount adhe- sive. It is intended as a guideline only as much of the con- tent is based on the experience of stencil designers, fabricators and users. Printing performance depends on many different variables and therefore no single set of design rules can be established. 1.1 Terms and Definitions All terms and definitions used throughout this handbook are in compliance with IPC- T-50. Definitions denoted with an asterisk (*) below are reprints from IPC-T-50. Other specific terms and defini- tions, essential for the discussion of the subject, are pro- vided below. 1.1.1 *Aperture An opening in the stencil foil. 1.1.2 *Aspect Ratio The ratio of the width of the aper- ture to the thickness of the stencil foil. 1.1.3 *Area Ratio The ratio of the area of aperture open- ing to the area of aperture walls. 1.1.4 Border Peripheral tensioned mesh, either polyester or stainless steel, which keeps the stencil foil flat and taut. The border connects the foil to the frame. 1.1.5 Contained Paste Transfer Head A stencil printer head that holds, in a single replaceable component, the squeegee blades and a pressurized chamber filled with sol- der paste. 1.1.6 Etch Factor Etch Factor = Etched Depth/Lateral; Etch in a chemical etching process 1.1.7 Fiducials Reference marks on the stencil foil (and other board layers) for aligning the board and the stencil when using a vision system in a printer. 1.1.8 Fine-Pitch BGA/Chip Scale Package (CSP) Ball grid array with less than 1 mm [39 mil] pitch. This is also known as Chip Scale Package (CSP) when the package size is no more than 1.2X the area of the original die size. 1.1.9 *Fine-Pitch Technology (FPT) A surface-mount assembly technology with component terminations on cen- ters less than or equal to 0.625 mm [24.61 mil]. 1.1.10 Foil The sheet used to create the stencil. 1.1.11 Frame This may be made of tubular or cast alu- minum to which a tensioned mesh (border) is permanently bonded using an adhesive. The foil is bonded to the mesh. Some foils can be mounted into a re-usable tensioning master frame and do not require a mesh border and negate a permanent bonding of the foil to the frame. 1.1.12 *Intrusive Soldering Intrusive soldering may also be known as paste-in-hole, pin-in-hole, or pin-in-paste sol- dering. This is a process in which the solder paste for the through-hole components is applied using the stencil. The through-hole components are inserted and reflow-soldered together with the surface-mount components. 1.1.13 *Land A portion of a conductive pattern usually used for the connection and/or attachment of components. 1.1.14 Modification The process of changing an aperture in size or shape. 1.1.15 *Overprinting The use of stencils with apertures larger than the lands or annular rings on the board. 1.1.16 *Pad See land. 1.1.17 *Squeegee A metal or polymer blade used to wipe a material (ink or solder paste) across a stencil or silk screen to force the material through the openings in the screen or stencil, onto the surface of a printed board or mounting structure. Normally the squeegee is mounted at an angle such that the contacting edge of the squeegee trails behind the print head and the face of the squeegee slopes forward. 1.1.18 Standard BGA Ball grid array with 1 mm [39 mil] pitch or larger. 1.1.19 *Stencil A thin sheet of material containing open- ings to reflect a specific pattern, designed to transfer a paste-like material to a substrate for the purpose of compo- nent attachment. 1.1.20 Step Stencil A stencil with more than one foil thickness level. 1.1.21 *Surface-Mount Technology (SMT) The electri- cal connection of components to the surface of a conduc- tive pattern that does not utilize component holes. 1.1.22 *Through-Hole Technology (THT) The electrical connection of components to a conductive pattern by the use of component holes. February 2007 IPC-7525A 1 1.1.23 Ultra-Fine Pitch Technology A surface-mount assembly technology with component terminations on cen- ters less than or equal to 0.40 mm [15.7 mil] 2 APPLICABLE DOCUMENTS 2.1 IPC1 IPC-T-50 Terms and Definitions for Interconnecting and Packaging Electronic Circuits IPC-2581 Generic Requirements for Printed Board Assem- bly Products Manufacturing Description Data and Transfer Methodology (Offspring) IPC-7095 Design and Assembly Process Implementation of BGAs 3 STENCIL DESIGN 3.1 Stencil Data 3.1.1 Data Format Regardless of the stencil fabrication method used, Gerber® is the preferred data format. Pos- sible alternative formats are IPC-2581, DXF, HP-GL,