数字时钟(数字逻辑)课程设计报告

数字时钟 班级： 学号： 姓名： 指导老师： 提交日期：2011年1月8日 1．​ 系统简介： 使用VHDL语言编写程序完成数字时钟的功能设计，利用软件进行编译和仿真，最后利用实验箱实现系统。 2．​ 功能简介： 完成时钟的计时、调整，整点报时等基础功能，完成闹钟的设置、开启和关闭功能，整点报时的开启和关闭功能，完成日期设定和显示功能。 3．​ 总体结构逻辑框图： 4．​ 状态图： 5．​ 各模块电路图及程序： 整体电路连接图： 1.​ 总控制模块： 时钟脉冲分频元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc4_1clkdmux is port( clk:in std_logic; clk1,clk4,clk512:out std_logic); end dc4_1clkdmux; architecture clkdmux of dc4_1clkdmux is signal c1:std_logic_vector(9 downto 0); begin process (clk) begin if clk'event and clk='1'then c1<=c1+1; end if; clk1<=c1(9);clk4<=c1(7); clk512<=c1(0); end process; end clkdmux; 模式控制元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc4_2mode is port( clk4,bt_m:in std_logic; mode:out std_logic_vector(1 downto 0); cr1,cr2:out std_logic); end dc4_2mode; architecture mode of dc4_2mode is signal modx:std_logic_vector(1 downto 0); signal c1,c2:std_logic; begin process (clk4,bt_m) begin if clk4'event and clk4='1' then if bt_m='1' then modx<=modx+1;c2<='1'; else c2<='0'; end if; end if; if modx="00" then c1<='1'; else c1<='0'; end if; mode<=modx; cr1<=c1;cr2<=c2; end process; end mode; 调节项目控制元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc4_2mode is port( clk4,bt_m:in std_logic; mode:out std_logic_vector(1 downto 0); cr1,cr2:out std_logic); end dc4_2mode; architecture mode of dc4_2mode is signal modx:std_logic_vector(1 downto 0); signal c1,c2:std_logic; begin process (clk4,bt_m) begin if clk4'event and clk4='1' then if bt_m='1' then modx<=modx+1;c2<='1'; else c2<='0'; end if; end if; if modx="00" then c1<='1'; else c1<='0'; end if; mode<=modx; cr1<=c1;cr2<=c2; end process; end mode; 数码管显示元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc4_4sel is port( clk:in std_logic; sel:out std_logic_vector(2 downto 0)); end dc4_4sel; architecture sel of dc4_4sel is signal selx:std_logic_vector(2 downto 0); begin process (clk) begin if clk'event and clk='1'then selx<=selx+1; end if; end process; sel<=selx; end sel; 模块波形图： 2.​ 时钟模块： 时钟秒调节元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_1second is port( clk1,clk4,rest,bt_a:in std_logic; mode,set:in std_logic_vector(1 downto 0); sco,mcen:out std_logic; clks0,clks1:out std_logic_vector(3 downto 0)); end dc3_1second; architecture second of dc3_1second is signal s0,s1:std_logic_vector(3 downto 0); signal co,rco,cr:std_logic; begin process (clk1,clk4,rest,bt_a,mode,set) begin if clk4'event and clk4='1'then if mode="01" then if rest='1' then cr<='1'; elsif set="00" and bt_a='1'then cr<='1'; else cr<='0'; end if; end if; end if; if cr='1'then s0<="0000";s1<="0000"; elsif clk1'event and clk1='1' then if s0="1001" and s1="0101" then s0<="0000";s1<="0000";co<='1'; elsif s0="1001" then s0<="0000";s1<=s1+1;co<='0'; else s0<=s0+1;co<='0'; end if; end if; if mode="01" and set="01" and bt_a='1' then rco<=clk4;mcen<='0'; else rco<=co;mcen<='1'; end if; end process; clks0<=s0;clks1<=s1;sco<=rco; end second; 时钟分调节元件: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_1minite is port( sco,mcen,clk4,rest,bt_a:in std_logic; mode,set:in std_logic_vector(1 downto 0); mco,hcen:out std_logic; clkm0,clkm1:out std_logic_vector(3 downto 0)); end dc3_1minite; architecture minite of dc3_1minite is signal m0,m1:std_logic_vector(3 downto 0); signal rco,co,cr:std_logic; begin process (sco,mcen,clk4,rest,bt_a,mode,set) begin if mode="01" and rest='1' then cr<=rest; else cr<='0'; end if; if cr='1' then m0<="0000";m1<="0000"; elsif sco'event and sco='1' then if m0="1001" and m1="0101"then m0<="0000";m1<="0000"; if mcen='1' then co<='1'; else co<='0'; end if; elsif m0="1001" then m0<="0000";m1<=m1+1;co<='0'; else m0<=m0+1;co<='0'; end if; end if; if mode="01" and set="10" and bt_a='1' then rco<=clk4;hcen<='0'; else rco<=co;hcen<='1'; end if; end process; clkm0<=m0;clkm1<=m1;mco<=rco; end minite; 时钟小时调节元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_1hour is port( mco,hcen,clk4,rest,bt_a:in std_logic; mode,set:in std_logic_vector(1 downto 0); hco,dcen:out std_logic; clkh0,clkh1:out std_logic_vector(3 downto 0)); end dc3_1hour; architecture hour of dc3_1hour is signal h0,h1:std_logic_vector(3 downto 0); signal rco,co,cr:std_logic; begin process (mco,hcen,clk4,rest,bt_a,mode,set) begin if mode="01" and rest='1' then cr<=rest; else cr<='0'; end if; if cr='1' then h0<="0000";h1<="0000"; elsif mco'event and mco='1' then if h0="1001" and h1="0101"then h0<="0000";h1<="0000"; if hcen='1' then co<='1'; else co<='0'; end if; elsif h0="1001" then h0<="0000";h1<=h1+1;co<='0'; else h0<=h0+1;co<='0'; end if; end if; if mode="11" and set="00" and bt_a='1' then rco<=clk4;dcen<='0'; else rco<=co;dcen<='1'; end if; end process; clkh0<=h0;clkh1<=h1;hco<=rco; end hour; 时钟模块波形图： 3.​ 闹钟模块： 闹钟分调节元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_2alminite is port( clk4,bt_a:in std_logic; mode,set:in std_logic_vector(1 downto 0); alm0,alm1:out std_logic_vector(3 downto 0)); end dc3_2alminite; architecture alarm of dc3_2alminite is signal m0,m1:std_logic_vector(3 downto 0); signal co:std_logic; begin process (clk4,bt_a,mode,set) begin if clk4'event and clk4='1'then if mode="10"and set="00" and bt_a='1'then if m0="1001"and m1="0101"then m0<="0000";m1<="0000"; elsif m0="1001" then m0<="0000";m1<=m1+1; else m0<=m0+1; end if; end if; end if; end process; alm0<=m0;alm1<=m1; end alarm; 闹钟小时调节元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_2alhour is port( clk4,bt_a:in std_logic; mode,set:in std_logic_vector(1 downto 0); alh0,alh1:out std_logic_vector(3 downto 0)); end dc3_2alhour; architecture alhour of dc3_2alhour is signal h0,h1:std_logic_vector(3 downto 0); begin process (clk4,bt_a,mode,set) begin if clk4'event and clk4='1'then if mode="10"and set="01" and bt_a='1'then if h0="0010"and h1="0100"then h0<="0000";h1<="0000"; elsif h0="1001" then h0<="0000";h1<=h1+1; else h0<=h0+1; end if; end if; end if; end process; alh0<=h0;alh1<=h1; end alhour; 闹钟与时钟比较控制模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_2alcontrol is port( clk,clk1,clk512:in std_logic; alc:in std_logic_vector(1 downto 0); clks0,clks1,clkm0,clkm1,clkh0,clkh1,alm0,alm1,alh0,alh1:in std_logic_vector(3 downto 0); alarm:out std_logic); end dc3_2alcontrol; architecture alcontrol of dc3_2alcontrol is signal al,al0,al1:std_logic; begin process (clk,clk1,clk512,clks0,clks1,clkm0,clkm1,clkh0,clkh1,alm0,alm1,alh0,alh1,alc) begin if clkm0="1001" and clkm1="0101" and clks1="0101"then if clks0="0001"then al<=clk512; elsif clks0="0011"then al<=clk512; elsif clks0="0101"then al<=clk512; elsif clks0="0111"then al<=clk512; elsif clks0="1001"then al<=clk; else al<='0'; end if; else al<='0'; end if; if clkm0=alm0 and clkm1=alm1 and clkh0=alh0 and clkh1=alh1 then if clks1="0000" and clk1='1'then al0<=clk; else al0<='0'; end if; else al0<='0'; end if; if alc="00" then al1<=(al or al0); elsif alc="01" then al1<=al; elsif alc="10" then al1<=al0; elsif alc="11" then al1<='0'; end if; end process; alarm<=al1; end alcontrol; 闹钟与时钟比较控制模块波形图： 4.​ 日期模块 日期日调整元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_3day is port( hco,dcen,clk4,bt_a,sm1,sm2:in std_logic; mode,set:in std_logic_vector(1 downto 0); dco:out std_logic; day0,day1:out std_logic_vector(3 downto 0)); end dc3_3day; architecture day of dc3_3day is signal d0,d1:std_logic_vector(3 downto 0); signal rco,co:std_logic; begin process (hco,dcen,clk4,bt_a,mode,set) begin if hco'event and hco='1' then if sm1='1' then if d0="1000" and d1="0010"then d0<="0000";d1<="0000"; if dcen='1' then co<='1'; else co<='0'; end if; elsif d0="1001" then d0<="0000";d1<=d1+1;co<='0'; else d0<=d0+1;co<='0'; end if; elsif sm2='1' then if d0="0000" and d1="0011"then d0<="0000";d1<="0000"; if dcen='1' then co<='1'; else co<='0'; end if; elsif d0="1001" then d0<="0000";d1<=d1+1;co<='0'; else d0<=d0+1;co<='0'; end if; else if d0="0001" and d1="0011"then d0<="0000";d1<="0000"; if dcen='1' then co<='1'; else co<='0'; end if; elsif d0="1001" then d0<="0000";d1<=d1+1;co<='0'; else d0<=d0+1;co<='0'; end if; end if; end if; if mode="11" and set="01" and bt_a='1' then rco<=clk4; else rco<=co; end if; end process; day0<=d0;day1<=d1;dco<=rco; end day; 日期月调整元件： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dc3_3month is port( dco:in std_logic; sm1,sm2:out std_logic; mon0,mon1:out std_logic_vector(3 downto 0)); end dc3_3month; architecture month of dc3_3month is signal m0,m1:std_logic_vector(3 downto 0); signal month:std_logic_vector(7 downto 0); begin process (dco) begin if dco'event and dco='1' then if m0="0010" and m1="0001" then m0<="0000";m1<="0000"; elsif m0="1001" then m0<="0000";m1<=m1+1; else m0<=m0+1; end if; end if; month<=m1&m0; if month="00000010" then sm1<='1';sm2<='0'; elsif month="00000100" or month="00000110" or month="00001001" or month="00010001" then sm1<='0';sm2<='1'; else sm1<='0';sm2<='0'; end if; end process; mon0<=m0;mon1<=m1; end month; 四(与附加四信号)选一选择器： library ieee; use ieee.std_logic_1164.all; entity dc2_2mux18 is port( m0,m1,h0,h1:in std_logic_vector(3 downto 0); sel:in std_logic_vector(2 downto 0); y:out std_logic_vector(3 downto 0)); end dc2_2mux18; architecture mux18 of dc2_2mux18 is begin process (m0,m1,h0,h1,sel) begin case sel is when "000"=>y<=m0; when "001"=>y<=m1; when "010"=>y<="1111"; when "011"=>y<=h0; when "100"=>y<=h1; when others=>y<="1111"; end case; end process; end mux18; 日期模块波形图： 5.​ 显示驱动模块 数码管动态显示选择元件： library ieee; use ieee.std_logic_1164.all; entity dc1_1choice is port( clk1:in std_logic; set:in std_logic_vector(1 downto 0); sel:in std_logic_vector(2 downto 0); g:out std_logic_vector(7 downto 0)); end dc1_1choice; architecture drive of dc1_1choice is begin process (set,sel) begin if set="00" and sel="000" and clk1='1'then g<="00000000"; elsif set="00" and sel="001" and clk1='1'then g<="00000000"; elsif set="01" and sel="011" and clk1='1'then g<="00000000"; elsif set="01" and sel="100" and clk1='1'then g<="00000000"; elsif set="10" and sel="110" and clk1='1'then g<="00000000"; elsif set="10" and sel="111" and clk1='1'then g<="00000000"; else case sel is when"000"=>g<="00000001"; when"001"=>g<="00000010"; when"010"=>g<="00000100"; when"011"=>g<="00001000"; when"100"=>g<="00010000"; when"101"=>g<="00100000"; when"110"=>g<="01000000"; when others=>g<="10000000"; end case; end if; end process; end drive; 三选一多路数据选择器： library ieee; use ieee.std_logic_1164.all; entity dc1_2mux13 is port( clock,date,alarm:in std_logic_vector(3 downto 0); mode:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end dc1_2mux13; architecture mux13 of dc1_2mux13 is begin process (clock,date,alarm,mode) begin case mode is when "00"=>y<=clock; when "01"=>y<=clock; when "10"=>y<=alarm; when "11"=>y<=date; when others=>y<=clock; end case; end process; end mux13; 七段译码器： library ieee; use ieee.std_logic_1164.all; entity dc1_3display is port( x:in std_logic_vector(3 downto 0); segout:out std_logic_vector(6 downto 0)); end dc1_3display; architecture disay of dc1_3display is begin process (x) begin case x is when "0000"=>segout<="1111110"; when "0001"=>segout<="0110000"; when "0010"=>segout<="1101101"; when "0011"=>segout<="1111001"; when "0100"=>segout<="0110011"; when "0101"=>segout<="1011011"; when "0110"=>segout<="1011111"; when "0111"=>segout<="1110000"; when "1000"=>segout<="1111111"; when "1001"=>segout<="1111011"; when "1010"=>segout<="1001001"; when "1011"=>segout<="1000001"; when "1100"=>segout<="0001001"; when others=>segout<="0000001"; end case; end process; end disay; 6．​  心得体会 决胜全面小康心得体会学党史心得下载党史学习心得下载军训心得免费下载党史学习心得下载 这是一次数字逻辑的整体练兵，本次课程设计，是对VHDL数字逻辑电子设计技术的进一步掌握，也是对MAX+PLLUS设计工具应用的进一步了解。通过不断地优化算法更改错误，关于数字逻辑与系统设计的知识在我脑中大大强化，可以我从这次锻炼中获益匪浅。同时必须感谢老师和同学们的帮助，让我顺利解决各个问题，最终完成课题。