DFT设计流程概述 (上)

ContentICDESIGNMAGAZINEVOLUME35www.Chip123.com1Mar.2003Design-for-TestabilityDFT8-bitRISCCICDFTFreeIPhttp://www.free-ip.comDFTReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com2Mar.2003DFTFree-RISC8DFTFree-RISC88-bitMicrochip16C57VerilogALUInstructionDecoderRegisterFileCPURegisterFileFlip-FlopMemoryBIST(BuiltInSelfTest)MemoryCompilertwo-portasynchronousSRAMRegisterFileMemoryCompilersynchronousROMROMsample2048x12ROM72x8SRAMDFTMemoryBISTMemoryBISTembeddedSRAMROMfull-scanscanchainATPGAutomaticTestPatternGenerationSynTestMemoryBISTSynTestSRAMBISTMemoryBIST.mdfmemorydescriptionfileBIST.mdfsrambistmemory.mdfMemoryBISTRTLcodesynthesisscriptsimulationtestbenchreport1)AsynchronousTwo-portSRAMSpecification(c4mtram72x8)MemoryAttributes:Worddepth:72Addresswidth:7Wordwidth:8Smalladdress:7b0000000Maximumaddress7b1000111Numberofports:twoMemoryPortAttributes:Port1Porttype:ReadAddresssignal:RAzoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com3Mar.2003Dataoutsignal:DOReadenablesignal:REB,activelowOutputenablesignal:OEB,activelowPort2Porttype:WriteAddresssignal:WADatainsignal:DIWriteenablesignal:WEBBISTConstraintSynchronousreset:TrueClockcycle:20nsTimescale:1ns/10psc4mtram72x8.mdf%GLOBAL{%TIMESCALE1ns/10ps;%SYNC_RESETTRUE;%CLK_CYCLE20;%BIST_CLK_TRIGGERposedge;}%MEMORYc4mtram72x8{%TIMESCALE1ns/10ps;%TYPESRAM;%DATA_BITS8;%ADDR_BITS7;%LOW_ADDR7b0000000;%HIGH_ADDR7b1000111;%LATENCY0;%PORTR{%TYPEr;%ADDRESSRA;%DATA_OUTDO;%READ_EN-REB;zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com4Mar.2003DFT%OUTPUT_EN-OEB;}%PORTW{%TYPEw;%ADDRESSWA;%DATA_INDI;%WRITE_EN-WEB;}}GLOBALVerilogtimescaleBISTresetBISTclockMEMORYtimescaleSRAMorROM72word7b00000007b1000111BISTBISTlatencylatencyclocklatency0portportport-.mdfsrambistc4mtram72x8=======SYNTESTSRAMBISTREPORTFILE=======TOOL:srambistV1.1.0r01(08/15/0016:30:26)TIME:WedMar1508:28:262002OPTIONSSELECTED:-algorithmMOIVNUMBEROFMEMORIES:1THECLOCKBEINGUSEDASTHEBISTCLOCK:Allmemoriesareasynchronous.PleasesupplyatestclockandlinkittotheTclkportofthetopmodule.BISTCLOCKTRIGGERING:zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com5Mar.2003Positivetriggeredclock.TOTALBISTCYCLES:1877FILESGENERATED:c4mtram72x8_top.v:TopmoduleBISTconnectionfilec4mtram72x8_wrapper.v:RAMwrapperfilec4mtram72x8_rb.v:BISTRTLfilec4mtram72x8_sim.v:BISTsimulationtestbenchfilec4mtram72x8.scp:Synopsyssynthesisscriptfilec4mtram72x8.bist.rpt:Reportfile=======ENDSRAMBISTREPORTFILE=======March13NMovingInversionAlgorithmfaultmodelMarchElementsBISTConfigurationFile.BCF.BCFBISTBISTclockBISTTclkBISTclockclockBISTclockRLT2)SynchronousROMSpecification(c4msrom0101)MemoryAttributes:Worddepth:2048Addresswidth:11Wordwidth:12Smalladdress:11b00000000000Maximumaddress11b11111111111Numberofports:singleportMemoryPortAttributes:Porttype:ReadAddresssignal:ADataoutsignal:OClocksignal:CLKwithpositiveedgetriggerOutputenablesignal:OE,activehighzoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com6Mar.2003DFTBISTConstraintSynchronousreset:TrueClockcycle:20nsTimescale:1ns/10psRomcontentfile:romdatac4msrom0101.mdf%GLOBAL{%TIMESCALE1ns/10ps;%SYNC_RESETTRUE;%CLK_CYCLE20;%BIST_CLK_TRIGGERposedge;}%MEMORYc4msrom0101{%TIMESCALE1ns/10ps;%TYPEROM;%DATA_BITS12;%ADDR_BITS11;%LOW_ADDR11b00000000000;%HIGH_ADDR11b11111111111;%CLOCKCLK;%LATENCY0;%ROM_CONTENT_FILEromdata;%PORTR{%TYPEr;%ADDRESSA;%DATA_OUTO;%OUTPUT_ENOE;}}ROMtypeROMROMsrambistc4msrom010zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com7Mar.2003============SYNTESTSRAMBISTREPORTFILE============TOOL:srambistV1.1.0r01(08/15/0016:30:26)TIME:WedMar1508:27:372002OPTIONSSELECTED:NUMBEROFMEMORIES:1THECLOCKBEINGUSEDASTHEBISTCLOCK:BistClockPort:[CLK]BISTCLOCKTRIGGERING:negativetriggeredclock.TOTALBISTCYCLES:2052ROMMISRINFORMATIONS:MISR_BITS,MISR_POLY,MISR_SEEDS,SIGNATUREROM[c4msrom0101]:MISRBITS:[23]MISRPOLY:[X^23+X^5+1]MISRSEEDS[ReportedMISRseedsarefromMSBtoLSB]:[10010101011100001010011]MISRSIGNATURE[ReportedsignaturesarefromMSBtoLSB]:[11011010111100010111011]SRAMBISTROMBISTROMROMMISRsignatureROMROMBISTMISR23bitsx^23+x^5+1MISRseedsignatureMISRzoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com8Mar.2003DFTMEMORYMISR_BITS2020bitsBISTSynTestScanInsertionATPGTurboScanDFTDFTgatelevelnetlistSynTestTurboCheck-RTLRTLDFTSynTestTurboScancelllibrarySynTestdatabasesdbSynTestsdblibraryDFTDFTasic123gatelevelDFTviolationTurboScanscanselscanelementsscanelementsscanchain.pso.psoscanelementsscansynscanchainFlip-FlopScanFlip-FlopscanchainscaninsertionATPGasicgentestpatternVerilogscaninsertionlsdbVerilognetlistphysicallayoutSynTeststanddelayformattimingtimingscaninsertionlayouttiming.sdfCICcelllibrarySynTestsdbCICTurboScansymboliclinksdblibraryDFTnetlistscancellRTLscancellscanselscansynFlip-Flopscancellsdblibrary.mapFlip-FlopScanFlip-Flopcellbuffermultiplexer.mapCICzoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com9Mar.2003RTLDesignRTLDRCSynthesisGate-LevelNetlistTestabilityAnalysisDFTPlansdblibraryDFTRuleViolationScanSelectionScanInsertionNetlistGenerationATPGFaultSimulationPatternTranslationDFTedDesignVerificationPatternMismatchUsedTool/CommandTurboCheck-RTLscanselscansynlsdbasicgenasicgentpoutTurboCheck-Gateasic123DFT.dftFreeRISC8.dft//TestabilityAnalysisconstraints%TA_CONSTRAINTS{%CLOCKI_CLK=010;%FORCEI_RESET=000;}//DefineascanchainwithtypeMDFFandnamechain_1%CONNECT_SCANchain1MDFFReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com10Mar.2003DFT{%SCAN_PAD{%SDI_PAD_NAME=PAD_PORTAIN00;%SDO_PAD_NAME=PAD_PORTBOUT00;%SDI_PAD_OUT=CIN;%SDO_PAD_IN=I;}%SCAN_PORT{%SCAN_IN=I_PORTAIN[0];%SCAN_OUT=O_PORTBOUT[0];%DEFAULT=SCAN;}%SCAN_CLOCK_1{%CLOCK=I_CLK;%GLOBAL_CLOCK=clk;}%SCAN_INSTANCES_FILE{%FILE_NAME=sel/top.sel1.pso;}%SCAN_INSTRUCTION{%INSTRUCTION=instruction1;}//DefineascanchainwithtypeMDFFandnamechain_2%CONNECT_SCANchain2MDFF{..........................................}%SEQUENCEshift_seq{ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com11Mar.2003%FORCEI_CLK=010;%FORCEI_RESET=000;%FORCEI_SCAN_EN=111;}%SEQUENCEhold_seq{%FORCEI_CLK=000;%FORCEI_RESET=000;%FORCEI_SCAN_EN=000;}%SEQUENCEcapture_seq{%FORCEI_CLK=010;%FORCEI_RESET=000;%FORCEI_SCAN_EN=000;}%INSTRUCTIONinstruction1{%MODE=scan;%SHIFT=shift_seq;%HOLD=hold_seq;%CAPTURE=capture_seq;}%SCAN_DECODER{%SCAN_MODE{%PORT_NAME=I_SCAN_EN;}%TEST_MODE{%PORT_NAME=I_TEST_EN;}}%READ_MAP{%FILE_NAME=top.map;ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com12Mar.2003DFT}%ATPG_CONSTRAINTS{%ATPG_MODEFULL_SCAN{%FORCEI_RESET=0;%FORCEI_CLK=0;}}%TA_CONSTRAINTSconstraintsclockresetscanchain%CONNECT_SCANchain1MDFFscanpadscanportscanclockscaninstance(.pso)scanselscaninstructionscaninstruction%SEQUENCEshiftholdcaptureshiftscanchaincaptureresponsescanchainholdscanchainFlip-Flopresponsecapturescanchain%SCAN_DECODERscandecoderportscansynscanchainscanscandecoder%READ_MAP.map%ATPG_CONSTRAINTSATPGholdsequencerunscriptSynTestTurboScan1st.ln-s/cad2/lib/CIC_CBDK35_V3/Syntest/liblib2nd.mkdirdesigns123selsynfsimfscan3rd.vlogin-odesignsnetsrc/top.v4th.expintop5th.asic123top-o123/top6th.scansel-fscantop-osel/top-scan_chain2-balance7th.scansyn-fscantop-osyn/topzoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com13Mar.20038th.lsdbtop_s0-verilog-hierarchy-timescale-otop_s0.v9th.asicgen-post_fscantop_s0-ofscan/top_s010th.asicgen-fsim-post_fscan-stm_filefscan/top_s0.tptop_s0-ofsim/top_s011th.tpout-vlog-fscan-int_filefscan/top_s0.int-tp_filefscan/top_s0.tptop_s0Step1.symboliclinksdblibraryStep2.designssdb123selscanelements.psosynscaninsertionfsimfaultsimulationfscanATPGfaultsStep3.VeriloggatelevelnetlistSynTestdatabasesdbdesignsStep4.Linkexpand(flatten)Step5.123============ASIC123V2.4.0(06/13/01126)Solaris============****CIRCUITSTATISTICS****Numberofinputpins...................................=19Numberofoutputpins................................=79Numberofbidirectionalpins....................=0Numberofaccessibleobjects...................=3908Numberofaccessiblenets.........................=3914Numberofdelayobjects............................=0Numberofinserteddelayobjects...........=0Numberofaccessibleflip-flops................=182Numberofaccessiblelatches...................=0NumberofaccessibleRAMs/ROMs.........=0Totalaccessiblememoryelements.........=182Numberofinaccessibleflip-flops............=0Numberofinaccessiblelatches................=0NumberofinaccessibleRAMs/ROMs.....=0Totalinaccessiblememoryelements.....=0ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com14Mar.2003DFTIOmemoryelementsFlip-FlopaccessaccessscanchaincellDFTgatedclockStep6.scanselectionFlip-Flopscan-chainchainscanchain.psocell.pso//--Scanchain:1//--Scaninstancenumber=91//--Scanclock=+I_CLK.//--Synchronousclock=+I_CLK.//---//clockparity:+I_CLK(2)MUST_SCAN7510comb.cpu.fsr_reg_0_;..........................................MUST_SCAN9398comb.cpu.inst_reg_8_;Step7..psoscaninsertionFlip-FlopScanFlip-FlopscanchainCircuitName:topNewCircuitName:top_s0ScanDecoderCell:SCAN_DECODER_CLASSScanInPortName:Chain1->I_PORTAIN[0]Chain2->I_PORTAIN[1]ScanOutPortName:Chain1->O_PORTBOUT[0]Chain2->O_PORTBOUT[1]AddedControlPort:I_SCAN_ENSynthesisStatus-------------------------------------------------ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com15Mar.2003ReplacedMemoryCells:182InsertedMUX(mx02d1):2DRCErrorStatus------------------------------------SetErrorFound:0Fixed:0Skiped:0ResetErrorFound:0Fixed:0Skiped:0ScanDecoderControlTable------------------------------------------Sequence|I_SCAN_EN------------------------------------------Normal|0Shift|1Hold|XCapture|X------------------------------------------------------------------------------------ScanChainStatus:Succeed!------------------------------------------Step8.scaninsertionSynTestdatabaseVerilognetlsitStep9.scaninsertionATPGfscanfaultcoveragefaults10010faultsfaultscollapsedfaultscollapsed6193109faultsHarddetected(HD)Potentiallytestable(PT)clockenablefaultsPotentiallyuntestale(PU)faultsUntestable(UT)zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com16Mar.2003DFTTiedtoVCC/GNDUncontrollableUnobservableduetocircuitdesign100faultsblockfaultsuncontrollableunobservablefaultcoveragefaultcoverageWrapperFlip-Flopfaultcoverageuncollapsedfaultsnetlistfaultsfaultcoverage88.9126%===========ASICGENV2.4.0(06/13/01150)Solaris=======Creatingcapturemodeinformation...6193collapsedand10010uncollapsedfaultsNo.ofTotalScanelementis:1825394Harddetectedfaultsaresavedin`fscan/top_s0.hdt.793Redundantfaultsaresavedin`fscan/top_s0.red.6Abortedfaultsaresavedin`fscan/top_s0.udt.Thiscircuithas109testpatternsandcontains6193faultsofwhich5394(87.10%)faultswereHarddetected(HD).0(0.00%)datafaultswerePotentiallytestable(PT).0(0.00%)clock/enablefaultswerePotentiallyuntestable(PU).102(1.65%)Untestable(UT)faultswereTiedtoVCC/GND(IG).159(2.57%)Untestable(UT)faultswereUncontrollable.406(6.56%)Untestable(UT)faultswereBlocked(Unobservable).126(2.03%)Untestable(UT)faultswereduetocircuitdesign.0(0.00%)clock/enablefaultswereAbortedforbacktrackcountexceeding100.6(0.10%)datafaultswereAbortedforbacktrackcountexceeding100.atpgpessimisticfaultcoverage=HD/(Total-IG)=88.5569%.atpgpessimistictestcoverage=HD/(Total-UT)=99.8889%.atpgpessimistictestefficiency=(HD+UT)/Total=99.9031%.atpgoptimisticfaultcoverage=(HD+PT)/(Total-IG)=88.5569%.zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin高亮zoushiyin线条zoushiyin线条zoushiyin线条zoushiyin线条ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com17Mar.2003atpgoptimistictestcoverage=(HD+PT)/(Total-UT-PU)=99.8889%.atpgoptimistictestefficiency=(Total-Abort)/Total=99.9031%.Thiscircuithas109testpatternsandcontains10010UNCOLLAPSEDfaultsofwhich8741(87.32%)faultswereHarddetected(HD).0(0.00%)datafaultswerePotentiallytestable(PT).0(0.00%)clock/enablefaultswerePotentiallyuntestable(PU).179(1.79%)Untestable(UT)faultswereTiedtoVCC/GND(IG).284(2.84%)Untestable(UT)faultswereUncontrollable.594(5.93%)Untestable(UT)faultswereBlocked(Unobservable).204(2.04%)Untestable(UT)faultswereduetocircuitdesign.0(0.00%)clock/enablefaultswereAbortedforbacktrackcountexceeding100.8(0.08%)datafaultswereAbortedforbacktrackcountexceeding100.atpgpessimisticfaultcoverage=HD/(Total-IG)=88.9126%.atpgpessimistictestcoverage=HD/(Total-UT)=99.9086%.atpgpessimistictestefficiency=(HD+UT)/Total=99.9201%.atpgoptimisticfaultcoverage=(HD+PT)/(Total-IG)=88.9126%.atpgoptimistictestcoverage=(HD+PT)/(Total-UT-PU)=99.9086%.atpgoptimistictestefficiency=(Total-Abort)/Total=99.9201%.Step10.faultsimulationfaultcoveragefaultsduetocircuitdesignfaultsPotentiallytestable(PT)faultcoverageCIC92FaultCoverage,FCSynTestfaultsimulationStep11.6ATPGVerilogGatecountBISTFlip-FlopScanFlip-Flopoverhead1.78%layoutclocktreescanchainTimingSlackclock20nsScanInsertionScanFlip-zoushiyin线条zoushiyin线条zoushiyin文本框save....vzoushiyin线条zoushiyin线条zoushiyin矩形ReprintCopyright©2001byChip123TechnologyCo.,Ltd.Allrightsreservedwww.chip123.comchip123@chip123.comISSN1609-8633ICDESIGNMAGAZINEVOLUME35www.Chip123.com18Mar.2003DFTFlopmultiplexerdelaySynTestDFTtimingconstraintsScanInsertionCICSynTestDFTCICeNewsSynopsysDFTGateCountTimingSlackFaultCoverageNumberofPatternsOri.DFTedNumberofFlip-FlopsOri.DFTed88.9126%10984042855381820.04ns-0.55nszoushiyin矩形zoushiyin高亮