74LS191

TL/F/6405 D M 5 4 L S 1 9 0 / D M 7 4 L S 1 9 0 , D M 5 4 L S 1 9 1 / D M 7 4 L S 1 9 1 S y n c h ro n o u s 4 -B it U p / D o w n C o u n te rs w ith M o d e C o n tro l May 1989 DM54LS190/DM74LS190, DM54LS191/DM74LS191 Synchronous 4-Bit Up/Down Counters with Mode Control General Description These circuits are synchronous, reversible, up/down coun- ters. The LS191 is a 4-bit binary counter and the LS190 is a BCD counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input, if the enable input is low. A high at the enable input inhibits count- ing. Level changes at either the enable input or the down/ up input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter counts up and when high, it counts down. These counters are fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock in- put. This feature allows the counters to be used as modulo- N dividers by simply modifying the count length with the preset inputs. The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the num- ber of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cas- cading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accom- plish look-ahead for high-speed operation. Features Y Counts 8-4-2-1 BCD or binary Y Single down/up count control line Y Count enable control input Y Ripple clock output for cascading Y Asynchronously presettable with load control Y Parallel outputs Y Cascadable for n-bit applications Y Average propagation delay 20 ns Y Typical clock frequency 25 MHz Y Typical power dissipation 100 mW Connection Diagram Dual-In-Line-Package TL/F/6405-1 Order Number DM54LS190J, DM54LS191J, DM54LS190W, DM54LS191W, DM74LS190M, DM74LS191M, DM74LS190N, or DM74LS191N See NS Package Number J16A, M16A, N16A or W16A C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range DM54LS b55§C to a125§C DM74LS 0§C to a70§C Storage Temperature Range b65§C to a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter DM54LS190, LS191 DM74LS190, LS191 Units Min Nom Max Min Nom Max VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V VIH High Level Input Voltage 2 2 V VIL Low Level Input Voltage 0.7 0.8 V IOH High Level Output Current b0.4 b0.4 mA IOL Low Level Output Current 4 8 mA fCLK Clock Frequency (Note 4) 0 20 0 20 MHz tW Pulse Width Clock 25 25 ns (Note 4) Load 35 35 tSU Data Setup Time (Note 4) 20 20 ns tH Data Hold Time (Note 4) 0 0 ns tEN Enable Time to Clock (Note 4) 30 30 ns TA Free Air Operating Temperature b55 125 0 70 §C ’LS190 and ’LS191 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 1) VI Input Clamp Voltage VCC e Min, II e b 18 mA b1.5 V VOH High Level Output VCC e Min, IOH e Max DM54 2.5 3.4 Voltage VIL e Max, VIH e Min DM74 2.7 3.4 V VOL Low Level Output VCC e Min, IOL e Max DM54 0.25 0.4 Voltage VIL e Max, VIH e Min DM74 0.35 0.5 V IOL e 4 mA, VCC e Min DM74 0.25 0.4 II Input Current @ Max VCC e Max Enable 0.3 mA Input Voltage VI e 7V Others 0.1 IIH High Level Input VCC e Max Enable 60 mA Current VI e 2.7V Others 20 IIL Low Level Input VCC e Max Enable b1.08 mA Current VI e 0.4V Others b0.4 IOS Short Circuit VCC e Max DM54 b20 b100 mA Output Current (Note 2) DM74 b20 b100 ICC Supply Current VCC e Max (Note 3) 20 35 mA Note 1: All typicals are at VCC e 5V, TA e 25§C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all inputs grounded and all outputs open. Note 4: TA e 25§C and VCC e 5V. 2 ’LS190 and ’LS191 Switching Characteristics at VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load) From (Input) RL e 2 kX Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units Min Max Min Max fMAX Maximum Clock 20 20 MHz Frequency tPLH Propagation Delay Time Load to 33 43 ns Low to High Level Output Any Q tPHL Propagation Delay Time Load to 50 59 ns High to Low Level Output Any Q tPLH Propagation Delay Time Data to 22 26 ns Low to High Level Output Any Q tPHL Propagation Delay Time Data to 50 62 ns High to Low Level Output Any Q tPLH Propagation Delay Time Clock to 20 24 ns Low to High Level Output Ripple Clock tPHL Propagation Delay Time Clock to 24 33 ns High to Low Level Output Ripple Clock tPLH Propagation Delay Time Clock to 24 29 ns Low to High Level Output Any Q tPHL Propagation Delay Time Clock to 36 45 ns High to Low Level Output Any Q tPLH Propagation Delay Time Clock to 42 47 ns Low to High Level Output Max/Min tPHL Propagation Delay Time Clock to 52 65 ns High to Low Level Output Max/Min tPLH Propagation Delay Time Up/Down to 45 50 ns Low to High Level Output Ripple Clock tPHL Propagation Delay Time Up/Down to 45 54 ns High to Low Level Output Ripple Clock tPLH Propagation Delay Time Down/Up to 33 36 ns Low to High Level Output Max/Min tPHL Propagation Delay Time Down/Up to 33 42 ns High to Low Level Output Max/Min tPLH Propagation Delay Time Enable to 33 36 ns Low to High Level Output Ripple Clock tPHL Propagation Delay Time Enable to 33 42 ns High to Low Level Output Ripple Clock 3 Logic Diagrams LS190 Decade Counters Pin (16) e VCC, Pin (8) e GND TL/F/6405–2 4 Logic Diagrams (Continued) LS191 Binary Counters Pin (16) e VCC, Pin (8) e GND TL/F/6405–3 5 Timing Diagrams LS190 Decade Counters Typical Load, Count, and Inhibit Sequences TL/F/6405–4 LS191 Binary Counters Typical Load, Count, and Inhibit Sequences TL/F/6405–5 6 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS190J, DM54LS191J NS Package Number J16A 16-Lead Small Outline Molded Package (M) Order Number DM74LS190M, DM74LS191M NS Package Number M16A 7 D M 5 4 L S 1 9 0 / D M 7 4 L S 1 9 0 , D M 5 4 L S 1 9 1 / D M 7 4 L S 1 9 1 S y n c h ro n o u s 4 -B it U p / D o w n C o u n te rs w it h M o d e C o n tr o l Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS190N, DM74LS191N NS Package Number N16E 16-Lead Ceramic Flat Package (W) Order Number DM54LS190W or DM54LS191W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. 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