数字逻辑课程设计VHDL数字逻辑课程设计报告

VHDL数字逻辑课程设计 报告 软件系统测试报告下载sgs报告如何下载关于路面塌陷情况报告535n,sgs报告怎么下载竣工报告下载 多功能数字电子钟 院 系: 计算计学院 班 级：计081—3 学 号：200825501309 姓 名: 杨长进 指导老师：王玲玲 实验地点: 理工楼334室 实验日期： 各模块的具体分析： 1总体模块： 2、分频器模块 （1）模块说明：用clk、reset实现对分频器的控制，输入频率为1024HZ的信号源，运用计数器原理产生各种需要的频率脉冲。 （2）模块图 （3）仿真图 （4）源程序代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith; use ieee.std_logic_unsigned.all; entity fdiv is port(clk: in std_logic; reset: in std_logic; f0,f512,f1:out std_logic); end fdiv; architecture rtl of fdiv is signal q: std_logic_vector(9 downto 0); begin process(clk,reset) begin if reset='0'then q<="0000000000"; elsif (rising_edge(clk)) then if q="1111111111" then q<="0000000000"; else q<=q + 1; end if; end if; end process; f0<=clk;f512<=q(0); f1<=q(9); end rtl; 三、校时控制模块 校时模块用tiaoh,tiaom来实现对时、分、秒的校时控制，Reset是对整个块的控制，使其是否工作。当无控制信号输入时则正常计时。 其中底层的模块图 主体是由一个24进制、两个60进制的计数器构成，并通过两个二选一选择器实现计时功能。当tiaoh,tiaom中无信号输入时，各计数器正常计数，当tiaoh,tiaom中有信号时，由二选一选择f1的频率校时。Reset控制整个模块是否工作。 二十四进制仿真图 六十进制仿真图 二选一仿真图 （4）源程序代码 模六十进制： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count60 is port(clk,clr: in std_logic; en:in std_logic; ql: out std_logic_vector(3 downto 0); qh: out std_logic_vector(3 downto 0); co: out std_logic); end count60; architecture act60 of count60 is signal qcl: std_logic_vector(3 downto 0); signal qch: std_logic_vector(3 downto 0); begin process(clk) begin if(clr='0') then qcl<="0000";qch<="0000"; elsif(clk'event and clk='1')then ----co<='0'; if(en='1' and qch="0101" and qcl="1001")then qcl<="0000";qch<="0000";co<='1'; elsif(en='1' and qcl="1001")then qch<=qch+'1'; qcl<="0000"; co<='0'; else qcl<=qcl+'1'; co<='0'; end if; end if; qh<=qch; ql<=qcl; end process; end act60; 模24进制： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count_24 is port(clk,clr: in std_logic; ql: out std_logic_vector(0 to 3); qh: out std_logic_vector(0 to 3); co: out std_logic); end count_24; architecture act24 of count_24 is signal qcl: std_logic_vector(0 to 3); signal qch: std_logic_vector(0 to 3); begin process(clk) begin if(clr='0') then qcl<="0000";qch<="0000"; elsif(clk'event and clk='1')then --co<='0'; if(qch="0010" and qcl="0011")then qcl<="0000";qch<="0000";co<='1'; elsif(qcl="1001")then qch<=qch+'1';qcl<="0000"; co<='0'; else qcl<=qcl+'1'; co<='0'; end if; end if; qh<=qch; ql<=qcl; end process; end act24; 二选一： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count_24 is port(clk,clr: in std_logic; ql: out std_logic_vector(0 to 3); qh: out std_logic_vector(0 to 3); co: out std_logic); end count_24; architecture act24 of count_24 is signal qcl: std_logic_vector(0 to 3); signal qch: std_logic_vector(0 to 3); begin process(clk) begin if(clr='0') then qcl<="0000";qch<="0000"; elsif(clk'event and clk='1')then --co<='0'; if(qch="0010" and qcl="0011")then qcl<="0000";qch<="0000";co<='1'; elsif(qcl="1001")then qch<=qch+'1';qcl<="0000"; co<='0'; else qcl<=qcl+'1'; co<='0'; end if; end if; qh<=qch; ql<=qcl; end process; end act24; 4、蜂鸣器模块 （1）模块说明：该模块既实现了整点报时的功能，又实现了闹铃的功能，通过所选频率的不同，而发出大小不同的声响。 （2）模块图 （3）仿真图 （4）源代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bel is port(tm1,ts1,tm0,ts0:in std_logic_vector(3 downto 0); f512,f1024:in std_logic; bell:out std_logic); end bel; architecture rtl of bel is signal t:std_logic_vector(7 downto 0); begin process(tm1,tm0,ts1) begin if (tm1="0101" and tm0="1001"and ts1="0101")then case ts0 is when"0001"=>bell<=f512; when"0011"=>bell<=f512; when"0101"=>bell<=f512; when"0111"=>bell<=f512; when"1001"=>bell<=f1024; when others=>bell<='0'; end case; end if; end process; end rtl; 5、动态显示电路 （1）模块说明：是一个8位的动态扫描数码显示器，由显示控制电路提供数据源，其中包括有八进制计数器、3：8译码器、BCD\七段数字显示译码器、8选1多路数据选择器的模块。 （2）模块图 底层文件模块 3）仿真图 动态扫描数码显示器的整体仿真 M_8计数器的仿真图 8:1选择器 源代码： 八选一： library ieee; use ieee.std_logic_1164.all; entity mux8_1 is port(d0,d1,d2,d3,d4,d5,d6,d7: in std_logic_vector(3 downto 0); sel:in std_logic_vector(2 downto 0); y2: out std_logic_vector(3 downto 0)); end mux8_1; architecture rtl of mux8_1 is begin process(d0,d1,d2,d3,d4,d5,d6,d7,sel) begin case sel is when"000"=>y2<=d0; when"001"=>y2<=d1; when"010"=>y2<=d2; when"011"=>y2<=d3; when"100"=>y2<=d4; when"101"=>y2<=d5; when"110"=>y2<=d6; when"111"=>y2<=d7; when others=>y2<="1111"; end case; end process; end rtl; 八进制计数器代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity m_8 is port(clk,clr:in std_logic; en:in std_logic;--'1'--count '0'---keep ql:out std_logic_vector(2 downto 0); co:out std_logic); end m_8; architecture act8 of m_8 is signal qcl:std_logic_vector(2 downto 0); begin process(clk) begin if(clr='1')then qcl<="000"; elsif(clk'event and clk='1')then if(en='1')then if(qcl="111")then qcl<="000"; co<='1'; else qcl<=qcl+'1';co<='0'; end if; end if; end if; end process; ql<=qcl; end act8; 3：8译码器代码 library ieee; use ieee.std_logic_1164.all; entity yima3_8 is port(a,b,c :in std_logic; g1,g2a,g2b :in std_logic; y :out std_logic_vector(7 downto 0)); end yima3_8; architecture rtl of yima3_8 is signal ind:std_logic_vector(2 downto 0); begin ind<=c&b&a; process(ind,g1,g2a,g2b) begin if (g1='1' and g2a='0' and g2b='0')then case ind is when"000"=>y<="10000000"; when"001"=>y<="01000000"; when"010"=>y<="00100000"; when"011"=>y<="00010000"; when"100"=>y<="00001000"; when"101"=>y<="00000100"; when"110"=>y<="00000010"; when"111"=>y<="00000001"; when others=>y<="00000000"; end case; else y<="11111111"; end if; end process; end rtl; BCD\七段数字显示译码器代码 library ieee; use ieee.std_logic_1164.all; entity m4_7 is port(y1:out std_logic_vector(6 downto 0); s:in std_logic_vector(3 downto 0)); end m4_7; architecture rtl of m4_7 is begin process(s) begin case s is when"0000"=>y1<="1111110"; when"0001"=>y1<="0110000"; when"0010"=>y1<="1101101"; when"0011"=>y1<="1111001"; when"0100"=>y1<="0110011"; when"0101"=>y1<="1011011"; when"0110"=>y1<="1011111"; when"0111"=>y1<="1110000"; when"1000"=>y1<="1111111"; when"1001"=>y1<="1111011"; when"1011"=>y1<="0000001"; when others=>y1<="0000000"; end case; end process; end rtl;