24C512完全手册（可编辑）

24C512完全手册（可编辑） 24C512完全手册 Atmel AT24C512C 2 I C-Compatiable 2-wire Serial EEPROM 512-Kbit 65536 x 8 DATASHEET Features Low-voltage and standard-voltage operation 17V VCC 17V to 36V 25V VCC 25V to 55V Internally organized as 65536 x 8 2-wire serial interface Schmitt Triggers filtered inputs for noise suppression Bidirectional data transfer protocol 400kHz 17V and 1MHz 25V 55V compatibility Write Protect pin for hardware data protection 128-byte page write mode partial page writes allowed Random and sequential read modes Self-timed write cycle 5ms High reliability Endurance 1000000 write cycles Data retention 40 years Green package options PbHalide-freeRoHS Compliant 8-lead JEDEC SOIC 8-lead EIAJ SOIC 8-lead TSSOP 8-pad UDFN 8-ball WLCSP and 8-ball VFBGA packages Die sale options wafer form and tape and reel available Description The Atmel AT24C512C provides 524288 bits of Serial Electrically Erasable and Programmable Read-Only Memory EEPROM organized as 65536 words of eight bits each The cascadable feature of the device allows up to eight devices to share a common 2-wire bus The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential The devices are available in space-saving 8-lead JEDEC SOIC 8-lead EIAJ SOIC 8-lead TSSOP 8-pad UDFN 8-ball WLCSP and 8-ball VFBGA packages In addition the entire family is available in 17V 17V to 36V and 25V 25V to 55V versions Atmel-8720D-SEEPROM-AT24C512C-Datasheet_037>2013 1 Pin Configurations and Pinouts Figure 1 Pin Configurations Pin Name Function 8-lead SOIC 8-lead TSSOP A - A Address Inputs A 1 8 V 0 2 0 CC A0 1 8 VCC GND Ground A1 2 7 WP A1 2 7 WP A2 3 6 SCL SDA Serial Data A2 3 6 SCL GND 4 5 SDA GND 4 5 SDA SCL Serial Clock Input WP Write Protect 8-pad UDFN 8-ball WLCSP VCC Power Supply VCC 8 1 A0 VCC SDA SCL WP 7 2 A1 WP A2 SCL 6 3 A2 A1 SDA 5 4 GND A0 GND Bottom View Bottom View 8-ball VFBGA VCC 8 1 A0 WP 7 2 A1 Note Drawings are not to scale SCL 6 3 A2 SDA 5 4 GND Bottom View 2 Absolute imum Ratings Operating Temperature 55?C to 125?C Notice Stresses beyond those– listed under Absolute imum Ratings may cause permanent damage Storage Temperature 65?C to 150?C to the device This is– a stress rating only and functional operation of the device at these or any Voltage on any pin other conditions beyond those indicated in the with respect to ground –10V to 70V operational sections of this specification is not imum Operating Voltage 625V implied Exposure to absolute imum rating conditions for extended periods may affect device DC Output Current 50mA reliability Atmel AT24C512C [DATASHEET] 2 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 3 Block Diagram V CC GND WP SCL Start Stop SDA Logic Serial EN Control HV PumpTiming Logic LOAD Device COMP Data Recovery Address Comparator LOAD INC A 2 A RW Data Word C 1 E EEPROM A0 Addrcounter D X Y DEC Serial MUX DIN DOUTACK Logic D OUT 4 Pin Descriptions Serial Clock SCL The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device Serial Data SDA The SDA pin is bidirectional for serial data transfer This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices Device Addresses A A A The A A and A pins are device address inputs that are hardwired or left not 2 1 0 2 1 0 connected for compatibility with other Atmel AT24Cxx devices When the pins are hardwired as many as eight 512K devices may be addressed on a single bus system see Section 7 Device Addressing on page 9 for more details If these pins are left floating the A A and A pins will be internally pulled down to GND However due to capacitive 2 1 0 coupling that may appear during customer applications Atmel recommends always connecting the address pins to a known state When using a pull-up resistor Atmel recommends using 10k or less Write Protect WP The Write Protect input when connected to GND allows normal write operations When WP pin is connected directly to VCC all write operations to the memory are inhibited If the pin is left floating the WP pin will be internally pulled down to GND however due to capacitive coupling that may appear during customer applications Atmel recommends always connecting the WP pin to a known state When using a pull-up resistor Atmel recommends using 10k or less Table 4-1 Write Protect Part of the Array Protected WP Pin Status Atmel AT24C512C At VCC Full Array At GND Normal ReadWrite Operations Atmel AT24C512C [DATASHEET] 3 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 5 Memory Organization Atmel AT24C512C 512-Kbit Serial EEPROM The 512K is internally organized as 512 pages of 128 bytes each Random word addressing requires a 16-bit data word address Table 5-1 Pin Capacitance 1 Applicable over recommended operating range from TA 25C f 10MHz VCC 55V Symbol Test Condition Units Conditions CIO InputOutput Capacitance SDA 8 pF VIO 0V C Input Capacitance A A A SCL 6 pF V 0V IN 0 1 2 IN Note 1 This parameter is characterized and is not 100 tested Table 5-2 DC Characteristics Applicable over recommended operating range from TAI 40C to 85C VCC 17V to– 36V or 25V to 55V unless otherwise noted Symbol Parameter Test Condition Min Typ Units VCC1 Supply Voltage 17 36 V VCC2 Supply Voltage 25 55 V ICC1 Supply Current VCC 50V Read at 400kHz 20 mA ICC2 Supply Current VCC 50V Write at 400kHz 30 mA VCC 17V 10 μA ISB1 Standby Current VIN VCC or VSS VCC 36V 30 μA VCC 25V 20 μA ISB2 Standby Current VIN VCC or VSS VCC 55V 60 μA ILI Input Leakage Current VIN VCC or VSS 010 30 μA Output Leakage ILO Current VOUT VCC or VSS 005 30 μA VIL Input Low Level 1 06– VCC x 03 V VIH Input High Level 1 VCC x 07 VCC 05 V VOL1 Output Low Level VCC 17V IOL 015mA 02 V VOL2 Output Low Level VCC 30V IOL 21mA 04 V Note 1 V min and V are reference only and are not tested IL IH Atmel AT24C512C [DATASHEET] 4 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 Table 5-3 AC Characteristics Applicable over recommended operating range from TAI -40C to 85C VCC 17V to 36V or 25V to 55V where applicable CL 100pF unless otherwise noted Test conditions are listed in Note 2 17V 25V 50V Symbol Parameter Min Min Units fSCL Clock Frequency SCL 400 1000 kHz tLOW Clock Pulse Width Low 13 04 μs tHIGH Clock Pulse Width High 06 04 μs tI Noise Suppression Time 1 100 50 ns tAA Clock Low to Data Out Valid 005 09 005 055 μs Time the bus must be free before a new tBUF transmission can start 1 13 05 μs tHDSTA Start Hold Time 06 025 μs tSUSTA Start Set-up Time 06 025 μs tHDDAT Data In Hold Time 0 0 μs tSUDAT Data In Set-up Time 100 100 ns tR Inputs Rise Time 1 03 03 μs tF Inputs Fall Time 1 300 100 ns tSUSTO Stop Set-up Time 06 025 μs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time 5 5 ms Endurance 1 25?C Page Mode 33V 1000000 Write Cycles Notes 1 This parameter is ensured by characterization only 2 AC measurement conditions R connects to V 13k 25V 5V 10k 17V L CC Input pulse voltages 03VCC to 07VCC Input rise and fall times 50ns Input and output timing reference voltages 05VCC Atmel AT24C512C [DATASHEET] 5 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 6 Device Operation Clock and Data Transitions The SDA pin is normally pulled high with an external device Data on the SDA pin may change only during SCL low time periods see Figure 6-4 on page 8 Data changes during SCL high periods will indicate a Start or Stop condition as defined below Start Condition A high-to-low transition of SDA with SCL high is a Start condition which must precede any other command see Figure 6-5 on page 8 Stop Condition A low-to-high transition of SDA with SCL high is a Stop condition After a read sequence the stop command will place the EEPROM in a standby power mode see Figure 6-5 on page 8 Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word see Figure 6-6 on page 8 Standby Mode The AT24C512C features a low-power standby mode which is enabled Upon power-up and After the receipt of the Stop bit and the completion of any internal operations Software Reset After an interruption in protocol power loss or system reset any 2-wire part can be protocol reset by following these steps 1 Create a Start condition 2 Clock nine cycles 3 Create another Start condition followed by a Stop condition as shown in Figure 6-1 below The device is ready for the next communication after the above steps have been completed Figure 6-1 Software Reset Dummy Clock Cycles SCL 1 2 3 8 9 Start Start Stop Bit Bit Bit SDA Atmel AT24C512C [DATASHEET] 6 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 Figure 6-2 Bus Timing SCL Serial Clock SDA Serial Data IO t HIGH t t F R t t LOW LOW SCL t t t t t SUSTA HDSTA HDDAT SUDAT SUSTO SDA IN t t t AA DH BUF SDA OUT Figure 6-3 Write Cycle Timing SCL Serial Clock SDA Serial Data IO SCL SDA 8th Bit ACK WORD N 1 t WR Stop Start Condition Condition Notes 1 The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal clearwrite cycle Atmel AT24C512C [DATASHEET] 7 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 Figure 6-4 Data Validity SDA SCL Data Stable Data Stable Data Change Figure 6-5 Start and Stop Definition SDA SCL Start Stop Figure 6-6 Output Acknowledge SCL 1 8 9 Data In Data Out Start Acknowledge Atmel AT24C512C [DATASHEET] 8 Atmel-8720D-SEEPROM-AT24C512C-Datasheet_032013 7 Device Addressing The 512K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a read or write operation The device address word consists of a mandatory 1010 sequence for the first four most-significant bits see Figure 7-1 below This is common to all 2-wire EEPROM devices The 512K uses the three device address bits A2 A1 and A0 to allow as many as eight devices on the same bus These bits must compare to their corresponding hardwired input pins The A A and A pins use an internal proprietary circuit 2 1 0 that biases them to a logic low condition if the pins are allowed to float The eighth bit of the device address is the readwrite operation select bit A read operation is initiated if this bit is high and a write operation is initiated if this bit is low Upon a compare of the device address the EEPROM will output a zero If a valid compare is not made the device will return to a standby state Figure 7-1 Device Address 1 0 1 0 A2 A1 A0 RW MSB LSB 8 Write Operations Byte Write A Byte Write operation requires two 8-bit data word addresses following the device address word and acknowledgment Upon receipt of this address the EEPROM will again respond with a zero and then the part is to receive an 8-bit data word Following receipt of the 8-bit data word the EEPROM will output a zero The addressing device such as a microcontroller then must terminate the write sequence with a Stop condition At this time the EEPROM enters an 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