主板电路图915GM_ICH6

A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet o f LA-2592 0.3 Cover Sheet 1 46Monday, February 21, 2005 Compal Electronics, Inc. Custom THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Compal confidential REV:0.3 Mobile Dothan uFCPGA with Intel Alviso_GM+ICH6-M core logic Schematics Document LA-2592 2005-02-15 A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet o f LA-2592 0.3 Block Diagram 2 46Tuesday, February 15, 2005 Compal Electronics, Inc. Custom 36,37,38,39,40,41,42 IDEBUS Fan Control Power On/Off CKT. File Name : LA-2592 LPC BUS page 29 Compal confidential PCBGA 1257 H_A#(3..31) CardBus Controller H_D#(0..63) CB-714 page 31 page 32USB conn x2 400/533MHz ALC250-VC PCI-E(DMI) page 25 DC/DC Interface CKT. Mobile Dothan/Yonah USB2.0 FSB Clock Generator THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ICS 954226 Power Circuit DC/DC PCI BUS uFCPGA-478 CPU page 34 DDR BANK0 32M*16*4 DDR-SO-DIMM1 page 35 Intel Alviso GMCH page 15page 4,5,6 RTC CKT. Audio CKT page 18 DDR1 -333 mBGA-609 AC-LINK page 15 page 7,8,9,10,11 Intel ICH6-M Thermal Sensor ADM1031AR page 12,13,14 page 19,20,21,22 AMP & Audio Jack APA2121 page 19 Touch Pad CONN. Int.KBD 4in1 Slot page 24 page 24 Gigabit LAN RTL8110SBL/ 8100CL RJ45/11 CONN M/B-S/B CONN LS-2594 TV-OUT / CRT conn page 17 page 25 page 33 page 32 Slot 0 page 26 One Channel page 23 IDE HDD Connector page 23 IDE ODD Connector SST39VF080-70 Flash ROM page 34 PCI-E page 16 M/B-NV44M VGA/B CONN LS-2597 VRAM 128MByte (32MByte*4) DDR300/300 page 28 Mini PCI socket page 27 page 32 IEEE1394 TSB43AB21 M/B-S/B CONN LS-2595 1394 conn page 30 MODEM AGERE CPS1038 EC KB910L page 33 SubBoard CONN List: LS-2597 VGA/B conn LS-2592 SWDJ/B conn LS-2593 TP/B conn LS-2594 CRT/TV-OUT conn LS-2595 USB&1394/B conn Intel CPU debug conn EC debug conn SW debug conn Page 32 Page 32 Page 32 Page 17 Page 4 Page 33 Page 33 Switch Button list: Power Botton(Sub/B) Lid Switch LED Function list: AC Power LED Charge LED HDD LED Page 34 Page 34 Page 32 Page 32 Page 32 M/B-S/B CONN LS-2595 USB conn x2 page 32 M/B-S/B CONN LS-2594 Camera/BlueTooth conn page 17USB2.0 M/B-S/B CONN LS-2593 Page 32 LS-2592 SWDJ/B List: SWDJ switch Button * 5 WL/BT on/foff Button *1 WL/BT LED *1 LS-2594 CRT/TV-OUT List: CRT conn * 1 TV-OUT conn * 1 USB conn * 2 BlueTooth conn * 1 Num LED * 1 CAP LED * 1 Scroll LED * 1 Lid Switch * 1 LS-2595 USB&1394/B List: USB conn* 2 1395 conn * 1 page 16 LVDS CONN 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet o f LA-2592 0.1 Design Note 3 46Tuesday, February 15, 2005 Compal Electronics, Inc. Custom I2C / SMBUS ADDRESSING External PCI Devices IDSEL # PIRQREQ/GNT #DEVICE Cardreader 1394 L AN CARD BUS Wireless LAN(MINI PCI) AD17 AD20 AD18 1 3 0 B E A G,H F +3VALW S0 S1 S3 S5 S4/AC S5 S4/AC don't exist State Signal ON +5VALW +12VALW +3V+2.5V +1.25VS +3VS+5VS +1.5VS +CPU_CORE ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF Power Managment table SERIAL SENSOR(CPU) SMB_EC_CK2 SOURCE KB910L INVERTER BATT EEPROM THERMAL SODIMM CLK CHIP SMBUS Control Table ICH_SMBCLK ICH_SMBDATA ICH6-M MINI PCI SMB_EC_DA2 SMB_EC_CK1SMB_EC_DA1 KB910L LCD_DDCCLKLCD_DDCDATA Alviso GM-GP LCD AD16 2 +1.1VS(VGA/B) +2.5VS +1.2VS(VGA/B) I2CC_SCLI2CC_SDA NV44M ADM1032 +1.8VS(VGA/B) +VCCP(1.05V) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CLK_ITP H_PWRGOOD TEST1 H_INTR H_D#27 H_D#19 H_D#16 H_D#8 CLK_CPU_BCLK H_REQ#4 H_REQ#2 H_A#25 H_D#30 H_D#26 H_D#14 H_D#12 H_A#20 H_FERR# H_D#56 H_D#5 H_RS#2 H_RS#0 H_ADS# H_A#29 H_A#26 H_A#7 H_A20M# H_D#41 H_D#29 H_D#24 H_D#21 H_ADSTB#0 H_A#14 H_HIT# H_BPRI# H_A#22 H_A#21 H_A#5 H_A#3 H_D#46 H_D#42 H_D#39 ITP_BPM#0 H_BR0# H_A#28 H_A#23 H_A#15 H_A#13 H_D#58 H_D#37 H_D#0 CLK_CPU_BCLK# H_A#24 H_A#11 H_A#8 H_INIT# H_DSTBP#1 H_D#60 H_DRDY# H_REQ#0 H_A#30 H_A#10 H_DSTBP#3 H_D#57 H_D#48 H_D#47 H_D#28 H_D#22 H_RS#1 H_ADSTB#1 H_A#31 H_A#27 H_A#9 H_NMI H_D#20 H_D#18 H_D#13 H_DEFER# H_A#18 H_DSTBN#0 H_D#52 H_D#51 H_D#50 H_D#45 H_D#15 H_D#11 H_D#3 ITP_BPM#3 H_IGNNE# H_DSTBP#2 H_DSTBN#1 H_D#33 H_D#23 H_D#7 H_D#1 H_REQ#3 H_DSTBP#0 H_D#63 H_D#59 H_D#49 H_D#32 H_D#17 ITP_BPM#2 H_TRDY# H_HITM# H_REQ#1 H_D#54 H_D#9 H_D#4 ITP_BPM#1 H_A#19 H_D#53 H_D#40 H_D#36 H_D#2 H_IERR# H_A#12 H_A#6 H_DSTBN#2 H_D#62 H_D#61 H_D#35 H_D#34 H_D#31 H_D#25 H_D#10 H_D#6 H_THERMDA H_RESET# H_DSTBN#3 H_D#55 H_D#38 H_LOCK# H_BNR# H_A#17 H_A#16 H_A#4 H_DPRSLP# TEST1 TEST2 ITP_TCK ITP_TRST# ITP_TDO H_CPUSLP# ITP_TMS ITP_TDI ITP_BPM#5 ITP_BPM#4 H_PROCHOT# H_SMI# H_STPCLK# ITP_DBRESET# H_DPSLP# H_DBSY# TEST2 H_THERMDC ITP_BPM#5 ITP_TDO ITP_TMS ITP_TDI ITP_TRST# ITP_TCK H_RESET# H_PROCHOT# ITP_TDI ITP_TRST# ITP_TMS ITP_TDO ITP_TDO_R CLK_ITP# CLK_ITP H_RESET# RESETITP# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_DBRESET# H_D#43 H_D#44 ITP_TCK CLK_ITP# H_A#[3..31]7 H_REQ#[0..4]7 H_ADSTB#07 H_ADSTB#17 CLK_ITP18 CLK_ITP#18 CLK_CPU_BCLK18 CLK_CPU_BCLK#18 H_ADS#7 H_BNR#7 H_BR0#7 H_BPRI#7 H_DEFER#7 H_DRDY#7 H_HIT#7 H_HITM#7 H_LOCK#7 H_RESET#7 H_RS#[0..2]7 H_TRDY#7 H_DBSY#7 H_DPSLP#20 H_DPRSLP#20 H_DPWR#7 H_PWRGOOD20 H_CPUSLP#7,20 H_THERMDA15 H_THERMDC15 H_THERMTRIP#7,20 H_D#[0..63] 7 H_DINV#0 7 H_DINV#1 7 H_DINV#2 7 H_DINV#3 7 H_DSTBN#[0..3] 7 H_DSTBP#[0..3] 7 H_A20M# 20 H_FERR# 20 H_IGNNE# 20 H_INIT# 20 H_INTR 20 H_NMI 20 H_STPCLK# 20 H_SMI# 20 PROCHOT# 33 ITP_DBRESET#21 +VCCP +VCCP +VCCP +VCCP +VCCP +3VS Title Size Document Number Rev Date: Sheet o f LA-2592 0.1 Dothan Processor(1/2) 4 46Tuesday, February 15, 2005 Compal Electronics, Inc. Custom Add pullups for PWRGOOD and THERMTRIP per INTEL Check ITP signal for Dothan Place near JITP 0.5" 39.2 Place near JITP 1" Place near JITP 0.5" 1" ~ 6.5" ITP_BPM#[0:3] < 6" Spacing 1:2 Place near JITP 0.5" Within 2" of the CPU Within 2" of the CPU Within 2" of the CPU Within 2" of the CPU H_DPRSLP will change to H_DPRSTP in future collateral version. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Spacing 8 mil LA2591 Rev0.1-DA600001600(6 layer) LA2592 Rev0.3-DA800005000(8 layer) R253 56_0402_5% 1 2 R49 54.9_0402_1% 1 2 T14PAD R32 200_0402_5% 1 2 R35 1K_0402_5%@ 1 2 LA-25 92 REV 0.3 ZZZ1 ADDR GROUP CONTROL GROUP HOST CLK MISC DATA GROUP THERMAL DIODE LEGACY CPU Dothan U15A TYCO_1612365-1_Dothan A3#P4 A4#U4 A5#V3 A6#R3 A7#V2 A8#W1 A9#T4 A10#W2 A11#Y4 A12#Y1 A13#U1 A14#AA3 A15#Y3 A16#AA2 A17#AF4 A18#AC4 A19#AC7 A20#AC3 A21#AD3 A22#AE4 A23#AD2 A24#AB4 A25#AC6 A26#AD5 A27#AE2 A28#AD6 A29#AF3 A30#AE1 A31#AF1 REQ0#R2 REQ1#P3 REQ2#T2 REQ3#P1 REQ4#T1 ADSTB0#U3 ADSTB1#AE5 BCLK0B15 BCLK1B14 ITP_CLK0A16 ITP_CLK1A15 ADS#N2 BNR#L1 BPRI#J3 BR0#N4 DEFER#L4 DRDY#H2 HIT#K3 HITM#K4 IERR#A4 LOCK#J2 RESET#B11 RS0#H1 RS1#K1 RS2#L2 TRDY#M3 BPM0#C8 BPM1#B8 BPM2#A9 BPM3#C9 DBR#A7 DBSY#M2 DPSLP#B7 DPWR#C19 PRDY#A10 PREQ#B10 PROCHOT#B17 PWRGOODE4 SLP#A6 TCKA13 TDIC12 TDOA12 TEST1C5 TEST2F23 TMSC11 TRST#B13 THERMDAB18 THERMDCA18 THERMTRIP#C17 D0# A19 D1# A25 D2# A22 D3# B21 D4# A24 D5# B26 D6# A21 D7# B20 D8# C20 D9# B24 D10# D24 D11# E24 D12# C26 D13# B23 D14# E23 D15# C25 D16# H23 D17# G25 D18# L23 D19# M26 D20# H24 D21# F25 D22# G24 D23# J23 D24# M23 D25# J25 D26# L26 D27# N24 D28# M25 D29# H26 D30# N25 D31# K25 D32# Y26 D33# AA24 D34# T25 D35# U23 D36# V23 D37# R24 D38# R26 D39# R23 D40# AA23 D41# U26 D42# V24 D43# U25 D44# V26 D45# Y23 D46# AA26 D47# Y25 D48# AB25 D49# AC23 D50# AB24 D51# AC20 D52# AC22 D53# AC25 D54# AD23 D55# AE22 D56# AF23 D57# AD24 D58# AF20 D59# AE21 D60# AD21 D61# AF25 D62# AF22 D63# AF26 DINV0# D25 DINV1# J26 DINV2# T24 DINV3# AD20 DSTBN0# C23 DSTBN1# K24 DSTBN2# W25 DSTBN3# AE24 DSTBP0# C22 DSTBP1# L24 DSTBP2# W24 DSTBP3# AE25 A20M# C2 FERR# D3 IGNNE# A3 INIT# B5 LINT0 D1 LINT1 D4 STPCLK# C6 SMI# B4 DPRSTP#G1 R179150_0402_5% 1 2 T3PAD T6PAD R38 200_0402_5%@ 12 T9PAD R251 1K_0402_5%@ 1 2 C B E Q29 2SC2411K_SC59 1 2 3 T1PAD T13PAD R48 54.9_0402_1% 1 2 T8PAD R177680_0402_5% 1 2 T5PAD R37 56_0402_5% 1 2 R258 1K_0402_5% 1 2 T15PAD R46 22.6_0402_1%@ 1 2 R33 56_0402_5% 1 2 R50 27.4_0402_1% 1 2T16PAD T2PAD T19PAD R42 39.2_0603_1% 1 2 T18PAD R266 56_0402_5% 1 2 T4PAD T17PAD R47 22.6_0402_1%@ 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A COMP0 COMP3 COMP1 COMP2 VID1 VID0 VID2 VID5 VSSSENSE VID3 VID4 VCCSENSE PSI# CPU_BSEL0 CPU_BSEL1 PSI#42 CPU_BSEL018 CPU_BSEL118 VID042 VID142 VID242 VID342 VID442 VID542 +VCCP +CPU_CORE +VCCP +V_CPU_GTLREF +V_CPU_GTLREF +CPU_CORE +1.5VS Title Size Document Number Rev Date: Sheet o f LA-2592 0.1 Dothan Processor(2/2) 5 46Tuesday, February 15, 2005 Compal Electronics, Inc. Custom Resistor placed within 0.5" of CPU pin.Trace should be at least 25 miles away from any other toggling signal. Layout close CPU Layout Note: 500 mil max length Spacing 25mil 20 mils(27.4Ohm) 20 mils 5 mils (55 Ohm) 5 mils(55 Ohm) Spacing 25mil Spacing 1:2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS T10 PAD R178 54.9_0402_1%@ 1 2 T12 PAD R250 54.9_0402_1% 1 2 R249 27.4_0402_1% 1 2 T20 PAD T11 PAD R247 2K_0402_1% 1 2 C341 10U_1206_6.3V6M 1 2 R181 54.9_0402_1%@ 1 2 C340 0.01U_0603_16V7K 1 2 R41 27.4_0402_1% 1 2 R40 54.9_0402_1% 1 2 Dothan POWER, GROUND U15C TYCO_1612365-1_Dothan VCCF20 VCCF22 VCCG5 VCCG21 VCCH6 VCCH22 VCCJ5 VCCJ21 VCCK22 VCCU5 VCCV6 VCCV22 VCCW5 VCCW21 VCCY6 VCCY22 VCCAA5 VCCAA7 VCCAA9 VCCAA11 VCCAA13 VCCAA15 VCCAA17 VCCAA19 VCCAA21 VCCAB6 VCCAB8 VCCAB10 VCCAB12 VCCAB14 VCCAB16 VCCAB18 VCCAB20 VCCAB22 VCCAC9 VCCAC11 VCCAC13 VCCAC15 VCCAC17 VCCAC19 VCCAD8 VCCAD10 VCCAD12 VCCAD14 VCCAD16 VCCAD18 VCCAE9 VCCAE11 VCCAE13 VCCAE15 VCCAE17 VCCAE19 VCCAF8 VCCAF10 VCCAF12 VCCAF14 VCCAF16 VCCAF18 VSSM4 VSSM5 VSSM21 VSSM24 VSSN3 VSSN6 VSSN22 VSSN23 VSSN26 VSSP2 VSSP5 VSSP21 VSSP24 VSSR1 VSSR4 VSSR6 VSSR22 VSSR25 VSST3 VSST5 VSST21 VSST23 VSS T26 VSS U2 VSS U6 VSS U22 VSS U24 VSS V1 VSS V4 VSS V5 VSS V21 VSS V25 VSS W3 VSS W6 VSS W22 VSS W23 VSS W26 VSS Y2 VSS Y5 VSS Y21 VSS Y24 VSS AA1 VSS AA4 VSS AA6 VSS AA8 VSS AA10 VSS AA12 VSS AA14 VSS AA16 VSS AA18 VSS AA20 VSS AA22 VSS AA25 VSS AB3 VSS AB5 VSS AB7 VSS AB9 VSS AB11 VSS AB13 VSS AB15 VSS AB17 VSS AB19 VSS AB21 VSS AB23 VSS AB26 VSS AC2 VSS AC5 VSS AC8 VSS AC10 VSS AC12 VSS AC14 VSS AC16 VSS AC18 VSS AC21 VSS AC24 VSS AD1 VSS AD4 VSS AD7 VSS AD9 VSS AD11 VSS AD13 VSS AD15 VSS AD17 VSS AD19 VSS AD22 VSS AD25 VSS AE3 VSS AE6 VSS AE8 VSS AE10 VSS AE12 VSS AE14 VSS AE16 VSS AE18 VSS AE20 VSS AE23 VSS AE26 VSS AF2 VSS AF5 VSS AF9 VSS AF11 VSS AF13 VSS AF15 VSS AF17 VSS AF19 VSS AF21 VSS AF24 Dothan P O W E R , G R O U N G , R E S E R V E D S I G N A L S A N D N C U15B TYCO_1612365-1_Dothan PSI#E1 GTLREFAD26 VCCQ0P23 VCCQ1W4 VCCSENSEAE7 VSSSENSEAF6 BSEL0C16 BSEL1C14 VCCA0F26 VCCA1B1 VCCA2N1 VCCA3AC26 VCCPD10 VCCPD12 VCCPD14 VCCPD16 VCCPE11 VCCPE13 VCCPE15 VCCPF10 VCCPF12 VCCPF14 VCCPF16 VCCPK6 VCCPL5 VCCPL21 VCCPM6 VCCPM22 VCCPN5 VCCPN21 VCCPP6 VCCPP22 VCCPR5 VCCPR21 VCCPT6 VCCPT22 VCCPU21 VCCD6 VCCD8 VCCD18 VCCD20 VCCD22 VCCE5 VCCE7 VCCE9 VCCE17 VCCE19 VCCE21 VCCF6 VCCF8 VCCF18 VID0E2 VID1F2 VID2F3 VID3G3 VID4G4 VID5H4 COMP0P25 COMP1P26 COMP2AB2 COMP3AB1 RSVDAF7 RSVDB2 RSVDC3 RSVDE26 VSS A2 VSS A5 VSS A8 VSS A11 VSS A14 VSS A17 VSS A20 VSS A23 VSS A26 VSS B3 VSS B6 VSS B9 VSS B12 VSS B16 VSS B19 VSS B22 VSS B25 VSS C1 VSS C4 VSS C7 VSS C10 VSS C13 VSS C15 VSS C18 VSS C21 VSS C24 VSS D2 VSS D5 VSS D7 VSS D9 VSS D11 VSS D13 VSS D15 VSS D17 VSS D19 VSS D21 VSS D23 VSS D26 VSS E3 VSS E6 VSS E8 VSS E10 VSS E12 VSS E14 VSS E16 VSS E18 VSS E20 VSS E22 VSS E25 VSS F1 VSS F4 VSS F5 VSS F7 VSS F9 VSS F11 VSS F13 VSS F15 VSS F17 VSS F19 VSS F21 VSS F24 VSS G2 VSS G6 VSS G22 VSS G23 VSS G26 VSS H3 VSS H5 VSS H21 VSS H25 VSS J1 VSS J4 VSS J6 VSS J22 VSS J24 VSS K2 VSS K5 VSS K21 VSS K23 VSS K26 VSS L3 VSS L6 VSS L22 VSS L25 VSS M1 RSVDAC1 T7 PAD R248 1K_0402_1% 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A +VCCP +CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE Title Size Document Number Rev Date: Sheet o f LA-2592 0.1 Dothan Bypass 6 46Tuesday, February 15, 2005 Compal Electronics, Inc. Custom Near VCORE regulator. ESR <= 3m ohm Capacitor > 880 uF THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C90 10U_1206_6.3V6M 1 2 C293 10U_1206_6.3V6M 1 2 C105 0.1U_0402_16V4Z 1 2 C260 10U_1206_6.3V6M 1 2 C91 0.1U_0402_16V4Z 1 2 C280 10U_1206_6.3V6M 1 2 C292 10U_1206_6.3V6M 1 2 C86 10U_1206_6.3V6M 1 2 C273 10U_1206_6.3V6M 1 2 + C70 150U_D_6.3VM 1 2 C80 0.1U_0402_16V4Z 1 2 C102 10U_1206_6.3V6M 1 2 C88 0.1U_0402_16V4Z 1 2 C99 10U_1206_6.3V6M 1 2 C259 10U_1206_6.3V6M 1 2 C82 10U_1206_6.3V6M 1 2 C274 10U_1206_6.3V6M 1 2 C87 10U_1206_6.3V6M 1 2 C267 10U_1206_6.3V6M 1 2 +C94 330U_D2E_2.5VM 1 2 C100 10U_1206_6.3V6M 1 2 C83 10U_1206_6.3V6M 1 2 C104 0.1U_0402_16V4Z 1 2 C84 10U_1206_6.3V6M 1 2 +C285 330U_D2E_2.5VM@ 1 2 C97 10U_1206_6.3V6M 1 2 C78 0.1U_0402_16V4Z 1 2 C92 10U_1206_6.3V6M 1 2 C282 10U_1206_6.3V6M 1 2 C302 10U_1206_6.3V6M 1 2 C93 10U_1206_6.3V6M 1 2 C279 10U_1206_6.3V6M 1 2 C283 10U_1206_6.3V6M 1 2 C265 10U_1206_6.3V6M 1 2 +C95 330U_D2E_2.5VM 1 2 C256 10U_1206_6.3V6M 1 2 C300 10U_1206_6.3V6M 1 2 C303 10U_1206_6.3V6M 1 2 C89 10U_1206_6.3V6M 1 2 +C286 330U_D2E_2.5VM 1 2 C272 10U_1206_6.3V6M 1 2 C301 10U_1206_6.3V6M 1 2 C257 10U_1206_6.3V6M 1 2 C98 10U_1206_6.3V6M 1 2 C101 10U_1206_6.3V6M 1 2 C96 0.1U_0402_16V4Z 1 2 C81 10U_1206_6.3V6M 1 2 C85 0.1U_0402_16V4Z 1 2 C79 0.1U_0402_16V4Z 1 2 C103 0.1U_0402_16V4Z 1 2 5 5 4 4 3 3 2 2 1 1 D D C C B B A A H_SWNG1 PM_EXTTS#0 PM_EXTTS#1 H_SWNG0 PM_EXTTS#0 PM_EXTTS#1 MCH_CLKSEL0 MCH_CLKSEL1 DDR_SCS#3 DDR_SCS#2 DDR_SCS#0 DDR_CKE3 DDR_CKE2 DDR_CKE0 DDR_CLK0# DDR_CLK1# DDR_CLK3# DDR_CLK4# DDR_CLK0 DDR_CLK1 DDR_CLK3 DDR_CLK4 DMI_RXP1 DMI_RXP0 DMI_RXN0 DMI_RXN1 DMI_TXP0 DMI_TXP1 DMI_TXN0 DMI_TXN1 SDREF SMRCOMPP SMRCOMPN CFG0 DMI_RXP3 DMI_RXP2 DMI_RXN2 DMI_RXN3 DMI_TXP2 DMI_TXP3 DMI_TXN2 DMI_TXN3 M_OCDOCMP0 M_OCDOCMP1 CFG0 H_D#21 H_D#46 H_D#30 H_D#47 H_D#33 H_D#49 TP_H_PCREQ# H_A#6 H_YSCOMP H_XSCOMP H_YRCOMP H_A#31 H_A#24 H_A#4 H_A#14 H_A#28 H_A#8 H_A#22 H_A#18 H_A#9 H_A#16 H_A#19 H_A#27 H_A#25 H_A#21 H_A#30 H_A#17 H_A#7 H_A#5 H_A#15 H_A#26 H_A#10 H_A#3 H_A#23 H_A#20 H_A#29 H_A#13 H_A#11 H_A#12 H_XRCOMP H_REQ#2 TP_H_EDRDY# H_REQ#0 H_REQ#4 H_REQ#1 H_ADSTB#1 H_REQ#3 H_DSTBN#3 H_ADSTB#0 H_DSTBP#0 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBP#3 H_DSTBP#2 H_DSTBP#1 H_DRDY# H_HIT# H_ADS# H_BR0# H_LOCK# H_TRDY# H_HITM# H_BNR# H_DEFER# H_BPRI# H_DBSY# H_RESET# H_SWNG0 H_SWNG1 H_RS#2 H_RS#0 H_RS#1 H_D#16 H_D#9 H_D#41 H_D#57 H_D#51 H_D#55 H_D#3 H_D#1 H_D#50 H_D#22 H_D#28 H_D#19 H_D#48 H_D#15 H_D#11 H_D#8 H_D#60 H_D#7 H_D#63 H_D#35 H_D#29 H_D#25 H_D#27 H_D#40 H_D#42 H_D#2 H_D#54 H_D#59 H_D#62 H_D#45 H_D#18 H_D#36 H_D#37 H_D#14 H_D#53 H_D#26 H_D#13 H_D#0 H_D#5 H_D#44 H_D#38 H_D#34 H_D#24 H_D#61 H_D#58 H_D#32 H_D#43 H_D#52 H_D#10 H_D#17 H_D#6 H_D#31 H_D#23 H_D#56 H_D#39 H_D#4 H_D#20 H_D#12 M_OCDOCMP0 M_OCDOCMP1 H_VREF SDREF H_CPUSLP# DMI_TXN021 DMI_TXN121 DMI_TXN221 DMI_TXN321 DMI_TXP021 DMI_TXP121 DMI_TXP221 DMI_TXP321 DMI_RXN021 DMI_RXN121 DMI_RXN221 DMI_RXN321 DMI_RXP021 DMI_RXP121 DMI_RXP221 DMI_RXP321 DDR_CLK012 DDR_CLK112 DDR_CLK313 DDR_CLK413 DDR_CLK0#12 DDR_CLK1#12 DDR_CLK3#13 DDR_CLK4#13 DDR_CKE012 DDR_CKE213 DDR_CKE313 DDR_SCS#012 DDR_SCS#213 DDR_SCS#313 MCH_CLKSEL1 18 MCH_CLKSEL0 18 PM_BMBUSY# 21 H_THERMTRIP# 4,20 +VCCP_PWRGD 33 PLTRST_MCH# 19,21,25,27 DREFCLK# 18 DREFCLK 18 SSC_DREFCLK 18 SSC_DREFCLK# 18 H_ADSTB#04 H_REQ#[0..4]4 H_A#[3..31]4 H_ADSTB#14 CLK_MCH_BCLK#18 CLK_MCH_BCLK18 H_DSTBN#[0..3]4 H_DSTBP#[0..3]4 H_DINV#04 H_DINV#14 H_DINV#24 H_DINV#34 H_RESET#4 H_ADS#4 H_TRDY#4 H_DPWR#4 H_DRDY#4 H_DEFER#4 H_HITM#4 H_HIT#4 H_LOCK#4 H_BR0#4 H_BNR#4 H_BPRI#4 H_DBSY#4 H_RS#[0..2]4 H_D#[0..63] 4 SDREF12,13 H_CPUSLP#4,20 +VCCP+VCCP +2.5VS +2.5V +VCCP +VCCP +VCCP +2.5V Title Size Document Number Rev Date: Sheet o f LA-2592 0.2 Alviso(1 of 5) 7 46Tuesday, February 15, 2005 Compal Electronics, Inc. Custom CFG[2:0] Refer to sheet 19 for FSB frequency select CFG19 (VTT Select) * * CFG18 (VCC Select) Low = DMI x 2 CFG7 High = DMI x 4 CFG5 Low = DT/Transportable CPU High = Mobile CPU CFG6 High = DDR-I Low = DDR-II CFG[13:12] CFG16 (FSB Dynamic ODT) Low = 1.05V (Default) 00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation (Default) High = 1.2V Low = 1.05V (Default) High = 1.5V High = Enabled Low = Disabled Low = Reverse Lane CFG9 High = Normal Operation * * * * * * 10/20 mils Layout Note: Rote as short as possible 100mil THIS SHEET OF ENGINEERING DRAWING IS THE