开发板所用芯片资料\ep1c3t144

PinInformationfortheCyclone™EP1C3T144DeviceFinalversion1.3BankVREFBankPinName/FunctionOptionalFunction(s)ConfigurationT144DQSforx8inNumberFunctiontheT144B1VREF0B1IOLVDS4pINIT_DONE1DM1LB1VREF0B1IOLVDS4n2DQ1L0B1VREF0B1IOLVDS3pCLKUSR3DQ1L1B1VREF0B1IOLVDS3n4B1VREF0B1IOVREF0B15B1VREF0B1IOLVDS2p6DQ1L2B1VREF0B1IOLVDS2n7DQ1L3B1VREF0B1VCCIO18B1VREF0B1GND9B1VREF0B1IODPCLK110DQS0LB1VREF1B1IOVREF1B111B1VREF1B1IOnCSO12B1VREF1B1DATA0DATA013B1VREF1B1nCONFIGnCONFIG14VREF1B1VCCA_PLL115B1VREF1B1CLK0LVDSCLK1p16B1VREF1B1CLK1LVDSCLK1n17VREF1B1GNDA_PLL118VREF1B1GNDG_PLL119B1VREF1B1nCEOnCEO20B1VREF1B1nCEnCE21B1VREF1B1MSEL0MSEL022B1VREF1B1MSEL1MSEL123B1VREF1B1DCLKDCLK24B1VREF1B1IOASDO25B1VREF1B1IOPLL1_OUTp26B1VREF1B1IOPLL1_OUTn27B1VREF2B1IODPCLK028DQS1LB1VREF2B1VCCIO129B1VREF2B1GND30B1VREF2B1IOVREF2B131B1VREF2B1IO32DQ1L4B1VREF2B1IOLVDS1p33DQ1L5B1VREF2B1IOLVDS1n34DQ1L6B1VREF2B1IOLVDS0p35DQ1L7B1VREF2B1IOLVDS0n36Copyright©2004AlteraCorp.PinListPage1of8PinInformationfortheCyclone™EP1C3T144DeviceFinalversion1.3BankVREFBankPinName/FunctionOptionalFunction(s)ConfigurationT144DQSforx8inNumberFunctiontheT144B4VREF2B4IOLVDS33p37B4VREF2B4IOLVDS33n38B4VREF2B4IOLVDS32p39DQ1B7B4VREF2B4IOLVDS32n40DQ1B6B4VREF2B4IOLVDS31p41DQ1B5B4VREF2B4IOLVDS31n42DQ1B4B4VREF2B4GND43B4VREF2B4VCCIO444VREF2B4GND45VREF2B4VCCINT46B4VREF2B4IODPCLK747DQS1BB4VREF2B4IOVREF2B448B4VREF2B4IO49B4VREF2B4IOLVDS30p50B4VREF2B4IOLVDS30n51B4VREF1B4IOLVDS29p52B4VREF1B4IOLVDS29n53B4VREF1B4IOLVDS28p54B4VREF1B4IOLVDS28n55B4VREF1B4IOVREF1B456B4VREF1B4IOLVDS27p57DM1BB4VREF1B4IOLVDS27n58B4VREF1B4IOLVDS26p59B4VREF0B4IOLVDS26n60B4VREF0B4IOVREF0B461B4VREF0B4IODPCLK662DQS0BVREF0B4GND63VREF0B4VCCINT64B4VREF0B4GND65B4VREF0B4VCCIO466B4VREF0B4IOLVDS25p67DQ1B3B4VREF0B4IOLVDS25n68DQ1B2B4VREF0B4IOLVDS24p69DQ1B1B4VREF0B4IOLVDS24n70DQ1B0B4VREF0B4IOLVDS23p71B4VREF0B4IOLVDS23n72Copyright©2004AlteraCorp.PinListPage2of8PinInformationfortheCyclone™EP1C3T144DeviceFinalversion1.3BankVREFBankPinName/FunctionOptionalFunction(s)ConfigurationT144DQSforx8inNumberFunctiontheT144B3VREF2B3IOLVDS22n73B3VREF2B3IOLVDS22p74B3VREF2B3IOLVDS21n75B3VREF2B3IOLVDS21p76B3VREF2B3IOLVDS20n77DQ1R7B3VREF2B3IOLVDS20p78DQ1R6B3VREF2B3IOVREF2B379B3VREF2B3GND80B3VREF2B3VCCIO381B3VREF2B3IODPCLK582DQS1RB3VREF2B3IOLVDS19n83DQ1R5B3VREF2B3IOLVDS19p84DQ1R4B3VREF2B3IO85DM1RB3VREF1B3CONF_DONECONF_DONE86B3VREF1B3nSTATUSnSTATUS87B3VREF1B3TCKTCK88B3VREF1B3TMSTMS89B3VREF1B3TDOTDO90B3VREF1B3IO91B3VREF1B3CLK3LVDSCLK2n92B3VREF1B3CLK2LVDSCLK2p93B3VREF1B3IO94B3VREF1B3TDITDI95B3VREF1B3IOVREF1B396B3VREF0B3IO97DQ1R3B3VREF0B3IOLVDS18n98DQ1R2B3VREF0B3IOLVDS18p99DQ1R1B3VREF0B3IODPCLK4100DQS0RB3VREF0B3GND101B3VREF0B3VCCIO3102B3VREF0B3IO103DQ1R0B3VREF0B3IOVREF0B3104B3VREF0B3IOLVDS17n105B3VREF0B3IOLVDS17p106B3VREF0B3IOLVDS16n107B3VREF0B3IOLVDS16p108Copyright©2004AlteraCorp.PinListPage3of8PinInformationfortheCyclone™EP1C3T144DeviceFinalversion1.3BankVREFBankPinName/FunctionOptionalFunction(s)ConfigurationT144DQSforx8inNumberFunctiontheT144B2VREF0B2IOLVDS15n109B2VREF0B2IOLVDS15p110B2VREF0B2IOLVDS14n111DQ0T0B2VREF0B2IOLVDS14p112DQ0T1B2VREF0B2IOLVDS13n113DQ0T2B2VREF0B2IOLVDS13p114DQ0T3B2VREF0B2VCCIO2115B2VREF0B2GND116VREF0B2VCCINT117VREF0B2GND118B2VREF0B2IODPCLK3119DQS0TB2VREF0B2IOVREF0B2120B2VREF0B2IOLVDS12n121B2VREF1B2IOLVDS12p122B2VREF1B2IOLVDS11n123DM0TB2VREF1B2IOLVDS11p124B2VREF1B2IOVREF1B2125B2VREF1B2IOLVDS10n126B2VREF1B2IOLVDS10p127B2VREF1B2IOLVDS9n128B2VREF1B2IOLVDS9p129B2VREF2B2IOLVDS8n130B2VREF2B2IOLVDS8p131B2VREF2B2IO132B2VREF2B2IOVREF2B2133B2VREF2B2IODPCLK2134DQS1TVREF2B2VCCINT135VREF2B2GND136B2VREF2B2VCCIO2137B2VREF2B2GND138B2VREF2B2IOLVDS7n139DQ0T4B2VREF2B2IOLVDS7p140DQ0T5B2VREF2B2IOLVDS6n141DQ0T6B2VREF2B2IOLVDS6p142DQ0T7B2VREF2B2IOLVDS5nDEV_OE143B2VREF2B2IOLVDS5pDEV_CLRn144Copyright©2004AlteraCorp.PinListPage4of8PinInformationfortheCyclone™EP1C3T144Deviceversion1.3PinType(1st,2nd,&PinName3rdFunction)PinDescriptionSupplyandReferencePinsTheseareI/Osupplyvoltagepinsforbanks1through4.Eachbankcansupportadifferentvoltagelevel.VCCIOsuppliespowertotheoutputbuffersforallI/Ostandards.VCCIOalsosuppliespowertotheinputVCCIO[1..4]PowerbuffersusedfortheLVTTL,LVCMOS,1.5-V,1.8-V,2.5-V,and3.3-VPCII/Ostandards.Theseareinternallogicarrayvoltagesupplypins.VCCINTalsosuppliespowertotheinputbuffersusedforVCCINTPowertheLVDS,SSTL2,andSSTL3I/Ostandards.GNDGroundDevicegroundpins.AllGNDpinsshouldbeconnectedtotheboardGNDplane.Inputreferencevoltageforbanks1-4.Ifabankusesavoltage-referencedI/Ostandard,thenthesepinsareusedasthevoltage-referencepinsforthebank.IfvoltagereferenceI/Ostandardsarenotusedinthebank,VREF[0..2]B[1..4]I/O,InputtheVREFpinsareavailableasuserI/Opins.VCCA_PLL[1..2]PowerAnalogpowerforPLLs[1..2].Thedesignermustconnectthispinto1.5V,evenifthePLLisnotused.GNDA_PLL[1..2]GroundAnaloggroundforPLLs[1..2].ThedesignercanconnectthispintotheGNDplaneontheboard.GNDG_PLL[1..2]GroundGuardringgroundforPLLs[1..2].ThedesignercanconnectthispintotheGNDplaneontheboard.NCNoConnectNoconnectpinsshouldnotbeconnectedontheboard.Theyshouldbeleftfloating.ConfigurationandJTAGPinsBidirectional(open-CONF_DONEdrain)Thisisadedicatedconfigurationstatuspin;itisnotavailableasauserI/Opin.Bidirectional(open-nSTATUSdrain)Thisisadedicatedconfigurationstatuspin;itisnotavailableasauserI/Opin.Dedicatedconfigurationcontrolinput.Alowtransitionresetsthetargetdevice;alow-to-hightransitionbeginsnCONFIGInputconfiguration.AllI/Opinstri-statewhennCONFIGisdrivenlow.Inpassiveserialconfigurationmode,DCLKisaclockinputusedtoclockconfigurationdatafromanexternalInput(PSmode),OutputsourceintotheCyclonedevice.Inactiveserialconfigurationmode,DCLKisaclockoutputfromtheCycloneDCLK(ASmode)device(theCyclonedeviceactsasmasterinthismode).Thisisadedicatedpinusedforconfiguration.DATA0InputDedicatedconfigurationdatainputpin.Active-lowchipenable.Dedicatedchipenableinputusedtodetectwhichdeviceisactiveinachainofdevices.nCEInputWhennCEislow,thedeviceisenabled.WhennCEishigh,thedeviceisdisabled.Outputthatdriveslowwhendeviceconfigurationiscomplete.Duringmulti-deviceconfiguration,thispinfeedsnCEOOutputasubsequentdevice’snCEpin.ActiveserialdataoutputfromtheCyclonedevice.Thisoutputpinisutilizedduringactiveserialconfigurationmode.TheCyclonedevicecontrolsconfigurationanddrivesaddressandcontrolinformationoutonASDO.InASDOI/O,Outputpassiveserialconfiguration,thispinisavailableasauserI/Opin.Chipselectoutputthatenables/disablesaserialconfigurationdevice.Thisoutputisutilizedduringactiveserialconfigurationmode.TheCyclonedevicecontrolsconfigurationandenablestheserialconfigurationnCSOI/O,OutputdevicebydrivingnCSOlow.Inpassiveserialconfiguration,thispinisavailableasauserI/Opin.Copyright©2004AlteraCorp.PinDefinitionsPage5of8PinInformationfortheCyclone™EP1C3T144Deviceversion1.3PinType(1st,2nd,&PinName3rdFunction)PinDescriptionThisisadual-purposepinandcanbeusedasanI/OpinwhennotenabledasINIT_DONE.Whenenabled,thepinindicateswhenthedevicehasenteredusermode.ThispincanbeusedasauserI/OpinafterINIT_DONEI/O,Output(open-drain)configuration.Optionaluser-suppliedclockinput.Synchronizestheinitializationofoneormoredevices.ThispincanbeusedCLKUSRI/O,InputasauserI/Opinafterconfiguration.Dual-purposepinthatcanoverrideallclearsonalldeviceregisters.Whenthispinisdrivenlow,allregistersDEV_CLRnI/O,Inputarecleared;whenthispinisdrivenhigh,allregistersbehaveasdefinedinthedesign.Dual-purposepinthatcanoverridealltri-statesonthedevice.Whenthispinisdrivenlow,allI/Opinsaretri-DEV_OEI/O,Inputstated;whenthispinisdrivenhigh,allI/Opinsbehaveasdefinedinthedesign.MSEL[1..0]InputDedicatedmodeselectcontrolpinsthatsettheconfigurationmodeforthedevice.TMSInputThisisadedicatedJTAGinputpin.TDIInputThisisadedicatedJTAGinputpin.TCKInputThisisadedicatedJTAGinputpin.TDOOutputThisisadedicatedJTAGoutputpin.ClockandPLLPinsDedicatedglobalclockinput.Thedual-functionofCLK0isLVDSCLK1p,whichisusedfordifferentialinputtoCLK0Input,LVDSInputPLL1.Dedicatedglobalclockinput.Thedual-functionofCLK1isLVDSCLK1n,whichisusedfordifferentialinputtoCLK1Input,LVDSInputPLL1.TheEP1C3T100doesnotsupportthisclockpin.Dedicatedglobalclockinput.Thedual-functionofCLK2isLVDSCLK2p,whichisusedfordifferentialinputtoCLK2Input,LVDSInputPLL2.Dedicatedglobalclockinput.Thedual-functionofCLK3isLVDSCLK2n,whichisusedfordifferentialinputtoCLK3Input,LVDSInputPLL2.TheEP1C3T100doesnotsupportthisclockpin.Dual-purposeclockpinsthatcanconnecttotheglobalclocknetwork.Thesepinscanbeusedforhighfan-outcontrolsignals,suchasclocks,clears,IRDY,TRDY,orDQSsignals.ThesepinsarealsoavailableasuserDPCLK[7..0]I/OI/Opins.ExternalclockoutputfromPLL1.ThispincanbeusedwithdifferentialorsingleendedI/Ostandards.IfclockoutputfromPLL1isnotused,thispinisavailableasauserI/Opin.TheEP1C3T100doesnotsupportthisPLL1_OUTpI/O,Outputoutputpin.NegativeterminalforexternalclockoutputfromPLL1.Iftheclockoutputissingleended,thispinisavailablePLL1_OUTnI/O,OutputasauserI/Opin.TheEP1C3T100doesnotsupportthisoutputpin.Dual-PurposeLVDS&ExternalMemoryInterfacePinsDual-purposeLVDSI/Ochannels0to33.ThesechannelscanbeusedforreceivingortransmittingLVDScompatiblesignals.Pinswitha"p"suffixcarrythepositivesignalforthedifferentialchannel.IfnotusedforLVDSinterfacing,thesepinsareavailableasuserI/Opins.TheEP1C3T100doesnotsupportLVDSI/OLVDS[0..33]pI/O,LVDSRXorTXinterfacing.Copyright©2004AlteraCorp.PinDefinitionsPage6of8PinInformationfortheCyclone™EP1C3T144Deviceversion1.3PinType(1st,2nd,&PinName3rdFunction)PinDescriptionDual-purposeLVDSI/Ochannels0to33.ThesechannelscanbeusedforreceivingortransmittingLVDScompatiblesignals.Pinswithan"n"suffixcarrythenegativesignalforthedifferentialchannel.IfnotusedforLVDSinterfacing,thesepinsareavailableasuserI/Opins.TheEP1C3T100doesnotsupportLVDSI/OLVDS[0..33]nI/O,LVDSRXorTXinterfacing.Dual-purposeLVDSclockinputtoPLL1.IfdifferentialinputtoPLL1isnotrequired,thispinisLVDSCLK1pInput,LVDSInputavailableastheCLK0inputpin.Dual-purposeLVDSclockinputtoPLL1.IfdifferentialinputtoPLL1isnotrequired,thispinisLVDSCLK1nInput,LVDSInputavailableastheCLK1inputpin.TheEP1C3T100doesnotsupportthisclockpin.Dual-purposeLVDSclockinputtoPLL2.IfdifferentialinputtoPLL2isnotrequired,thispinisLVDSCLK2pInput,LVDSInputavailableastheCLK2inputpin.Dual-purposeLVDSclockinputtoPLL2.IfdifferentialinputtoPLL2isnotrequired,thispinisLVDSCLK2nInput,LVDSInputavailableastheCLK3inputpin.TheEP1C3T100doesnotsupportthisclockpin.Optionaldatastrobesignalforuseinexternalmemoryinterfacing.ThesepinsalsofunctionasDPCLKpins;therefore,theDQSsignalscanconnecttotheglobalclocknetwork.AprogrammableDQS[0..1][L,R,T,B]I/OdelaychainisusedtoshifttheDQSsignalsby90or72degrees.DQ[0..7][L,R,T,B]I/OOptionaldatasignalforuseinexternalmemoryinterfacing.DM[0..1][L,R,T,B]I/OOptionaldatamaskoutputsignalforuseinexternalmemoryinterfacing.Copyright©2004AlteraCorp.PinDefinitionsPage7of8PinInformationForTheCyclone™EP1C3Device,ver1.3VREF2B2VREF1B2VREF0B2B2VREF0B1VREF0B3PLL1B1B3VREF1B1VREF1B3VREB2B1VREB2B3B4VREF2B4VREF1B4VREF0B4Notes:1.Thisisatopviewofthesilicondie.2.Thisisapictoralrepresentationonlytogetanideaofplacementonthedevice.Refertothepin-listandtheQuartusIIforexactlocations.Copyright©2004AlteraCorp.PLL&BankDiagramPage8of8