The International Technology Roadmap for Semiconductors

Chapter7ITRS:TheInternationalTechnologyRoadmapforSemiconductorsBerndHoefflingerAbstractInamovesingularfortheworld’sindustry,thesemiconductorindustryestablishedaquantitativestrategyforitsprogresswiththeestablishmentoftheITRS.Inits17thyear,ithasbeenextendedin2009totheyear2024.Wepresentsomeimportantandcriticalmilestoneswithafocuson2020.Transistorgatelengthsof5.6nmwitha3sigmatoleranceof1nmclearlyshowtheaggressivenatureofthisstrategy,andwereflectonthisgoalonthebasisofour10nmreferencenanotransistordiscussedinSect.3.3.Theroadmaptreatsindetailthetotalprocesshierarchyfromthetransistorlevelupthrough14levelsofmetallicinterconnectlayers,whichmusthandlethesignaltransportbetweentransistorsandwiththeoutsideworld.Thishierarchystartswithafirst-levelmetalinterconnectcharacterizedbyahalf-pitch(roughlythelinewidth)of14nm,whichisrequiredtobeapplicablethroughintermediatelayerswithwiringlengthsordersofmagnitudelongerthanatthefirstlocallevel.Attheuppermostgloballevel,themetalpatternhastobecompatiblewithhigh-densitythrough-siliconvias(TSV),inordertohandlethe3Dstackingofchipsatthewaferleveltoachievethefunctionalityofthefinalchip-sizeproduct.Attheindividualwaferlevel,thefullmanufacturingprocessischaracterizedbyupto40masks,thousandsofprocessingstepsandacumulativedefectdensityofhopefully<1/cm2.7.1Historyand2010StatusoftheRoadmapTheorganizationoftheUSsemiconductorindustry,theSIA(SemiconductorIndustryAssociation),launcheditsfirstroadmapin1992.FromtheexperiencewithMoore’slawof1965[1]and1975[2](Fig.2.10)andofthe“scaling”lawof1974[3](Fig.2.11),aforecastingschemewasderivedwitha15-yearhorizon.ThatB.Hoefflinger(*)LeonbergerStrasse5,71063Sindelfingen,Germanye-mail:bhoefflinger@t-online.deB.Hoefflinger(ed.),CHIPS2020,TheFrontiersCollection,DOI10.1007/978-3-642-23096-7_7,#Springer-VerlagBerlinHeidelberg2012161effortwasjoinedbythesemiconductorindustryinEurope,Japan,Korea,andTaiwanin1998,andthefirstInternationalTechnologyRoadmapforSemi-conductors(ITRS)wasissuedin1999.Afullyrevisedroadmaphasbeenissuedsinceineveryodd-numberedyear.Forourdiscussionhere,werelyonthe2009roadmapreachingouttotheyear2024[4].Itsaimistoprovidethebestpresentestimate(ofthefuture)witha15-yearhorizon.Theroadmapstartedoutinthe1990swithshrinkfactorsof0.7�/2yearsforminimumdimensionsandotherdimensionalparameterssuchasfilmthicknesses,lateraltoleranceswithinlayersandbetweenlayers,etc.,whichhadtobescaledconcurrently.Thistargetorientationhadatangibleinfluenceonprogress,evidentinthe1999speed-uponscalingto0.7�/18months(Fig.2.17).Inthemeantime,theroadmapprocessandstructurehasevolvedintoahighlycomplex,multidimen-sionaleffortwithmajorenhancements:2001:systemdrivers2005:emergingresearchdevices(ERD)2007:emergingresearchmaterials(ERM).Asaresult,numerousinternationalworkinggroupshavebeenestablished.Table7.1isalisting,togetherwithreferencestothechaptersinthepresentbookinwhichrelatedissuesareaddressedbyspecialists.Broadglobalassumptionsandstiffmodelsofexponentialprogressarecharac-teristicoftheroadmap,supportedsofarby40yearsofhistory.WestartwiththeS-curvefortheintroductionofnewproductsasshowninFig.7.1.InFig.7.1,firstconferencepapermeansfirstproductannouncement(typicallyattheISSCC).Itisalsocharacteristicthatthespecificequipmentforanewgenerationbecomesavailableinanearly(alpha)versiononly3yearsbeforethemassproduc-tionofchips.Furthermore,lead-timefromsamplestovolumeislessthan12months.IftheITRSortheindustrytalksofatechnologynode,itmeansthestartofvolumeproduction.Forcalibration:2010istheyearofthe32nmnode.The32nmhereintheITRSdefinesthesmallesthalf-pitchofcontactedmetallinesonanyproduct.Modelassumptionsarealsomadefortheoverallinnovationprocess,asweseeinFig.7.2.Table7.1Structureofthe2009ITRSandrelatedchaptersinthepresentbookSystemdriversChaps.6,10–13DesignChap.9TestandtestequipmentChap.21Processintegration,devicesandstructuresChap.3RFandanalog/mixed-signaltechnologiesChaps.4,5EmergingresearchdevicesChaps.3,23Front-endprocessesSect.3.2LithographyChap.8InterconnectsSect.3.6,Chap.5FactoryintegrationChap.21AssemblyandpackagingSect.3.8,Chaps.12,21162B.HoefflingerTheassumedR&Dlead-timeof10yearsintheexampleemphasizesthatanynewchiptechnologywithaneconomicimpactin2020shouldhavebeenpresentedinacrediblereductiontopracticeby2010.Basedonthesefundamentals,thecoreoftheroadmapcontinuestobetheoverallroadmaptechnologycharacteristics(ORTC).Fig.7.2Typicalrampfromresearchtoproduction.Theexampleillustratestheassumptionofintroducinghigh-electron-mobilitymaterialsforthetransistorchannelby2019[4].FEP:Frontendprocessing(#SEMATECH)Fig.7.1Productionramp-upandtechnology-cycletiming[ITRS2009].ERD/ERMemergingresearchdevices/materials,PIDSprocessintegrationanddevicestructures(#SEMATECH)7ITRS:TheInternationalTechnologyRoadmapforSemiconductors1637.2ORTC:OverallRoadmapTechnologyCharacteristicsThesecharacteristicsarethesmallestlengthsforgatesandlinewidthsoffirst-levelmetalintroducedinaproductinagivenyear(Table7.2).ThetrendsexpressedinthisdataarebestillustratedbythelinesinFigs.7.3and7.4.Thebasicobservationonthesetrendlinesisthatprogressisslowing:The0.7�shrink,whichclassicallyhappenedevery2yearsandevensawaspeed-upinthedecade1995–2005to18months,hasslowedto3yearsandtoalmost4yearsforthephysicalgatelengthinlogicchips.The2009roadmapdrawsamagiclineatthe16nmnodein2016.Theroadmapdataiscallednear-termtothisyear(2016),andithappenstobearsignificance,because,after2016andthe16nmnode,thesolutionstomostofthetechnologyissuesrelatedtoastraightscalingstrategyhadtobedeclaredasunknowninTable7.2Keylithography-relatedcharacteristicsbyproductandyear[ITRS2009]Near-termyears2010201220142016FlashPolySi½pitch[nm]32252016MPU/ASICfirstmetal½pitch[nm]45322419MPUphysicalgatelength[nm]27221815Long-termyears2018202020222024FlashpolySi½pitch[nm]12.610.08.06.3MPU/ASICfirstmetal½pitch[nm]15.011.99.57.5MPUphysicalgatelength[nm]12.810.78.97.4Fig.7.3ITRStrendlinesformetal-1half-pitchofDRAMandflashmemory[4](#SEMATECH)164B.Hoefflinger2009,whereaswiththelead-timemodelofFig.7.2,theyshouldhavebeenknownsince2004–2006.Asacaseinpoint,lithographyandtransistorperformancearehighlightedhere:AsoutlinedinChap.8onnanolithography,thereisin2010noknownlithographytechnologyfor16nmandbeyondotherthanlow-throughputmultiple-electron-beam(MEB)lithography.AsdescribedinSect.3.2,MOStransistorswithanequivalentoxidethickness(EOT)of1nmandL<15nmareastepbackincurrent/mm,havefundamentallylargevariancesofthresholdandcurrentandmostlynointrinsicgain.InSect.7.4,wediscusstowhatextentemergingresearchdevicescanremovethisroadblockby2020.Inanyevent,thehistoricscalingstrategyiscomingtoanendinawindowof16–10nm.Isthistheendofthechipindustryastheworldleaderinmarketgrowth?Toanswerthisquestion,itisworthwhileforgettingtheORTCscalingtrendlinesasaself-fulfillingprophecyordriverforamomentandtolookatthesolelyimportantproductandservicedrivers.7.3SystemDriversThesystem-driversworkinggroupwasestablishedin2001inordertofocusontherequirementsofthevariouschipmarkets,inawayalaterecognitionofamarket-drivenstrategy(marketpull)aftertheY2Kcrashandafter40yearsofanunparal-leledtechnologypushprovidedbyaMoore’slawimplementedbyscalingor,inotherwords,forceful2-yearsuccessionsofnewtechnologygenerations.Fig.7.4ITRStrendlinesforgatesandmetal-1half-pitchinmicroprocessorsandhigh-performanceASICs[4](#SEMATECH)7ITRS:TheInternationalTechnologyRoadmapforSemiconductors165TheInternationalTechnologyWorkingGroups(ITWGs)areamixofmarket(horizontal)andspecialty(vertical)groupsinthesenseofthematrixinChap.6ofthisbook,recalledhereasTable7.3.Ourexpertauthorsdealwiththerequirementsandchallengesinthespecialtyareasinthechaptersindicatedinthetable.Theextensivelistingsofrequirementsandchallengesofthe16workinggroupsoftheITRSshowcommondenominatorsfortherequiredratesofprogressintermsofproductperformance:–Doublethecomputing/communicationspeedevery2years–Doublethememorydensityevery2years.Thiscannotbeachievedbyscalinganymore,and,infact,ithasnotbeenachievedbyscalingsincethemid-1990s,butratherby“engineeringcleverness”,asdemandedbyMooreinthe1980s.Themultiprocessorcoresincomputingandthemultilevelstorage/transistorandstackedmemorychipsarestrikingexamplesofthiscleverness.Clearly,theenergyperfunction,CV2,demandscontinuousandforcefulreduc-tionofthecapacitanceCandtheoperatingvoltageV,andthedecisivecontributionshavetocomefrom–Thereductionofwirelengthsperfunction–Thereductionoftransistorsitesperfunction–Thereductionofthebandwidthbetweenprocessorsandmemories–Thereductionofvoltageswing(e.g.,low-voltagedifferentialsignaling,LVDS).Theprogressontheseissuesiscritical,anditwillbeaddressedagaininSect.7.4.Astosystemrequirements,wehavetolooksomemoreatthe2�/2yearsrate,asaggressiveasitmaybe.Itpromisesa32�progressperdecade.Justlookingatthepersonalmobileassistantof2020(Chap.13),weseethatadvances300�between2010and2020havebeendemandedandhavebeenconsideredtobefeasible.Thisstrategizingclearlyrequiresquantumjumpsinperformancebeyondthe2�/2yearsimprovement.Themulti-bit/cellflashRAMisthemostprominentexampleofthisphenomenon(Fig.7.5).Operationspersecondpermilliwattisthekeymetricforgraphicsandimageprocessing,anditisherethatrichmediaand3Dvisionrequirea300-foldimprove-mentbetween2010and2020.HIPERLOGICinSect.3.6anddigitalneuro-processinginChap.16areindicativeofsuchquantumjumpsinperformanceTable7.3Markets(vertical)andspecialfunctions(horizontal)ofnanochipsProcessorChaps.10,13,16MemoryChaps.11,18Analog/digitalChap.4Transmitter/receiverChap.5Sensor/actuatorChaps.14,15,17ComputingxxxxxxxxCommunicatingxxxxxxxxxxConsumerxxxxxxxxxxxxMed./IndustrialxxxxxxxxxxxxxAutomotivexxxxxxxxxxMilitaryxxxxxxxxxxxxxxx166B.Hoefflingerbeyondjustanextensionofthemainstreamby2�/2years.Inviewofthe16nmbarrier,theITRSputshighhopesonemergingresearchdevices.7.4ERD:EmergingResearchDevicesNumerouskeywordsforfuturedevicesandnewinformationparadigmsaremen-tionedbythisworkinggroup.WithreferencetotheinnovationcurveinFig.7.2asappliedtoproductintroductionby2020,wefocusonenhancedMOStransistorswithgates10nmlong.Theroadmapshowsapossibleprogression,reproducedinFig.7.6.Themostimportant,10�,R&Dtasksareclearlyidentifiedinthisfigure:1.Transitiontometalgate2.Transitiontohigh-k(high-dielectric-constant)gatedielectric3.Transitiontofullydepletedsilicon-on-insulator(FDSOI)4.Transitiontomultiple-gate(MuG)transistorsWhileitems1and2havebeenintroducedintoproduction,continuousimprove-mentisnecessary.Item3,thinSifilmsoninsulator,withthicknesses<5nm,fullydepleted,areamatterofcomplextrade-offsandcloselyrelatedtothechallengingintroductionofmultiple-gatetransistors,eitheras–Dual-gatetransistorsoras–Surround-gatetransistors.Fig.7.5Gigabits/chipforDRAMandflashRAM[4].SLCsingle-levelcell,MLCmulti-levelcell(#SEMATECH)7ITRS:TheInternationalTechnologyRoadmapforSemiconductors167Thesetransistortypesupsetthephysical-designtopographiessomuchengravedintheindustrythattheirintroductionbyanycompanywillreallymeanaquantumstepintheindustry.Whiledual-gateandtri-gatetransistorshavebeenintroducedin2011,andseveralinterestingandpowerfulfunctionalitieshavebeendescribedinSect.3.5,thesurround-gatetransistorisalong-termtopiccloselyassociatedwiththenanotube-transistors(Sect.3.8).Figure7.6alsopointsoutnewmaterialsforthetransistorchannels.StrainedSiandSiGehavealreadybeenintroducedtoachievehigherelectronmobilitiesandholemobilitiescomingclosertothoseofidealelectronsforspeedandsymmetricaloperation.III–VmaterialsforMOStransistorchannelsareconsideredwithopti-mismtobenefitfromafivefoldorhighermobility.However,weshouldkeepinmindthatwhatcountsinswitchingcircuitryismaximumcurrent,andthisisdeterminedbymaximumvelocity,(3.15),andthiswouldbeatbesttwotimeshigher.Whilethismightstillbeworththeeffort,theprocessingandcompatibilitychallengesandthelossofatechnologywithcomplementarytransistorshavetobeweighedin.Theemphasisonspeedisonlyjustifiedforthegighertzandterahertzcommunityofsuperprocessorsandbroadbandcommunication.Forallothers,energy/functionistheissue.Herewedealwiththeworldbelow400mV.WestudiedthisworldextensivelyinSects.3.2and3.3,andthemostimportantmessageswelearnedare:1.Themaximumoperatingvoltagefora1nm(EOT)gatetransistoris500mV.2.At<500mV,MOStransistorsoperateinthebarrier-control(diffusion,bipolar,orleakage)mode,wherethepotentialbarrieriscontrolledbyboththegateandthedrainvoltages(3.17,20).3.ThetransconductanceofaMOStransistoratroomtemperatureisadecadeofcurrentper120mVatbest,withafundamental4sspreadto<300mVforL¼10nm.Fig.7.6Apossibleprogressiontoa10nmtransistorin2020[4](#SEMATECH)168B.Hoefflinger4.TheintrinsicvoltagegainfortI¼1nm(EOT)andL¼10nmisunity,i.e.,nogainwithoutchannelengineering(3.22).5.Themaximumcurrentisagaindeterminedbythemaximumhigh-fieldvelocityandnotbylow-fieldmobility(3.16,21).Again,themobilityadvantageofIII–VmaterialsandGeisnotrelevant.Fur-thermore,thetemperaturedependenceofcurrentsinthebarrier-controlmodeisratherstrong.Thismeansthaton–offcurrentratiosshrinkrapidlyathighertemperatures,aproblemforSiandlikelytheoutforGeasachannelmaterial.6.ThefundamentalvarianceofnanotransistorsduetoPoissondistributionsofcharges(acceptors,donors,channelcharges)requiresthatanysignalregenera-tor/amplifierhastobemadeupofcomplementarytransistors,and,infact,differentialsignaling(LVDS),andcross-coupledcomplementarytransistorpairsarerequired(Sect.3.3)forsafelogicoperations.Thesestringentcriteriahavetobeobservedintheevolutionofscaled-downMOStransistorsbutalsoforanypossiblereplacementsintherealworldofchipsforthemasses,whichisat20�Candmostlysignificantlyhigheron-chip.BeyondthescenarioofFig.7.6anda2020horizon,emergingresearchpursuesmanydirectionsintheabsenceofawinner.TheERDcommitteehasassessedmorethan15differenttechnologiesinamultidimensionalperformanceevaluation.Weselecttheevaluationoftwotypesoftransistors,whichwediscussedinSect.3.8:–Thecarbon-nanotube(CNT)MOSFET–Thesingle-electrontransistor(SET)Theirevaluation,asshowninFig.7.7,showseightwell-chosenperformancecriteria:–Performance–Energyefficiency–Gain–Scalability–CompatibilitywithCMOSarchitecture–CompatibilitywithCMOStechnology–Operationaltemperature–ReliabilityApartfromthequantitativeassessmentofthecriteria,theimportantobservationonthesediagramsistheevolutionoftheratingsovertime:Fromgreenin2005throughbluein2007toredin2009.Althoughaspanoffouryearsisshortonaresearchtimescale,theapparenttrendisthatalmostallvaluesof2005lookedoptimisticcomparedwiththeassessmentin2009.Thisappearanceofmorerealismisfrequentinthe2009issueoftheroadmap.Itisanindicatorthatmorefundamental,radicalinnovationsareseenashavinganimpactfartherinthefuturethanassumedinrecentyears.Thisdoesnotmeanthattheprogressionofelectronicchipshasslowed,butthatotherdisruptiveinnovationshavetakencenterstage,whicharelessnanoandquantum-driven.Interconnectsareasuperbexampleofthisphenomenon.7ITRS:TheInternationalTechnologyRoadmapforSemiconductors1697.5InterconnectsFortheintegratedcircuitfunctionsonachip,thousandstobillionsoftransistorshavetobeinterconnectedbythin-filmmetallayers,eachseparatedfromthoseaboveandbelowbyinter-leveldielectricinsulators.TheschematiccrosssectioninFig.7.8ofthesurfaceofachipillustratestheresultingstructure.Atthebottom,weseeapairofcomplementarytransistors,eachinitswellforisolation.Bluetungstenplugsreachuptothefirstmetalinterconnectlayer.Themanufacturingprocessuptothisleveliscalledthefront-endofline(FEOL).WhatGainGainEnergyEfficiencyEnergyEfficiencyOperationalReliabilityOperationalReliabilityOperationalTemperatureOperationalTemperatureScalabilityCMOSArchitecturalCompatibilityCMOSTechnologicalCompatibility123PerformancePerformance321ScalabilityCMOSArchitecturalCompatibilityabCMOSTechnologicalCompatibility2005(1DStructures)2007(1DStructures)2005(SETs)200920092007(SETs)Fig.7.7Evaluationof(a)carbonnanotubeMOSFETsand(b)single-electrontransistors[4](#SEMATECH)170B.Hoefflingerfollowsintheexampleisthreelayersofintermediate-levelwires,twolayersofsemi-global,andanotherfivelayersofglobalinterconnects.Thishierarchyvisiblydemonstratesthemostseriousroadblockfornanoelectronics:Themulti-levelinterconnectwithitsproblemsof–Resistance,capacitance,inductance–Loadingthetransistors–Crosstalk–Areaandvolume–Overlaytolerance–Costandyield–ReliabilityThescalingofthismazeofinvertedskyscraperswithskywalksatupto14levelsisahighlycomplexchallenge,andtheroadmapdemandsaprogressionasshowninFig.7.9,forwhichmanufacturablesolutionsbeyond2015arenotknownorhaveseveredrawbacksinresistance,crosstalkandreliability.Inanyevent,thepressureto–Reduceoperatingvoltages–Uselow-voltagedifferentialsignaling(LVDS)Fig.7.8SchematiccrosssectionthroughthesurfaceofaCMOSchipillustratingthewiringhierarchy.Blueandorange:metal,gray:insulators[4](#SEMATECH)7ITRS:TheInternationalTechnologyRoadmapforSemiconductors171mountssteadily.Atthesametime,lateralwiringlengthsarebecomingexcessive,becauseofthewiderpitch,whichhastobeacceptedatthehigher,intermediate,andgloballevels,andalsobecauseoftheslowerpaceofscalingtransistorsand,infact,theendoftheroadmapforlateraltransistordimensions.Thisscenariohasfinallycausedawidespreadcommitmentsinceabout2005toreducelateralwiringlengthsandchipsizesbystackingchipsontopofeachother,10111042020199020002010TSV´sContacts1010109108107106105xxxxmbumpsOn-ChipViasDensity(cm–2)YearFig.7.9Projecteddensityofcontacts,vias,TSV’s,andbumps172B.HoefflingeraswediscussedinSect.3.7.Manyalternativesforstackingexist,dependingonchipfunctionalityandthemanufacturersinvolved,leadingtonewnetworksandactionchains.Wehighlightthesepossiblescenarioswiththeillustrationofthreealternativesforproducingvias,whichhavetogothroughthe(thinned)chipstocarrysignalsandpowerfromonechiptothenext(Fig.7.10).AssumingaSOIchip,TSV-firstmeansthattheviaisformedliterallybeforetheformationofthetransistorlayer.Inthecenter,thealternativeTSV-middleisshown,wheretheTSVisformedattheendoftheFEOL,togetherwiththefirstmetal.Attheback-end-of-line(BEOL)ontheright,avoluminousTSV-lastisshowngoingthroughthechip,indicativeoftheaspectratiosthathavetoberealizedbyappropriatecuttingand/oretchingprocesses.Bearinginmindtheseriouslithographylimitsonavolume-productionlevelbelow15nmandtheconductancelimitsofmetalwiresatthisscale,thefurtherscaling-downofinterconnectsisclearlythenumberoneareaforalternativewires/interconnectssuchascarbonnanotubesandgraphenelinesbecauseoftheirfundamentaladvantagesbutalsobecausetheycanbeproducedwithoutlithography[5–7].References1.Moore,G.:Crammingmorecomponentsontointegratedcircuits.Electron.Mag38(8),19Apr19652.Moore,G.:Progressindigitalintegratedelectronics.IEEEIEDM(InternationalElectronDevicesMeeting),TechnicalDigest,pp.11–13(1975)3.Dennard,R.H.,Gaensslen,F.H.,Yu,H.N.,Rideout,V.L.,Bassous,E.,LeBlanc,A.R.:Designofion-implantedMOSFET’swithverysmallphysicaldimensions.IEEEJSolid-StCirc9,256(1974)Fig.7.10ChipcrosssectionsshowingTSVfirst,attheendofFEOL,andlast[4](#ITRS)7ITRS:TheInternationalTechnologyRoadmapforSemiconductors1734.www.itrs.net/reports.html.SemiconductorIndustryAssociation.TheInternationalTechnologyRoadmapforSemiconductors,2009Edition.InternationalSEMATECH:Austin,TX20095.Appenzeller,J.,Joselevich,E.,Hoenlein,F.:Carbonnanotubesfordataprocessing.In:Waser,R.(ed.)NanoelectronicsandInformationTechnology,2ndedn.Wiley-VCH,Weinheim(2005)6.Wolf,E.L:Chap.5,Somenewerbuildingblocksfornanoelectronics.In:QuantumNanoelectronics,Wiley-VCH,Weinhiem(2009)7.Hoenlein,W.,Kreupl,F.,Duesberg,G.S.,Grahem,A.P.,Liebau,M.,Seidel,R.,Unger,E.:Carbonnanotubeapplicationsinmicroelectronics.In:Siffert,P.,Krimmel,E.F.(eds.)Silicon:EvolutionandFutureofaTechnology,pp.477–488.Springer,Berlin/Heidelberg(2004)174B.Hoefflinger Chapter7:ITRS:TheInternationalTechnologyRoadmapforSemiconductors 7.1Historyand2010StatusoftheRoadmap 7.2ORTC:OverallRoadmapTechnologyCharacteristics 7.3SystemDrivers 7.4ERD:EmergingResearchDevices 7.5Interconnects References