台式机电脑主板检测代码全（Desktop computer motherboard detects code all）

台式机电脑主板检测代码全（Desktop computer motherboard detects code all） 台式机电脑主板检测代码全(Desktop computer motherboard detects code all) In general, code: FF, 00, C0, D0, CF, F1, or nothing means the CPU hasn't passed ? ? C1, C6, C3, D3, D4, D6, D8, B0, A7, E1 represent memory ? ? 24, 25, 26, 01, 0A, 0B, 2A, 2B and 31 represent the graphics card ? 23, 24, 25, said some integrated graphics motherboard can normal light, some VIA chipset showed 13 said can light up, some in the name-brand computer motherboard shows 0 b is normal, some motherboard shows 4 e said normal light, some INTEL motherboard chipset showed 26 or 16 can normal light. ? ? The combination cycle of C1, C6, C3, 01, and 02 is mostly I / 0 bad or swiping the BIOS ? ? If shown in 05, ED, 41, direct the BIOS 00. Will control INI19 boot load. . 01 processor test 1, processor state verifies, if the test fails, the loop is infinite. Processor register tests are about to begin, and unblocking interrupts are about to be stopped. CPU register tests are ongoing or fail. Determine the type of diagnosis (normal or manufacturing). If the keyboard buffer contains data, it will fail. Disable unmasking interrupt; Start with a delay. CMOS write/read is in or out. Remove 8042 keyboard controller and send out the TESTKBRD command (AAH). ROM? The BIOS checkups are ongoing or fail. 4 reset the 8042 keyboard controller to verify the TESTKBRD. Soft reset/power test for keyboard controller. Programmable interval timer tests are being performed or failed. If repeated manufacturing tests 1 to 5 are repeated, 8042 control status can be obtained. The soft reset/power is determined; The ROM is to be started. The DMA is starting or failing. Make the circuit chip initial preparation, disable video, parity, DMA circuit, and clear DMA circuit, all page registers and CMOS outage bytes. The ROM BIOS check sum has been set up and the keyboard buffer is checked. The DMA initial page register read/write test is ongoing or malfunctioning. 7 processor test 2, verify the CPU register's work. ROM BIOS check sum is normal, keyboard buffer has been cleared, and the keyboard is issued BAT (basic guarantee test) command. . Make the CMOS timer as the initial preparation, normal update timer cycle. The BAT command has been issued to the keyboard, which is about to be written to the BAT command. RAM update inspection is ongoing or failure. 09 EPROM check sum must be equal to zero. Verify the basic guarantee test of the keyboard and then verify the keyboard command bytes. The first 64K RAM test is ongoing. 0A makes video interface initial preparation. Issue keyboard command byte code to write command byte data. The first 64K RAM chip or data line malfunction, shift. 0B test 8254 channel 0. Write to the keyboard controller command byte, which will issue the blocking/unlock command of pin 23 and 24. The first 64K RAM odd/even logic failed. 0C test 8254 channel 1. Keyboard controller pin 23, 24 has been blocked/unlocked; The NOP command has been issued. The first 64K RAN address line fault. 0D 1. Check whether CPU speed matches the system clock. 2. Check whether the programmed value of the control chip is consistent with the initial setting. 3. Video channel test. If it fails, honk. The NOP command has been processed; Then the CMOS stop the register. The parity failure of the first 64K RAM 0E test CMOS outage bytes. CMOS stop the register read/write test; The CMOS check sum will be calculated. Initialize the input/output port address. 0F test expanded CMOS. Computed CMOS check sum to write diagnostic bytes; CMOS is starting to prepare. . 10 test DMA channel 0. CMOS is ready for initial preparation, and CMOS status registers will be ready for date and time. The first 64K RAM zero bit fault. 11 test DMA channel 1. The CMOS status register has been initialized to disable DMA and interrupt controllers. The first 64DK RAM 1 fault. 12 test DMA page register. Disable DMA controller 1 and interrupt controller 1 and 2; Prepare the video monitor and make port B initial. The first 64DK RAM second fault. Test 8741 keyboard controller interface. The video display has been deactivated and port B has been pre-prepared; Starting circuit chip initialization/memory automatic detection. The first 64DK RAM no. 3 fault. 14 test memory update trigger circuit. Circuit chip initialization/memory automatic detection end; The 8254 timer test is about to begin. The first 64DK RAM is the fourth fault. 15 test the beginning of 64K system memory. The second channel timer is half tested; 8254 the 2nd channel timer is about to complete the test. The first 64DK RAM no. 5 fault. Set up the interrupt vector table for 8259. End of channel 2 timer test; The 8254 first channel timer is about to complete the test. The first 64DK RAM no. 6 fault. Set the video input/output job, and the video BIOS is enabled. The first channel timer test is over; The 08254 0 channel timer is about to complete the test. The first 64DK RAM was the seventh failure. Test video memory. If the installation of video BIOS is adopted, it can be bypassed. The 0th channel timer test is over; The memory will begin to be updated. The first 64DK RAM was the eighth failure. Test # 1 interrupt controller (8259) mask bit. The memory is now being updated and the memory is updated. The first 64DK RAM no. 9 fault. 1A test the interruption controller of channel 2 (8259) shielding bit. The memory update line is being triggered to check the 15 microsecond pass/break time. The first 64DK RAM is the 10th fault. 1B test CMOS battery level. Complete memory update time 30 microsecond test; The basic 64K memory test is about to begin. The first 64DK RAM was the 11th fault. 1C test CMOS total. . The first 64DK RAM no. 12 fault. 1D adjust CMOS configuration. The first 64DK RAM no. 13 failed. 1E determines the size of system memory and compares it to CMOS value. . The first 64DK RAM no. 14 fault. 1F test 64K memory to maximum 640K. . The first 64DK RAM no. 15 fault. The fixed 8259 interrupt was measured. Start the basic 64K memory test; Test the address line. The slave DMA register tests are ongoing or failing. Maintain an unmasking interrupt (NMI) bit (parity or input/output channel checks). Pass the address line test; It's about to trigger parity. The main DMA register test is in or out. Test the interrupt function of 8259. End trigger parity; The serial data read/write test will begin. The main interrupt mask register test is in or out. Test protection mode 8086 virtual mode and 8086 page mode. Basic 64K serial data read/write test normal; Any adjustment before the interrupt vector initialization is about to begin. The slave interrupt mask test is ongoing or malfunctioning. Measure 1MB of extended storage. Any adjustments prior to the initialization of the vector will begin the initial preparation of the interrupt vector. Set up the ES section address register registry to memory high end. 25 test all memory after the first 64K. Complete the initial preparation of the interrupt vector; The input/output port of 8042 will be read for rotary interrupter. The load interrupt vector is being carried out or failed. The exception of the test protection method. Read 8042 input/output ports; It's about to start making global data ready for a rotational interruption. Open A20 address line; To enter the address. Determine the control or block RAM of the superfast buffer memory. All 1 data initial preparation is completed; Then any initial preparation after the interrupt vector is performed. Keyboard controller tests are ongoing or malfunction. Determine the control of the ultra high speed buffer memory or the special 8042 keyboard controller. The initial preparation after completing the interrupt vector; The color scheme is about to be adjusted. CMOS power failure/check summation is ongoing. 29. The color mode of the order has been adjusted. A check on the effectiveness of CMOS configuration is under way. 2A makes the keyboard controller initial preparation. The color mode has been adjusted to trigger parity before the ROM test. Empty 64K base memory. 2B the disk drive and the controller for initial preparation. Trigger parity end; Any adjustments you need before you control the video ROM check. Screen memory tests are ongoing or failing. 2C check the serial port and make the original preparation. Complete video ROM control before control; Check the optional video ROM and control it. The screen initial preparation is ongoing or malfunctioning. 2D detection parallel port and make the original preparation. You have completed the optional video ROM control, which is about to be controlled by any other processing after the video ROM restore control. The screen rescan test is ongoing or malfunctioning. 2E makes the hard disk drive and controller initial preparation. Processing recovery from video ROM control; If no EGA/VGA is found to be on display memory read/write test. Detection of video ROM is ongoing. 2F tests the mathematical coprocessor and prepares the work. EGA/VGA was not found; To start the display memory read/write test. . Build basic memory and expand memory. Read/write tests on display memory; A scan is about to be done. Think the screen works. Test the selection of ROM from C800:0 to EFFF: 0, and make the original preparation. The display memory reads/writes tests or scans fail, and another display memory reads/writes tests. A monochrome monitor can work. 32 the I/O chip programming of the mainboard COM/LTP/FDD/sound device makes it suitable for setting values. Read/write tests on another display memory; It will perform another monitor scan. The color monitor (40 columns) can work. 33. Video monitor is completed; Will start to use the adjustment switch and the actual card to check the display of the display. Color monitors (80 columns) can work. 34. The display adapter has been inspected; Then the display mode is set. The tick off test is ongoing or malfunction. 35. Complete the adjustment display mode; The data area to check the BIOS ROM. The shutdown test is ongoing or malfunctioning. The BIOS ROM data area has been checked; A cursor that is about to tune the information. A - 20 failure in the door circuit. 37. The cursor identification of the electronic information is completed; Electrical information is about to be displayed. Unexpected interruption in the protection mode. 38. Complete the display of electrical information; The new cursor position is to be read. RAM tests are ongoing or address failure. 39. The cursor position is read and the reference string is displayed. . 3A. Display the end of the reference string; Discover < ESC > information. Interval timer channel 2 test or failure. 3B USES the OPTI circuit (only 486) to make the auxiliary super high speed buffer memory for initial preparation. Already shown < ESC > information; Virtual mode, memory testing is about to begin. Daily calendar clock tests are ongoing or malfunction. 3C establishes the mark that allows access to CMOS Settings. The serial port test is in or out. 3D initializer keyboard/PS2 mouse/PNP device and total memory node. Parallel port tests are ongoing or fail. 3E tries to open the L2 cache. The mathematical coprocessor test is ongoing or failing. 40. Preparation of virtual methods for testing; It's going to be tested from video memory. Adjust the CPU speed to match the peripheral clock accurately. The 41st interrupt has been opened, the initialization data will be initialized to the 0:0 test memory transform (interrupt controller or malmemory) from the video memory test. Prepare the descriptor table. System card selection failed. 42 display window into SETUP. The descriptor table is ready; Virtual methods are about to be tested in memory. Expand CMOS RAM failures. If plug and play BIOS, then serial port, and initialization. Enter the virtual mode; An interrupt is being implemented for diagnostics. . 44. Interruption has been achieved (for example, the diagnostic switch has been switched on; the data is about to be initialized to check the memory on the 0:0 return.) The BIOS interrupt is initialized. 45 initializing the mathematics coprocessor. The data has been initialized; The memory is about to be checked back to 0 0 0 and to find out the size of the system memory. . 46. The test memory has returned; The memory size is completed and the page will be written to test the memory. Check the read-only memory ROM version. 47. Upcoming memory trial writing pages; The basic 640K memory is written to the page. . 48. The basic memory is written to the page; To determine more than 1MB of storage. Video check, CMOS reconfiguration. 49. Find out the memory of 1BM and verify; To determine more than 1MB of storage. . 4A. Find out more than 1MB of storage and check; Will check the BIOS ROM data area. You initialize the video. 4B. The test of the BIOS ROM data area is over, and it is about to check the memory of < ESC > and over 1MB for soft reset. . 4C. Erase more than 1MB of memory (soft reset) to remove more than 1MB of storage. . 4D has cleared more than 1MB of memory (soft reset); Will save the size of the memory. . 4E if there is any error detected; Display the error message on the display and wait for the customer to press the < F1 > key to continue. Test of memory: (no soft reset); A test to show the first 64K memory. Display copyright information. 4F read and write soft, hard disk data, DOS boot. Start showing the size of the memory, and the memory will be updated; Serial and random memory tests will be performed. . The CMOS value in the current BIOS can be stored in CMOS. Complete the memory test of 1MB. The size of the high - speed memory for relocating and masking. Send CPU types and speed to the screen. Test more than 1MB of memory. . All the ISA read-only memory ROM is initialized, and finally the initialization of IRQ is assigned to PCI. Has completed storage testing of more than 1MB; Ready to go back to the real location. Enter keyboard detection. If the BIOS is not plug and play, the serial port, parallel port and set time value are initialized. Save the size of the CPU register and memory and will enter the real address. . 54. Successful opening of the real address; The register that will be saved when it is ready to be stopped. Scan "hit key" 55. The register has been restored and the address line of the door circuit a-20 will be stopped. . 56. Successfully discontinued the address line of a-20; Will check the BIOS ROM data area. The keyboard test is over. 57. The BIOS ROM data area was examined in half; Keep going. . 58. The data area of BIOS ROM is completed; Find < ESC > information. Unset interrupt testing. 59. The ESC > information has been cleared; Information has been shown; Testing of the upcoming DMA and interrupt controllers. . 5A. Display press "F2" button for setting. 5B. Test the basic memory address. 5C.. Test 640K base memory. Set up the disk to boot sector virus protection function. Testing of DMA page registers; The video memory will be tested. Test extended memory. Display the system configuration table. Video memory test; An upcoming test of DMA# 1 basic registers. . 62 start system boot with interrupt 19H. Testing of the basic register of DMA# 1; Testing of the DMA# 2 register. Test the extended memory address line. 63. Testing of basic registers through DMA# 2; Will check the BIOS ROM data area. . 64. The BIOS ROM data area is checked in half and continues. . 65. Conclusion of BIOS ROM data area; The DMA devices 1 and 2 will be programmed. . 66. The end of programming of DMA devices 1 and 2; Ready to use the no. 59 interrupt controller for initial preparation. The Cache registry is optimized for configuration. 67. The initial preparations for 8259 have ended; The keyboard test is about to begin. . 68. Make both external Cache and CPU internal Cache work. 6A.. Test and display external Cache values. 6C. Display blocked content. 6E. Display attached configuration information. 70. The detected error code is sent to the screen. 72. The detection configuration is incorrect. 74. Test the real-time clock. Scanning keyboard errors. The keypad. 7C.. Set the hardware interrupt vector. 7E.. Test the installation of a math processor. 80. At the beginning of the keyboard test, the keys are being cleared and checked, and the keyboard is about to be restored. Close programmable input/output devices. 81. Find the key to the error of the keyboard recovery; A test command to issue keyboard control ports. . The keyboard controller interface test is over and will be written to the command byte and the loop buffer for initial preparation. Check and install the fixed RS232 interface (serial port). 83. A command byte has been written to complete the initial preparation of the global data; You are going to check if there is a key locked. . 84. Check that the locked key is checked to check whether the memory is mismatched with the CMOS. Check and install fixed parallel port. 85. The size of the memory is checked; Displays soft errors and passwords or password-by-pass arrangements. . 86. The password has been checked; The program is about to be pre-arranged. Re-open programmable I/O devices and detect whether there is a conflict between fixed I/O. 87. Programming before completion; Programming of CMOS scheduling. . 88. Remove screen from CMOS scheduling; You're going to be programming later. Initialize the BIOS data area. 89. Programming after completion of the arrangement; The screen information is about to be displayed. . 8A. Display the first screen information. Expand the BIOS data area initialization. 8B. Information: the main and video BIOS are about to be blocked. . 8C. Successfully shielded the main and video BIOS, and will start programming for the post-cmos scheduling option. The floppy drive controller is initialized. 8D. Optional programming has been arranged, then the mouse and initial preparations have been checked. . 8E. Test the mouse and the initial preparation; The hard and floppy disk will be reset. . 8F. The floppy disk has been checked. The disk will be ready for initial preparation and then a floppy disk. . 90. End of floppy disk configuration; The presence of the hard disk is tested. The hard disk controller is initialized. 91. The hard disk has test ended; The hard disk is then configured. Local bus hard disk controller initialization. 92. Hard disk configuration completion; The data area to check the BIOS ROM. Jump to user path 2. 93. The data area of the BIOS ROM has been checked in half; Keep going. . 94. The data area of the BIOS ROM is checked, which is the size of the basic and extended memory. Close the a-20 address line. 95. Adjust the memory size in response to mouse and hard disk 47 support; Incoming inspection display memory. . 96. The inspection shows the recovery after storage; Upcoming C800:0 optional ROM control prior to initial preparation. The "ES section" registry is cleared. 97. C800: any initial preparations prior to the optional ROM control are completed, followed by the check and control of the optional ROM. . 98. Control of the optional ROM; Any processing required after the optional ROM reply control is pending. Find ROM selection. 99. Any initial preparation required after the optional ROM test is completed; The base address of the data area or printer that will set up the timer. . 9A. The return operation after the setting timer and the basic address of the printer; The rs-232 basic address is set. Screen ROM selection. 9B. Return after the rs-232 basic address; An initial preparation for the coprocessor test. . 9C. The initial preparation before the coprocessor test is completed; The coprocessor is then initialized. Establish power saving management. 9d.the coprocessor is ready for any initial preparation after the coprocessor test. . 9E. The initial preparation after the completion of the coprocessor, will check the extended keyboard, keyboard identifier, and number lock. Open hardware interrupts. 9F. Has been checked to extend the keyboard, to set up the identification mark, the number lock to be switched on or off, the keyboard identification command will be issued. . A0. Issuing keyboard identification commands; The keyboard identification logo is about to be restored. Set the time and date. A1. Recovery of keyboard identification mark; Then the cache memory is tested. . The speed buffer memory test is over. Any soft error will be displayed. Check keyboard lock. A3. Soft error display finished; The speed of the keyboard strike is about to be adjusted. . To adjust the speed of the keyboard, the waiting status of memory will be made. The initialization of the keyboard repeat input rate. A5. Memory waiting status is completed; The screen will then be cleared. . A6. Screen cleared; The parity and unmasking interrupts are to be launched. . A7. Enabled unmasked interrupts and parity; Any initial preparation required to control the optional ROM in E000:0. . A8. Control ROM is initially ready to end before E000:0, and then control E000: any initial preparation required after 0. Clear the "F2" key prompt. A9. Return from the control E000:0 ROM, which is about to take control of any initial preparation required after the optional ROM. . AA. The initial preparation after control of the optional roms is completed; The configuration of the system will be displayed. Scan the "F2" button. Enter Settings. AE. Clear the self - check mark. B0.. Check for non-critical errors. 2. Prepare to enter the operating system guide. B4. The buzzer rang. B6. Check password Settings (optional). B8.. Clear the full description table. BC.. Clear checksum check value. The BE program defaults to the control chip, which corresponds to the modulated binary default table. Clear screen (optional). BF test CMOS build value. . Detect virus and prompt for data backup. The C0 initializes the cache. Use interrupt 19 test guide. C1 memory self-check. Find the "55" and "AA" tags in the boot sector. C3 the first 256K memory test. C5 copies BIOS from ROM for quick self-check. C6 cache self-check. The CA detects the Micronies overspeed buffer memory (if it exists) and prepares the original. CC off unblocked interrupt handler.