电脑维修主板电路

A A B B C C D D E E 4 4 3 3 2 2 1 1 TITLE 1 SHEET COVER SHEET 5,6 DIMM1 / DIMM2 / DIMM3/DIMM4 USB CONNECTORS AC'97 CODEC & AUDIO 19 20 24 25 DDR TERMINATIONS A&B 21 LPC SUPER IO & FLOPPY CONNECTOR 22,23 SOUTH BRIDGE (VT8237) 15,16 PROCESSOR (SOCKET478) PCI SLOTS 1-5 AGP SLOT IDE CONNECTORS NORTH BRIDGE (PT880) ATX POWER CONNECTOR 26 29 30 Revision 0A CHIPSET PT880+8237 12,13,14 27 MS7008 System Chipset: Expansion Slots: CPU: On Board Chipset: PCI2.3 SLOT * 5 BIOS -- ISA EEPROM PT880 (North Bridge) Intel Northwood/Prescott LAN --RTL8110S / 8100C Controller: Intersil 6563 PWM: CLOCK --ICS 952911A + ICS 93733 Main Memory: AC'97 Codec --ALC655 VIA 8237/8235 (South Bridge) MSI 2 3 4 28 7,8,9,10,11 17,18 VIA 1394 VT6306 DDR * 2+2 (Max 4GB) 31 32 33 BLOCK DIAGRAM PWR MAP/CLOCK MAP GPIO/MEMORY/PCI/HW STRPPING VRM10.0(FMB1) MS7 ACPI CONTROLLER DLED & LAN CONNECTORS RTL8110S / 8100C LPC Super I/O -- W83697HF CLOCK & BUFFER SYNTHESIZER EMI PORT PARALLEL / SERIAL MS8 34 35 MS-7008 0 A COVER SHEET MICRO-STAR INt'L CO., LTD. 1 38Tuesday, June 17, 2003 Title Size Document Number R e v Date: Sheet o f 1 1 A A MSI Serial FS B P C I S lo t 3 ParallelFlash USB Port 7 VRM 10 IDE Secondary USB Port 3 Intel mPAG478B Processor 2-Phase PWM USB Port 4 Block Diagram P C I S lo t 2 Modules Floopy USB Port 0 P C I S lo t 5 VT8237/8235CE AC'97 Link LPC B u s USB PCI CNTRL ISL6563 64bit DDR P C I S lo t 4 P C I S lo t 1 USB Port 1 SATA prot1 and port2 83697HF 2 DDR AC'97 Codec LPC SIO USB Port 2 USB Port 5 PT880 IDE Primary PCI ADDR/DATA UltraDMA 33/66/100 V -Lin k Winbond USB Port 6 DIMM P C I in te rfa ce 1394 AGP 1.5V 2X/4X/8X Connector Modules 2 DDR DIMM P C I in te rfa ce 1 0 0 /1 G LA N chip Keyboard Mouse MS-7008 0 A BLOCK DIAGRAM MICRO-STAR INt'L CO., LTD. 2 38Tuesday, June 17, 2003 Title Size Document Number R e v Date: Sheet o f 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CK-409 AND BUFFER +2.5V MSI LAN-PHY VCC3_SB PT800 PLATFORM CLOCK GENERATOR MAP Intel mPAG478B Processor PT880 VT8237/8235CE PCI Slot 1~5PCI CLK 0~4 C L O C K G E N E R A T O R C K 409 CPU HOST CLK 2+2 DDR DIMM Modules MEM CLK 0~12/CLK#0~12 DCLKO DCLKI PCI CLK 1394 Winbond 83697HF LPC SIO PCI CLK Flash PCI CLK PCI CLK APIC 14.318MHZ 48MHZ 48MHZ AGP SLOTAGP CLK AGP CLK 3.3V 5V 5VSB 12V VRM 1.2V VREG 1.5V VREG DDR 2.5V VREG PROCESSOR VCCP 2.5VSB VREG FWH 3.3V LPC SUPER I/O 3.3V CK-409 3.3V PROCESSOR 1.2V NORTH BRIDGE VCC_AGP NORTH BRIDGE VCCP NORTH BRIDGE +2.5V NORTH BRIDGE SYSEM MEMORY VCC_DDR SOUTH BRIDGE RESUME 2.5V_SB SOUTH BRIDGE RESUME VCC3_SB SOUTH BRIDGE VCC3 SOUTH BRIDGE +2.5V LPC SUPER I/O VCC5 PT800 PLATFORM POWER DELIVERY MAP SOUTH BRIDGE RTC 3.3V PCI 1394 VCC3 3VSB VREG DDR DIMM1 / DIMM2 / DIMM3 2.5V 2.5V VREG DDR VTT 1.25VVTT 1.25V VREG AC97 VDD5AC97 VDD5 VREG AGP SLOT 1.5V MS-7008 0A PWR AND CLOCK MAP MICRO-STAR INt'L CO., LTD. 3 38Tuesday, June 17, 2003 Title Size Document Number Rev Date: Sheet of 1 1 A A NB GPI 0 GPI 1 GPIO 10 GPO 0 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 16 GPIO 17 GPIO 20 GPIO 21 I I I FunctionTypeGPIO Pin GPO 1 I I GPIO 18 GPIO 19 GPIO 15 I I MSI NA GPIO 22 PCI Slot 3 PCI_REQ#2 AD21 CLOCKREQ#/GNT# 18 (PCI_CLK0) INTD# INTC# INTC# INTA# CLK GEN PIN OUTMCP1 INT Pin PCI_GNT#1 PCI Slot 2 PCICLK0 PCI_REQ#1 AD20 PCICLK1 21 (PCI_CLK2) INTD# INTB# INTB# INTA# PCI_GNT#0 DEVICE PCI_REQ#0PCI Slot 1 PCI Config. PCICLK2 AD19 INTD# INTC# INTA# INTB# 19 (PCI_CLK1) IDSEL PCI_GNT#2 I FWH DIMM 1 MCLK0/MCLK#0 MCLK3/MCLK#3 MCLK2/MCLK#2 Signals DIMM 2 MCLK1/MCLK#1 Target CLOCKADDRESS DDR DIMM Config. Primary, Scondary IDE SB, NB MCLK4/MCLK#4 PCI slot 1-3, 1394,PCIRST#2 PCI RESET DEVICE 1010001B DEVICE HD_RST# MCLK5/MCLK#5 1010000B PCIRST#1 Function I GPI 4 GPI 0 I GPI 3 I I I TypeGPIO Pin GPI 2 GPI 1 Power well MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN default output default output 14 (PCI_CLK3) INTC# INTC# PCI_GNT#4 PCI Slot 5 PCICLK3 PCI_REQ#4 AD23 PCICLK4 INTD# INTB# INTA# PCI_GNT#3 PCI_REQ#3PCI Slot 4 AD22 INTD# INTA# INTB# 17 (PCI_CLK4) RESUME RESUME GPI 0 RESUME RESUME GPO 0 GPO 0 IDE2 CBD GPIO A GPIO B GPIO C GPIO D NB STR S NB STR S GTL PULL IOQ DEPH Pull UP through 1K ohms (unused) Pull UP through 1K ohms (unused) Pull UP through 1K ohms (unused) Pull UP through 1K ohms (unused) Pull UP through 1K ohms (unused) FWH I/O I/O I/O I/O MAIN MAIN MAIN MAIN MAIN MAIN I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NA NA NA NA NA NA NA NA NA default output HI HI HI DIMM 3 1010010B MCLK6/MCLK#6 MCLK7/MCLK#7 MCLK8/MCLK#8 MS-7008 0 A General Purpose Spec MICRO-STAR INt'L CO., LTD. 4 38Tuesday, June 17, 2003 Title Size Document Number R e v Date: Sheet o f 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CPU STRAPPING RESISTORS CPU GTL REFERNCE VOLTAGE BLOCK ALL COMPONENTS CLOSE TO CPU 0.63*Vccp CPU ITP BLOCK MSI CPU SIGNAL BLOCK VIH Min MaxTyp VIL 0.9 0.3 VIDPWRGD DC Specifications I t must rout to the enable pin of PWM and CK-409. V I DGD to Vccp delay time is from 1ms to 10ms. VIDGD rising time is 150ns. X7R X7R MS-7008 0 A Intel mPGA478B - Signals MICRO-STAR INt'L CO., LTD. 5 38Tuesday, July 08, 2003 Title Size Document Number R e v Date: Sheet o f ITP_TRST# ITP_TDO FERR# ITP_TMS BPM#4 ITP_TDI ITP_TCK BPM#3 HBR#0 BPM#2 BPM#1 BPM#5 CPU_GD H A #1 7 H A #4 HRS#1 H A #1 1 BPM#2 COMP0 H A #2 5 H A #1 6 H A #1 2 H A #9 H A #5 BPM#5 BPM#3 HREQ#1 HBR#0 BPM#0 INTR H A #2 7 H A #1 8 H A #1 0 BPM#1 HREQ#0 H A #3 0 H A #2 2 HRS#0 TESTHI11 H A #2 0 H A #1 4 TESTHI12 H A #2 6 H A #1 5 H A #2 3 H A #1 3 HREQ#4 HREQ#2 HREQ#3 H A #2 9 H A #2 4 H A #1 9 H A #8 H A #6 HRS#2 H A #3 1 H A #7 H A #2 8 H A #3 COMP1 H A #2 1 BPM#4 NMI FERR# CPURST# HD#58 ITP_TDO ITP_TMS BOOT HD#59 HD#56 SLP# HD#57 HDBI#2 ITP_TRST# HD#60 HD#63 A20M# THERMTRIP# HDBI#1 ITP_TCK CPU_GD HINIT# NMI ITP_TDI HD#61 HD#55 HDBI#3 SMI# HD#54 HDBI#0 HD#62 H D #1 H D #5 0 H D #4 0 H D #5 2 H D #3 3 H D #3 8 H D #2 7 H D #4 3 H D #2 6 H D #6 H D #3 9 H D #3 6 H D #4 H D #4 5 H D #1 2 H D #3 5 H D #5 3 H D #1 6 H D #2 3 H D #3 H D #4 7 H D #3 2 H D #2 5 H D #1 5 H D #3 7 H D #2 9 H D #2 2 H D #2 8 H D #1 7 H D #5 H D #4 4 H D #7 H D #2 1 H D #1 4 H D #4 1 H D #4 2 H D #4 9 H D #3 4 H D #8 H D #1 0 H D #5 1 H D #3 1 H D #1 3 H D #4 8 H D #2 4 H D #1 8 H D #3 0 H D #2 H D #4 6 H D #2 0 H D #1 9 H D #9 H D #1 1 VI D1 VI D0 VI D2 VI D4 VI D3 VI D5 H D #0 TESTHI1 TESTHI0 IERR# GTLREF GTLREF DBRESET RSP# H A #3 5 H A #3 4 H A #3 3 H A #3 2 IGNNE# STPCLK# SMI# A20M# SLP# INTR THERMTRIP# STPCLK# AP#0 AP#1 THERM# PROCHOT# PROCHOT# IGNNE# CPUMISS NMI HINIT# IERR# BPM#0 DBRESET PROCHOT# VID4 VID3 VID2 VID1 VID5 VID0 CPURST# VID[0..5] 34 CPU_GD26 THERMTRIP#34 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCC3 R29 X_27R RN11 8P4R-62R 12 34 56 78 R25 61.9R1% R28 300R R34 680R CPU1A ZIF-SOCKET478 {Priority} AB 1 Y1 W 2 V3 U4 T 5 W 1 R6 V2 T 4 U3 P6 U1 T 2 R3 P4 P3 R2 T 1 N5 N4 N2 M 1 N1 M 4 M 3 L2 M 6 L3 K1 L6 K4 K2 A E 25 A5 A4 A D 26 A C 26 AA24 AA22 AA25 Y21 Y24 Y23 W25 Y26 W26 V24 V 22 U 21 V 25 U 23 U 24 U 26 T 23 T 22 T 25 T 26 R 24 R 25 P 24 R 21 N 25 N 26 M 26 N 23 M 24 P 21 N 22 M 23 H 25 K 23 J2 4 L2 2 M 21 H 24 G 26 L2 1 D 26 F 26 E 25 F 24 F 23 G 23 E 24 H 22 D 25 J2 1 D 23 C 26 H 21 G 22 B 25 C 24 C 23 B 24 D 22 C 21 A 25 A 23 B 22 B 21 AE 1 AE 2 AE 3 AE 4 AE 5 AA21 AA6 F20 F6 AB4 AA5 Y6 AC4 AB5 AC6 H3 J3 J4 K5 J1 U6 AB22 AA20 AC23 AC24 AC20 AC21 AA2 AD24 AF23 AF22 F4 G5 F1 V5 AC1 H6 P1 L24 L25 K26 K25 J26 R5 L5 W23 P23 J23 F21 W22 R22 K22 E22 E5 D1 W4 Y3 E21 G25 P26 V21 AC3 V6 B6 Y4 AA3 W5 AB2 H5 H2 J6 G1 G4 G2 F3 E3 D2 E2 D4 C1 D5 E6 B3 C4 A2 C3 F7 B2 B5 C6 AB26 A22 AB23 AB25 A6 AD25 A7 AD 2 AE21 AF24 AF25 AD6 AD5 AF26 AD 3 AD1 AE26 A 35 # A 34 # A 33 # A 32 # A 31 # A 30 # A 29 # A 28 # A 27 # A 26 # A 25 # A 24 # A 23 # A 22 # A 21 # A 20 # A 19 # A 18 # A 17 # A 16 # A 15 # A 14 # A 13 # A 12 # A 11 # A 10 # A 9# A 8# A 7# A 6# A 5# A 4# A 3# DB R# VC C _S EN SE VS S_ SE N SE IT P _C LK 1 IT P _C LK 0 D63# D62# D61# D60# D59# D58# D57# D56# D55# D54# D 53 # D 52 # D 51 # D 50 # D 49 # D 48 # D 47 # D 46 # D 45 # D 44 # D 43 # D 42 # D 41 # D 40 # D 39 # D 38 # D 37 # D 36 # D 35 # D 34 # D 33 # D 32 # D 31 # D 30 # D 29 # D 28 # D 27 # D 26 # D 25 # D 24 # D 23 # D 22 # D 21 # D 20 # D 19 # D 18 # D 17 # D 16 # D 15 # D 14 # D 13 # D 12 # D 11 # D 10 # D 9# D 8# D 7# D 6# D 5# D 4# D 3# D 2# D 1# D 0# V ID 4# V ID 3# V ID 2# V ID 1# V ID 0# GTLREF3 GTLREF2 GTLREF1 GTLREF0 BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# REQ4# REQ3# REQ2# REQ1# REQ0# TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0 BCLK1# BCLK0# RS2# RS1# RS0# AP1# AP0# BR0# COMP1 COMP0 DP3# DP2# DP1# DP0# ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1# DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0# LINT1/NMI LINT0/INTR TESTHI9 TESTHI10 DBI0# DBI1# DBI2# DBI3# IERR# MCERR# FERR# STPCLK# BINIT# INIT# RSP# DBSY# DRDY# TRDY# ADS# LOCK# BNR# HIT# HITM# BPRI# DEFER# T C K TDI TDO TRST# THERMDA THERMDC THERMTRIP# PROCHOT# TMS IGNNE# SMI# A20M# SLP# RESERVED0 PWRGOOD RESET# TESTHI11 TESTHI12 RESERVED1 V ID P W R G D RESERVED2 RESERVED3 RESERVED4 BSEL0 BSEL1 GND/SKTOCC# V ID 5# BOOTSELECT OPTIMIZED/COMPAT# R47 61.9R1% RN15 8P4R-150R 12 34 56 78 C39 C0.1U16X R49 61.9R1% Q11 N-MMBT3904_SOT23 B C E R39 61.9R1% R26 4.7KR C55 C220P16X {VOLTAGE} R27 61.9R1% RN21 8P4R-62R 12 34 56 78 R63 100R1% R64 49.9R1% CP3 X_COPPER 1 2 R24 0R R32 61.9R1% R36 X_39R R31 X_150R RN16 8P4R-62R12 34 56 78 R37 220R R33 X_75R RN14 8P4R-150R12 34 56 78 R38 61.9R1% R272 4.7KR RN108 8P4R-4.7KR 1 3 5 7 2 4 6 8 R271 4.7KR R30 62R HDSTBN#3 7 CPUCLK# 31 CPUCLK 31 HRS#[0..2] 7 CPU_VID_GD 27 HDSTBN#1 7 INTR 14 HDSTBP#3 7 HDSTBP#1 7 HDSTBP#0 7 HDSTBN#2 7 HADSTB#0 7 HADSTB#1 7 HREQ#[0..4] 7 HDSTBP#2 7 HDSTBN#0 7 HA#[3..35]7 BSEL031,34 HIT#7 HITM#7 HD#[0..63]7 HDEFER#7 CPU_TMPA32 HBPRI#7 CPURST#7 FERR#14 HADS#7 HDBSY#7 HBNR#7 STPCLK#14 HINIT#14 HTRDY#7 HLOCK#7 A20M#14 HDRDY#7 SMI#14 SLP#14 IGNNE#14 HDBI#[0..3]7 VTIN_GND32 BSEL131,34 BOOT27 RSP#7 DP#3 7 DP#2 7 DP#1 7 DP#0 7 AP#0 7 AP#1 7 HBR#0 7 NMI_SB 14 THERM#13,31,32 CPUMISS13,34 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 D D C C B B A A CPU VOLTAGE BLOCK CPU DECOUPLING CAPACITORS MSI 1.2V 150mA VID Voltage is from 1.14V to 1.32V. It is derived from 3.3V. It should be able to source 150mA. I t d rives the power logic of BSEL[1:0] and VID[5:0]. V I D to VIDGD delay time is from 1ms to 10ms. V I D to VIDGD deassertion time is 1ms for max. Near p rocessor It support DC current if 100mA. DC vol tage drop should be less than 70mV. T h e ESL is less than 5nH, and the ESR is less than 0.3ohm. MS-7008 0 A Intel mPGA478B - Power MICRO-STAR INt'L CO., LTD. 6 38Tuesday, July 08, 2003 Title Size Document Number R e v Date: Sheet o f VCC_VID CPU_IOPLL VSSA VCCP VCCPVCCP VCCP VCCP VCCP VCC_VID C50 X_C10U10Y1206 C49 X_C10U10Y1206 C47 C22U10Y1206 C48 X_C10U10Y1206 C45 C10U10Y1206 C46 C10U10Y1206 C19 X_C1U10Y C33 X_C10U10Y1206 C13 X_C10U10Y1206 C15 X_C10U10Y1206 C16 X_C10U10Y1206 C12 X_C10U10Y1206 C22 C10U10Y1206 C35 C10U10Y1206 C29 C10U10Y1206 L2 10U100m_0805 L3 10U100m_0805 CPU1B ZIF-SOCKET478 {Priority} A 10 A 12 A 14 A 16 A 18 A 20 A8 A A 10 A A 12 A A 14 A A 16 A A 18 AA 8 A B 11 A B 13 A B 15 A B 17 A B 19 AB 7 AB 9 A C 10 A C 12 A C 14 A C 16 A C 18 AC 8 A D 11 A D 13 A D 15 A D 17 A D 19 AD 7 AD 9 A E 10 A E 12 A E 14 A E 16 A E 18 A E 20 AE 6 AE 8 A F 11 A F 13 A F 15 A F 17 A F 19 A F2 A F 21 A F5 A F7 A F9 B 11 B 13 B 15 B 17 B 19 B7 B9 C 10 C 12 A E 23 C 14 C 16 C 18 C 20 C8 D 11 D 13 D 15 D 17 D 19 D7 D9 E 10 E 12 E 14 E 16 E 18 E 20 E8 F 11 F 13 F 15 F 17 F 19 AD22 D10 A11 A13 A15 A17 A19 A21 A24 A26 A3 AA1 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC13 AC11 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 A D 10 A D 12 A D 14 A D 16 A D 18 A D 21 AD 4 A D 23 AD 8 A E 11 A E 13 A E 15 A E 17 A E 19 A E 22 A E 24 AE 7 AE 9 A F1 A F 10 A F 12 A F 14 A F 16 A F 18 A F 20 A F6 A F8 B 10 B 12 B 14 B 16 B 18 B 23 B 20 B 26 B4 B8 C 11 C 13 C 15 C 17 C2C 19 C 22 C 25 C5 C7 C9 D 12 D 14 D 16 D 18 D 20 D 21 D3D 24 D6 D8 E1 E 11 E 13 E 15 E 17 E 19 E 23 A D 20 A F4 A F3 E7 E9 F 10 F 12 F 14 F 16 F 18 F 2 F 22 F 25 F 5 F 8 G 21 G 6 G 24 E4E 26 G 3 H1 H 23 H 26 H4 J2 J2 2 J2 5 J5 K 21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 R4 R26 R23 R1 P5 P25 P22 P2 N6 N3 V23 V1 U5 U25 U22 U2 T6 T3 T24 T21 Y5 Y25 Y22 Y2 W6 W3 W24 W21 V4 V26 F 9 A9 VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C A VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VC C VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S V C C -IO P LL VC C -V ID VC C -V ID PR G VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VC C VSS C14 X_C10U10Y1206 C21 C0.1U16X C38 X_C100U2SP C11 C10U10Y1206 C26 C100U2SP C30 C10U10Y1206 C10 C10U10Y1206 {VOLTAGE} C9 X_C10U10Y1206 {VOLTAGE} C34 C10U10Y1206 A A B B C C D D E E 4 4 3 3 2 2 1 1 near NB MSI MS-7008 0A NORTH BRIDGE (PART 1 & PART4) MICRO-STAR INt'L CO., LTD. 7 38Tuesday, July 08, 2003 Title Size Document Number Rev Date: Sheet of HRCOMP HRCOMP GTLVREF_NB HCOMPVREF HCOMPVREF GTLVREF_NB HBR#0 HD#34 HD#15 HD#61 HD#56 HD#27 HD#8 HD#0 HD#10 HD#14 HD#43 HD#62 HD#12 HD#42 HD#50 HD#55 HD#52 HD#46 HD#38 HD#35 HD#22 HD#32 HD#40 HD#30 HD#37 HD#53 HD#63 HD#16 HD#45 HD#29 HD#7 HD#28 HD#36 HD#60 HD#21 HD#18 HD#41 HD#1 HD#11 HD#58 HD#47 HD#59 HD#24 HD#19 HD#13 HD#49 HD#4 HD#6 HD#57 HD#39 HD#44 HD#54 HD#51 HD#26 HD#23 HD#33 HD#20 HD#2 HD#17 HD#48 HD#9 HD#31 HD#3 HD#25 HD#5 HA#17 HA#4 HA#11 HA#25 HA#16 HA#12 HA#9 HA#5 HA#27 HA#10 HA#30 HA#22 HA#14 HA#26 HA#15 HA#23 HA#13 HA#29 HA#24 HA#19 HA#8 HA#6 HA#31 HA#7 HA#28 HA#3 HA#21 HA#35 HA#34 HA#33 HA#32 HA#18 HA#20 HREQ#1 HREQ#0 HREQ#4 HREQ#3 HREQ#2 HDBI#3 CPURST# HRS#1 HRS#0 HRS#2 HDBI#2 HDBI#1 HDBI#0 VCCP VCCP VCCP R83 49.9R1% C0.01U50X C283 R75 100R1% C0.01U50X C279 C0.01U50X C280 U5A PT880/PM880 B22 A20 F20 A21 B21 E23 C21 D21 E22 F21 C22 E21 D22 F22 C25 C24 D24 E24 E25 F26 B26 B23 E26 D25 E27 C23 F27 D27 D28 C27 C28 A22 C26 A19 C18 C16 E18 B19 E17 C19 C17 F16 F18 G18 D19 C20 D20 E19 F19 B18 D18 B17 A6 B13 J3 A5 K6 M5 M6 H19 G22 H11 H14 K7 J7 H17 F15 G14 G10 D9 C9 B9 F10 B7 A9 F9 E7 E9 F7 C7 A8 C8 D7 A7 D16 E16 B14 D15 E15 C14 E14 C15 D12 C13 B12 B10 C11 B11 A10 C12 H6 G7 J4 G6 H5 G3 H4 G4 K1 J5 H1 J6 J1 J2 K4 K3 C3 C4 B4 D3 A4 C5 D4 E4 E2 E3 F3 F4 C2 F1 G1 F2 F8 D8 E13 D13 H3 H2 D1 E1 F23 F25 F24 B6 D6 C6 E6 E28 F28 G15 C 2 9 F 2 9 H 2 7 N 1 3 N 1 4 N 1 5 N 1 6 N 1 7 N 1 8 N 1 9 N 2 0 R 1 3 T 1 3 U 1 3 P 1 3 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31 HA32 HA33 ADSTB0 ADSTB1 ADS BNR BPRI BREQ0 DBSY DEFFER DRDY HIT HITM HLOCK HTRDY HREQ0 HREQ1 HREQ2 HREQ3 HREQ4 RS0 RS1 RS2 DBI0 DBI1 DBI2 DBI3 CPURST HCLK HCLK HAVREF0 HAVREF1 HDVREF0 HDVREF1 HDVREF2 HDVREF3 GTLREF HRCOMP HCOMPVREF HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 DSTBP0 DSTBN0 DSTBP1 DSTBN1 DSTBP2 DSTBN2 DSTBP3 DSTBN3 RSP AP0 AP1 DP0 DP1 DP2 DP3 HA34 HA35 DPWR V T T V T T V T T V T T V T T V T T V T T V T T V T T V T T V T T V T T V T T V T T V T T R67 20.5R1% R90 100R1% R91 49.9R1% C0.01U50X C81 HA#[3..35]5 HDSTBN#3 5 HDSTBP#3 5 HDSTBP#1 5 HDSTBP#0 5 HDSTBN#2 5 HADSTB#05 HADSTB#15 HDSTBP#2 5 HDSTBN#0 5 HREQ#[0..4]5 HBR#05 HIT#5 HITM#5 HDEFER#5 HBPRI#5 HADS#5 HDBSY#5 HBNR#5 HTRDY#5 HDRDY#5 HLOCK#5 CPURST#5 DP#0 5 DP#1 5 DP#2 5 HD#[0..63] 5 NBHCLK31 NBHCLK#31 AP#15 AP#05 DP#3 5 HDSTBN#1 5 HRS#[0..2]5 HDBI#[0..3]5 RSP#5 A A B B C C D D E E 4 4 3 3 2 2 1 1 Decoupling capacitors DCLKI = DCLKx + 2 " D CLKO as short as passable MSI MS-7008 0A NORTH BRIDGE (PART 2) MICRO-STAR INt'L CO., LTD. 8 38Tuesday, July 08, 2003 Title Size Document Number Rev Date: Sheet of -DQS_7 -DQS_0 -DQS_3 -DQS_6 -DQS_2 -DQS_5 -DQS_1 -DQS_4 -CS0 -CS3 -CS2 -CS1 CKE0 CKE3 CKE2 CKE1 MAA4 MAA12 MAA13 MAA7 MAA1 MAA11 MAA9 MAA5 MAA6 MAA3 MAA15 MAA0 MAA8 MAA10 MAA14 MAA2 MD_6 MD_29 MD_41 MD_37 MD_43 MD_5 MD_10 MD_55 MD_56 MD_15 MD_2 MD_45 MD_0 MD_42 MD_44 MD_23 MD_28 MD_20 MD_38 MD_35 MD_11 MD_12 MD_30 MD_54 MD_9 MD_22 MD_50 MD_34 MD_4 MD_13 MD_3 MD_47 MD_57 MD_62 MD_39 MD_14 MD_49 MD_19 MD_36 MD_59 MD_26 MD_31 MD_8 MD_25 MD_58 MD_40 MD_7 MD_60 MD_48 MD_53 MD_24 MD_17 MD_61 MD_52 MD_63 MD_46 MD_51 MD_1 MD_33 MD_21 MD_32 MD_18 MD_16 MD_27 MVREF_NB MVREF_NB MAA3 MAA10 MAA13 MAA5 MAA6 MAA2 MAA12 MAA9 MAA15 MAA8 MAA4 MAA11 MAA1 MAA7 MAA0 MAA14 -DQM_2 -DQM_1 -DQM_7 -DQM_4 -DQM_5 -DQM_0 -DQM_6 -DQM_3 QBM_SBB0 QBM_MEB0 QBM_MEB1 QBM_SBB1 DCLKI DCLKO_ QBM_MEA1 QBM_SBA0 QBM_SBA1 QBM_MEA0 QBMMEB1 18 QBMSBB1 18 QBMSBB0 18 QBMMEB0 18 QBMMEA0 17 QBMSBA1 17 QBMSBA0 17 QBMMEA1 17 VCCPVCC_DDR VCC_DDR +2.5V VCC_DDR X_C33P50NC79 X_C33P50NC91 C1000P50X C281 C1000P50X C274 X_C33P50NC52 X_C33P50NC54 X_C33P50NC92 R85 1KR1% C0.1U16X CB138 X_C33P50NC41 X_C1U10Y CB136 C1U10Y CB64 C1000P50X C275 C0.1U16X CB135 X_C33P50NC74 X_C33P50NC58 C2.2U10