CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
FEATURES
● Automatic feed forward compensation
● Optimized for offline converter
● Double pulse suppression
● Current mode operation to 500 KHz
● High gain totem pole output
● Internally trimmed bandgap reference
● Undervoltage lockout with hysteresis
● Low start up current :< 0.3 mA
ORDERING INFORMATION
Device Package
DESCRIPTION LM3842A/3A/4A/5A D 8 SOP
LM3842A/3A/4A/5A N 8 DIP
The LM3842A is fixed frequency current-mode PWM controller. It is specially designed for Off-Line and
DC-to-DC converter applications with minimal external components.
This integrated circuit features a trimmed oscillator for precise duty cycle control, a temperature
compensated reference, high gain error amplifier, current sensing comparator, and a high current
totempole output ideally suited for driving a power MOSFET.
Protection circuitry includes built in under-voltage lockout and current limiting.
SIMPLIFIED BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS (TA= 25℃)
Characteristic Symbol Value Unit
Power Supply Voltage Vcc 30 V
Output Current I ± 1 A
Analog Inputes Voltage VIN -0.3 to 5.5V V
Error Amp Output Sink Current ISINK 10 mA
Power Dissipation PD 1 W
Storage Temperature Range Tstg -65 to 150 ℃
Lead Temperature (soldering 5 sec) T 260 ℃
HTC
1
5V
Reference
Vcc
Undervoltage
Lockout
Latching
PWM
Oscillator
VREF
Undervoltage
Lockout
+-
⑦ Vcc
⑥ Output
⑤ Ground
③ Current
Sense
Input
VREF ⑧
RT/CT ④
VFB ②
COMP ①
Error
Amplifie
r
R
R
1
2
3
4
8
7
6
5
Voltage
Feedback
Current
Sense
RT/CT
Vcc
OUTPUT
GND
VREFCompen sation
8 SOP/ 8 DIP PIN Configulation
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CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
ELECTRICAL CHARACTERISTIC
(Vcc=15V(Note 1), RT = 10kΩ, CT=3.3nF 0 ≤ TA ≤ 70℃ ; unless otherwise specified)
Characteristic Symbol Test Condition Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage VREF Tj = 25℃, IO=1 mA 4.90 5.00 5.10 V
Line Regulation Vo 12V ≤ Vcc ≤ 25V 2 20 mV
Load Regulation Vo 1mA ≤ Io ≤ 20mA 3 2.5 mV
Output Short Circuit Current Isc TA = 25℃ -85 -180 mA
OSCILLATOR SECTION
Normal Frequency FOSC Tj = 25℃ 47 52 57 kHz
Voltage Stability Sv 12V ≤ Vcc ≤ 25V 0.2 1 %
Amplitude Vosc 1.6 Vp-p
ERROR AMPLIFIER SECTION
Input B Current I BI -0.1 -2 μA
Feedback Input Voltage VFB Vo=2.5V 2.42 2.50 2.58 V
Open Loop Voltage Gain AVOL 2V≤ Vo ≤ 4V 65 90 dB
Power Supplier Rejection Ratio PSRREA 12V ≤ Vcc ≤ 25V 60 70 dB
Output Sink Current ISI VFB=2.7V, Vo - 1.1V 2 7 mA
Output source Current ISO V = 2.3V, Vo=5V -0.5 -1.0 mA
Output Voltage High VOH VFB=2.7V, RL=15kΩ to GND 5 6 V
Output Voltage Low VOL VFB=2.7V, RL=15kΩ to VRGR 0.8 1.1 V
CURRENT SENSE SECTION
Input Voltage Gain Av (Note 2 & 3) 2.85 3 3.15 V/V
Maximum Input Signal VMAX Vo=5V (Note 2) 0.9 1 1.1 V
Power Supply Rejection Ratio PSRRSC 12V ≤ Vcc ≤ 25V 70 dB
Input Bias Current I BI -2 -1.0 μA
OUTPUT SECTION
Output Voltage Low VOL Isink = 20mA 0.1 0.4 V
I inks = 20mA 1.5 2.2 V
Output Voltage High VOH Isource = 20mA 13 13.5 V
I ources = 20mA 12 13.0 V
Rise Time T Tj = 25℃, CL=1nF 45 150 nS
Fail Time T Tj = 25℃, CL=1nF 35 150 nS
UNDERVOLTAGE LOCKOUT SECTION
Start-up Threshold Vth 3842A / 3844A 14.5 16 17.5 V3843A / 3845A 7.8 8.4 9 V
Minimum Operating Voltage VCC(MIN) 3842A / 3844A 8.5 10 11.5 V(After Turn-On ) 3843A / 3845A 7.0 7.6 8.2 V
TOTAL STANDBY CURRENT
Start-up Current I ts Vcc=14V 0.17 0.3 mA
Operating Supply Current I CC 13 mA17
Zener Voltage V Icc = 25mA 30 38 V
Note: 1. Adjust Vcc above the start threshould before setting at 15V.
2. Parameter measured at trip point of latch with VFB - 0.
3. Comparator Gain defined as:
HTC
2
ΔV Output Compensation(pin FB)
ΔV Current Sanseinput(pin CS)
A
V
= ;
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CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
Fig.1 Open Loop Test Circuit
High peak currents associated with capacitive loads necessitate careful grounding techniques
Timing and bypass capacitors should be connected close to pin 5 in a single point ground.
The transistor and 5KΩ potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Fig.2 Under Voltage Lockout
LM3842A LM3843A/5A
VON 16V 8.4V
VOFF 10V 7.6V
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state.
Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch
with output leakage current.
Fig.3 Error Amp Configuration
HTC
3
1
2
3
4
8
7
6
5
COMP VREF
VFB VC
OUTPUT
GND
ISENSE
RT/CT
LM3842A 0.1
0.1
A
CT
OUTPUT
1K/1W
VREF
V1
RT
100K
2N
22224.7K
1K
5KISENSE
ADJUST
4.7K
E/A
ADJUST
Error amp can source or sink up to 0.5mA
2
1
-
+
Zi
Zf
COMP
VFB
0.5mA2.5V
7
ON/OFF COMMAND
TO REST OF IC
< 15mA
< 1mA
VOFF VON
VCC
ICC
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CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
Fig.4 Current Sense Circuit
Peak current (IS) is determined by the formula:
IS(MAX)
A small RC filter may be required to suppress switch transients.
Fig.5 Oscillator Waveforms and Maximum Duty Cycle
Oscillator timing capacitor, CT, is charged by VREF through RT, and discharged by an internal
current source. During the discharge time, the internal clock signal blanks the output to the
low state. Selection of RT and CT therefore determines both oscillator frequency and maximum
duty cycle. Charge and discharge times are determined by the formulas:
tc 0.55 RT CT
td RT CT ∫n( )
Frequency, then, is: f = (tc + td) -1
For RT>5KΩ, f
HTC
4
1
3
5
IS
ERROR
AMP 2R
R 1V CURRENT
SENSE
COMPARATOR
COMP
CURRENT
SENSE
GND
C
RS
R
~~ 1.0VRS
~~
0.0063 RT - 2.7
0.0063 RT - 4~~
1.8
RT CT
~~
8
4
5
VREF
RT/CT
GND
LARGE RT
SMALL CT V4
INTERNAL CLOCK
LARGE RT
SMALL CT V4
INTERNAL CLOCK
RT
CT
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CURRENT MODE PWM CONTROLLER LM3842A/3A/4A/5A
Fig.6 Shutdown Techniques
Shutdown of the LM3842A can be accomplished by two methods; either raise pin 3 above 1V or
pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the
PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that
the output will remain low until the next clock cycle after the shoutdown condition at pins 1 and/or 3
is removed. In one example, an externally latched shutdown may be accomplished by adding an
SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the
reference turns off, allowing the SCR to reset.
Fig.7 Slope Compensation
A fraction of the oscillator ramp can be resistively summed with the current sense signal to
provide slope compensation for converters requiring duty cycles over 50%.
Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes.
HTC
5
1
SHUTDOWN
COMP
8
3
VREF
ISENSE
1K
330Ω
500Ω
SHUTDOWN
TO CURRENT
SENSE-RESISTOR
8
4
3
ISENSE
R2
VREF
RT/CT
0.1μF
RT
CT
R1
RSENCEC
ISENSE
LM3842A
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CURRENT MODE PWM CONTROLLER
Fig.1 Output Dead Time Fig.2 Timing Resistor vs Frequency
Fig.3 Output Saturation Characteristics Fig.4 Error Amplifier Open Loop
Gain and Phase Frequency
PIN FUNCTION DESCRIPTION
Pin No. Function Description
1 Compensation This pin is the Error Amplifier output and is made available for loop
compensation.
2 Voltage This is the inverting input of the Error Amplitier. It is normally connected
Feedback to the switching power supply output through a resister divider.
3 Current Sense A voltage proportional to inductor current is connected to this input.
The PWM uses this information to terminate the output switch conduction.
4 RT/CT The Oscillator frequency and maximum Output duty cycle are
programmed by connecting resistor RT to VREF and capacitor CT
to ground. Operation to 500kHz is possible.
5 GND This pin is the combined control circuitry and power ground.
6 Output This output directly drives the gate of a power MOSFET. Peak currents
up to 1.0A are sourced and sunk by this pin.
7 Vcc This pin is the positive supply of the control IC.
8 VREF This is the reference output. It provides charging current for capacitor
CT through resistor RT.
HTC
6
LM3842A/3A/4A/5A
10-3 2 4 6 8 10-1 2 4 86
4
2
0
1
3
SINK (VOL)
VCC=15V
TA=25℃
SOURCE (VCC-VOH)
V S
AT
, O
ut
pu
t S
at
ur
at
ion
V
olt
ag
e
(V
Io, Output Load Current (A)
80
50
20s
ist
er
(k
8.0
5.0
1.0M
R T
, T
im
ing
R
e
2.0
0.8
10k 20k 50k100k 500k200k
Ω
fosc, Frequency (kHz)
CT=10nF
CT=5.0nF CT=2.0nF
CT=1.0nF
CT=500pF
CT=200pF
CT=100pF
100
30)
10R
T(k
Ω
3
1M100k10k1k100
fosc, Frequency(Hz)
CT=100nF
CT=47nF
CT=22nF
CT=10nF
CT=4.7nF
CT=2.2nF
CT=10nF
80
60
40
10K 100K 1M1K100
0
-135
10
-180
0
-45
20
Fosc, Frequency (Hz)
-90
10M
A V
OL
, O
pe
n-
Lo
op
V
olt
ag
e
Ga
in
(d
Φ,
E
xc
es
s P
ha
se
D
eg
re
eGain
Phase
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