810主板电路图

A A A A INTEL® PENTIUM® III & INTEL® CELERON (R) PROCESSOR/ 810E2 CHIPSET UNIVERSAL SOCKET 370 PLATFORM UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS REVISION 1.0 Title Page Cover Sheet Block Diagram 370-pin socke t 82810e Display Cache System Memory ICH2 FWH & UDAM 100 IDE1-2 Super I/O PCI Connectors USB Connectors AC97 CODEC Audio I /O Kybrd / Mse / F. Disk / Gme Connectors Digi tal Video Out Video Connectors Front Panel & CNR ATX Power & H/W M onitor Voltage Regulators System Configuration 1 2 3 , 4 7, 8, 9 10 11, 12 13, 14 15 16 17, 18 19 20 21 22 23 24 25 31 32 ** Please note these schematics are subject to change. THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLES. Information in this document is provided in connection w ith Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel 's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particu lar purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, l i fe saving o r life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel® Celeron(R) processor and Intel® 810e2 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copyright (c) Intel Corpora tion 2001. * Third-party brands and names are the property of thei r respective owners. 5AGTL Termination Clock Synthesi zer 6 WOL, WOR & 2S1P 26 35, 36 Pullup Resistors UMB Circuits Unused Gates & Decoupling capacitors 27, 28 29, 30 33, 34 Intel® 810e2 Chipset Universal Socke t 370 CRB Cover Sheet 36 1.0 9/02/01 1 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. Last Revision Date: Sheet: of Title: intel A A A A D A T A C T R L A D D R Term VRM ICH2 Keyboard Mouse Floppy ParallelSerial 1 SIO Clock P C I C O N N 1 P C I C O N N 2 P C I C O N N 3 Block Diagram 2 DIMM Modules USB Port 1-4 CNR CONNECTOR C T R L D A T A A D D R IDE Primary IDE Secondary UltraDMA/100 PCI CNTRL PCI ADDR/DATA AC'97 Link FirmWare Hub L P C B us GMCH Game Port Display Cache Memory Out Device Digital Video 370-PIN SOCKET PROCESSOR GTL BUS USB AUDIO CODEC Serial 2 Intel® 810e2 Chipset Universal Socke t 370 CRB Block Diagram 36 1.0 9/02/01 2 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. Last Revision Date: Sheet: of Title: intel A A A A 370 - Pin Socket Part 1 Intel® 810e2 Chipset Universal Socket 370 CRB HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HD#63 370-PIN SOCKET PART 1 36 1.0 9/02/01 3 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. R Last Revision Date: Sheet: of Title: intel HA#[31:3] HD#[63:0] HA#16 HD#11 HD#2 HA#12 HA#11 HA#3 HD#53 HD#34 HD#29 HA#30 HA#13 HA#9 HD#28 HD#17 HA#15 HD#61 HD#57 HD#26 HD#10 HD#3 HD#59 HD#20 HD#15 HD#13 HD#6 HD#0 HA#26 HA#19 HD#42 HD#25 HD#16 HD#14 HD#9 HD#8 HD#7 HA#6 HA#5 HD#55 HD#47 HD#46 HD#5 HA#25 HA#18 HA#14 HA#4 HD#52 HD#45 HD#23 HD#4 HA#28 HD#32 HD#31 HD#44 HD#35 HD#33 HD#18 HA#17 HD#50 HD#43 HD#36 HD#22 HD#21 HA#31 HA#27 HA#22 HD#58 HD#54 HD#49 HD#48 HD#40 HD#1 HA#23 HA#10 HD#56 HD#12 HA#20 HD#30 HA#21 HA#8 HA#7 HD#62 HD#51 HD#41 HD#38 HD#24 HA#24 HD#60 HD#39 HD#27 HA#29 HD#37 HD#19 HA#[31:3] 5,7 HD#[63:0] 5,7 VID1 16,29 RS#[2:0]7 HREQ#[4:0] 5,7 VID2 16,29 VID3 16,29 VID0 16,29 33 TUALDETVTTPWRGD 33 VID4 16,29 VCCVID VTT VTT VTT R340 1K U1A Socket 370_9 W1 T 4 N1 M6 U1 S3 T 6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8 D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 AH26 AH22 AK28 A M 34 A H 2 A D 2 Z2 V 2 M 2 D 18 H 2 D 2 A L3 A K 4 A G 5 A C 5 Y 5 U 5 Q 5 L5 G 5 D 4 B 4 A M 6 A J7 E 7 B 8 A M 10 A J1 1 E 11 B 12 A M 14 A J1 5 E 15 B 16 A M 18 A J1 9 E 19 F 20 B 20 A M 22 A J2 3 D 22 F 24 B 24 A M 26 A J2 7 D 26 F 28 B 28 A M 30 D 30 A F 32 A B 32 X 32 T 32 P 32 F 32 B 32 A H 34 A D 34 Z 34 V 34 R 34 M 34 H 34 D 34 AK36 A F 36 X 36 T 36 P 36 K 36 F 36 A 37 A C 33 A J3 A L1 A N 3 Y 37 AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 X6 AC1 W3 AF4 AL35 AM36 AL37 AJ37 AK18 AH16 AH18 AL19 AL17 C33 C31 A33 A31 E31 C29 E29 A29 AH20 AK16 AL21 AN11 AN15 G35 AL13 U37 U35 S37 S33 E23 AN21 AA35 AA33 B 26 C 3 A K 2 A F 2 A B 2 T2 P 2 K 2 F4 E 5 A M 4 A E 5 A A 5 W 5 S 5 N 5 J5 F2 D 6 B 6 A M 8 A J9 E 9 B 10 A M 12 A J1 3 E 13 B 14 A M 16 A J5 A J1 7 E 17 B 18 A M 20 A J2 1 D 20 F 22 A M 24 A J2 5 D 24 F 26 A M 28 A J2 9 D 28 A K 34 F 30 B 30 A M 32 A H 32 Z 32 V 32 R 32 M 32 H 32 A F 34 A B 34 X 34 T 34 P 34 K 34 F 34 B 34 A H 36 B 22 V 36 R 36 H 36 D 36 D 32 A D 32 A H 24 F 14 K 32 A A 37 Y 35 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 RS#0 RS#1 RS#2 G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D V TT P W R G D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D GND/VID4 T U A LD E T G N D G N D G N D G N D G N D G N D G N D R S V D -N C G N D D Y N _O E G N D HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 VID0 VID1 VID2 VID3 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V TT V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID V C C V ID 1 1 A A FSB 66M 100M 133M rsvd near VCMOS Processor PinVCMOS Decouping 370 - Pin Socket Place 0603 Paclage Part2 Place Site w/in 0.5" Do Not stuff C of clock pin (W37) GTLREF Generation Circuit Use 0603 Packages and distribute within 500 mils of VREF pins 1 BSEL#0 0 01 11 BSEL#1 0 0 CMOSREF CMOSREF Generation Circuit No-stuff R199 page33 see page 34 see page 4 150 Intel® 810e2 Chipset Universal Socket 370 CRB 370-Pin Socket Part 2 36 1.0 9/02/01 4 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. R Last Revision Date: Sheet: of Title: intel GTLREFA GTLREFA A20M# 13 VTIN2 16,28 BPRI# 5,7 HITM# 5,7 BNR# 5,7 STPCLK# 13 INTR 13 HLOCK# 5,7 HTRDY# 5,7 IGNNE# 13 CPUSLP# 13 HIT# 5,7 DRDY# 5,7 BSEL#1 31 DEFER# 5,7 VCMOS 14 HADS# 7 BSEL#0 31 SMI# 13 DBSY# 5,7 APICD113,32 APICD013,32 CPUHCLK6 CPURST#7 APICCLK_CPU6 CPU_PWGD13 ITPRDY#5 ITPCLK6 DBRESET#27 BR0# 5 GTLREF 7 CMOSREF NMI 13 FERR# 13,32 INIT# 13,15 THERMTRIP# 33 THRMDN 16,28 33 TUAL5 ITPTCK33 VCC2_5 VTT VTT V3SBV3SB VTT1_5 VTT1_5 VTT VCC 2_5 VTT VCCVID VTT C2 X18PF BC3 0.1UF R15 0 R340 1K R9 330 U1B Socket 370_9 X2 AG1 C37 E21 AJ33 AJ31 AN29 AL29 AL31 AH28 S35 W33 U33 E27 AN35 AN37 AN33 AL33 AK32 J37 A35 G33 E37 C35 E35 N33 N35 N37 Q33 Q35 Q37 AK30 AM2 F10 W35 Y1 R2 G37 L33 J35 L35 J33 W37 Y33 AK26 AH4 X4 A B 36 A D 36 Z 36 E 33 F 18 K 4 R 6 V 6 A D 6 A K 12 A K 22 AH14 AN17 AN25 AN19 AK20 AN27 AL23 AL25 AL27 AN31 AE37 AE33 AG35 AH30 AJ35 M36 L37 AG33 AC35 AG37 AE35 AC37 AL11 AN13 AN23 B36 AK24 V4 RESVD21(BR1#) EDGCTRL/VRSEL CPUPRES# VCOREDET BSEL0# BSEL1# BR0# THRMDN THRMDP THERMTRIP# RTTCNTR PLL1 PLL2 SLEWCNTR TDI TDO TRST# TCK TMS PREQ# PRDY# BP2# BP3# BPM0# BPM1# RSRVD6 RSRVD7 RSRVD8 RSRVD9 RSRVD10 RSRVD11 RSRVD12/JBSEL1# RSRVD13 RSRVD15 RSRVD16 RSRVD17 RSRVD18 RSRVD19 RSRVD20 PICD0 PICD1 PICCLK BCLK CLKREF PWRGOOD RESET# RESET2# V _C M O S V 1_ 5 V 2_ 5 V R E F 0 V R E F 1 V R E F 2 V R E F 3 V R E F 4 V R E F 5 V R E F 6 V R E F 7 BNR# BPRI# TRDY# DEFER# LOCK# DRDY# HITM# HIT# DBSY# ADS# FLUSH# A20M# STPCLK# SLP# SMI# LINT0/INTR LINT1/NMI INIT# FERR# IGNNE# IERR# RSP# AP0# AP1# RP# BINIT# AERR# BERR# R1 1K R339 150,1% R23 X0 R11 150 R275 22 PR3 110,%1 MC1 4.7UF R346 1K R6 1k BC5 0.1UF R12 150 R3 150 PR5 75,1% R4 150 R317 0 R373 330 R316 0 R14 1K +C6 33uF (C size) J1 HEADER 15X2 12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 R33 90.9, 1% R5 330 R199 1.8K PR4 110,%1 BC228 0.1UF R319 243,1% PR6 150,1% R345 1k R7 PR1 150,1% BC6 0.1UF R374 14 R338 75.1% C12 10PF BC4 0.1UF R10 680 R318 243.1% L2 4.7UH/SMD-0805 BC1 0.1UF Q27 FDN335N PR2 150,1% R8 150 BC2 0.1UF R13 1K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A AGTL Termination " One Cap for each 2 R-Pack " HEATSINK GROUNDING Intel® 810e2 Chipset Universal Socket 370 CRB AGTL TERMINATION 36 1.0 9/02/01 5 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. R Last Revision Date: Sheet: of Title: intel HA#23 HA#17 HA#22 HA#31 HA#19 HA#21 HA#25 HA#10 HA#13 HA#16 HA#3 HA#9 HA#20 HA#24 HA#30 HA#28 HA#15 HA#12 HA#5 HA#7 HA#11 HA#6 HA#8 HA#4 HA#14 HA#27 HA#29 HA#26 HD#15 HD#1 HD#0 HD#6 HD#4 HD#9 HD#5 HD#8 HD#10 HD#12 HD#24 HD#21 HD#17 HD#23 HD#16 HD#3 HD#20 HD#7 HD#18 HD#11 HD#30 HD#13 HD#14 HD#2 HD#19 HD#29 HD#31 HD#26 HD#25 HD#35 HD#59 HD#48 HD#52 HD#40 HD#60 HD#62 HD#61 HD#56 HD#57 HD#55 HD#46 HD#58 HD#63 HD#53 HD#50 HD#54 HD#45 HD#27 HD#51 HD#44 HD#42 HD#47 HD#41 HD#49 HD#22 HD#38 HD#39 HD#37 HD#28 HD#34 HD#36 HD#43 HD#[63:0] HA#[31:3] HA#18 HD#32 HD#33 BNR# 4,7 HA#[31:3] 3,7 HD#[63:0] 3,7 HREQ#2 3,7 HLOCK# 4,7 HITM# 4,7 HIT# 4,7 DRDY# 4,7 DBSY# 4,7 HREQ#4 3,7 BPRI# 4,7 HREQ#0 3,7 ITPRDY# 4 BR0# 4 HREQ#1 3,7 HTRDY# 4,7 DEFER# 4,7 HREQ#3 3,7 VTT1_5 VTT1_5 VTT1_5VTT1_5 VTT1_5 RN27 56/8P4R 1 3 5 7 2 4 6 8 R24 150 BC14 0.1UF BC13 0.1UF U1C Socket 370_9 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 GD32 GD33 GD34 GD35 GD36 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND BC11 0.1UF RN25 56/8P4R 1 3 5 7 2 4 6 8 BC18 0.1UF BC17 0.1UF RN21 56/8P4R 1 3 5 7 2 4 6 8 RN13 56/8P4R 1 3 5 7 2 4 6 8 RN16 56/8P4R 1 3 5 7 2 4 6 8 RN6 56/8P4R 1 3 5 7 2 4 6 8 RN2 56/8P4R 1 3 5 7 2 4 6 8 RN24 56/8P4R 1 3 5 7 2 4 6 8 RN8 56/8P4R 1 3 5 7 2 4 6 8 BC15 0.1UF RN7 56/8P4R 1 3 5 7 2 4 6 8 MC3 4.7UF RN15 56/8P4R 1 3 5 7 2 4 6 8 BC12 0.1UF RN18 56/8P4R 1 3 5 7 2 4 6 8 RN1 56/8P4R 1 3 5 7 2 4 6 8 RN4 56/8P4R 1 3 5 7 2 4 6 8 RN19 56/8P4R 1 3 5 7 2 4 6 8 BC21 0.1UF RN26 56/8P4R 1 3 5 7 2 4 6 8 BC16 0.1UF BC7 0.1UF RN14 56/8P4R 1 3 5 7 2 4 6 8 RN11 56/8P4R 1 3 5 7 2 4 6 8 RN20 56/8P4R 1 3 5 7 2 4 6 8 RN3 56/8P4R 1 3 5 7 2 4 6 8 RN23 56/8P4R 1 3 5 7 2 4 6 8 BC10 0.1UF RN17 56/8P4R 1 3 5 7 2 4 6 8 RN5 56/8P4R 1 3 5 7 2 4 6 8 BC20 0.1UF BC19 0.1UF BC9 0.1UF RN10 56/8P4R 1 3 5 7 2 4 6 8 BC8 0.1UF RN28 56/8P4R 1 3 5 7 2 4 6 8 RN22 56/8P4R 1 3 5 7 2 4 6 8 RN9 56/8P4R 1 3 5 7 2 4 6 8 MC2 4.7UF R25 10 A A A A Clock Synthesizer - Place all decoupling caps as close to VCC/GND pins as possible Notes: Minimize Stub Length from CLK14 trace to JP20A. - PCI_0/ICH pin has to go to the ICH. - CPU_ITP pin must go to the ITP. It is the only CPU CLK that can be shut off through the SMBUS interface. (This clock cannot be turned off through SMBus) APIC Clk Strap JP20A 16 MH z 33 MH z in ou t Intel® 810e2 Chipset Universal Socket 370 CRB Clock Synthesize r 36 1.0 9/02/01 6 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. Last Revision Date: Sheet: of Title: intel D C L K MEMCLK2 MEMCLK1 MEMCLK4 MEMCLK7 MEMCLK3 MEMCLK5 MEMCLK0 MEMCLK6 DRAM_1 XTAL_IN CPU_0_1 DRAM_7 MEMV3PCIV3 3V66_0 L_VCC2_5 XTAL_OUT USBV3 APIC_1 DRAM_0 DRAM_2 DRAM_3 DRAM_4 DRAM_5 DRAM_6 S E L1 _P U 3V66_1 PCI_3 L_CKVDDA CPU_2REFCLK APIC_0 DCLK_WR 8 FREQSEL 9,31 APICCLK_ICH 13 CPUHCLK 4 GMCHHCLK 7 ITPCLK 4 SLP_S3# 14,16,30 CK_SMBDATA 25 CK_SMBCLK 25 ICH_CLK1414 ICH_3V6614 GMCH_3V668 PCLK_0/ICH13 DOTCLK9 USBCLK14,16 PCLK_615 PCLK_518 PCLK_416 PCLK_318 PCLK_217 PCLK_117 FMOD131 SIO_CLK2414,16 MEMCLK[7:0] 11,12 33 VTTPWRGD12 TUAL5 33 APICCLK_CPU 4 VCC_CLOCK VCC_CLOCK VCC_CLOCK VCC2_5 VCC3_3 VCC3_3 VCC_CLOCK 0.1UF C22A 0.1UF C8A R26A 8.2K CPU APIC USB REF CK810e 3V66 PCI Memory U2A 7 8 55 54 52 50 49 11 12 13 15 16 18 19 20 1 31 30 46 45 43 42 40 39 37 36 28 29 25 26 51 53 2 9 10 21 27 33 38 44 22 48 56 5 6 14 17 24 35 41 47 23 3 4 34 32 3V66_0 3V66_1 APIC_0 APIC_1 CPU_0 CPU_1 CPU_2/ITP PCI_0/ICH PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 PCI_6 PCI_7 REF0 SCLK SDATA SDRAM_0 SDRAM_1 SDRAM_2 SDRAM_3 SDRAM_4 SDRAM_5 SDRAM_6 SDRAM_7 SEL0 SEL1 USB_0 USB_1 VDD2_5[0] VDD2_5[1] V D D 3_ 3[ 0] V D D 3_ 3[ 1] V D D 3_ 3[ 2] V D D 3_ 3[ 3] V D D 3_ 3[ 4] V D D 3_ 3[ 5] V D D 3_ 3[ 6] V D D 3_ 3[ 7] VDD_A VSS2_5[0] VSS2_5[1] V S S 3_ 3[ 0] V S S 3_ 3[ 1] V S S 3_ 3[ 2] V S S 3_ 3[ 3] V S S 3_ 3[ 4] V S S 3_ 3[ 5] V S S 3_ 3[ 6] V S S 3_ 3[ 7] VSS_A XTAL_IN XTAL_OUT D C L K PWRDWN# R32A 33 .001UF C6A R54A 10K .1UF C16A BC23 X10PF R36A 22 R347 0 .001UF C13A .1UF C18A .001UF C15A R348 130 R35A 22 R 5 1 A 10 R45A 22 0.1UF C25A R41A 22 Q29 FDN359AN R52A 33 + 22UF C11A 1 2 Q28 2N7002 .001UF C23A .001UF C17A .001UF C7A R42A 33 R27A 33 R38A 33 .001UF C9A R49A 33 R37A 22 L6A 1 2 L4A 1 2 R31A 10 R33A 22 + 22UF C4A 1 2 12PF C21A R47A 22 + 4.7UF C26A 1 2 R28A 33 R53A 22 + 22UF C19A 1 2 R44A 33 Y1A XT AL 14.318MHZ1 2 JP1A 12PF C20A 0.1UF C5A 0.1UF C10A R29A 33 R43A 22 R39A 22 L 3 A 1 2 R34A 22 R50A 22 BC22 X10PF 0.1UF C12A 0.1UF C14A L2A 1 2 R30A 33 R40A 33 .001UF C24A R48A 33 R46A 33 L5A 1 2 A A A A 82810E, PART 1: HOST INTERFACE Place site w/in 0.5" of clock ball (V6) Do not Stuff C365A Intel® 810e2 Chipset Universal Socke t 370 CRB 82810E, Part 1: Host Interface 36 1.0 9/02/01 7 IAMG Platform Apps Engineering 1900 Prairie City Road Folsom, Ca. 95630 REV. Last Revision Date: Sheet: of Title: intel HA#13 HA#26 HA#6 HD#16 HD#17 HREQ#0 HA#4 HD#29 HREQ#4 HD#18 HD#30 HD#31 HD#43 HD#44 HD#49 HD#5 HD#6 HA#18 HA#25 HD#1 HD#11 HD#25 HD#40 HD#62 RS#1 HA#27 HD#46 HD#48 HA#10 HA#9 HD#2 HD#63 HREQ#3 HA#20 HA#21 HD#23 HD#24 HD#53 HREQ#1 HA#24 HA#3 HD#47 HD#51 RS#2 HD#12 HD#19 HD#3 HD#35 HD#36 HD#52 HD#55 HD#8 HD#9 HA#11 HD#26 HD#14 HD#20 HD#21 HD#4 HD#50 HD#57 HA#15 HA#22 HA#30 HA#7 HD#15 HD#28 HD#41 HD#56 HD#61 HREQ#2 HA#28 HA#31 HA#5 HD#0 HD#59 HA#29 HD#34 HD#38 HA#16 HA#19 HA#8 HD#13 HD#42 HD#45 HD#54 HD#58 HD#60 HD#7 HA#23 HD#10 HD#32 HD#39 RS#0 HA#12 HA#14 HA#17 HD#22 HD#27 HD#33 HD#37 GMCHGTLREF CPURST#4 HLOCK#4,5 HTRDY#4,5 GMCHHCLK6 PCIRST#15,16,24,32 DEFER#4,5 HADS#4 BNR#4,5 BPRI#4,5 DBSY#4,5 DRDY#4,5 HIT#4,5 HITM#4,5 HD#[63:0] 3,5 HA#[31:3]3,5 HREQ#[4:0]3,5 RS#[2:0]3 GTLREF4 VCC1_8 VTT1_5 HOST INTERFACE U 3 A INTEL 82810E PART1 N3 T3 T1 M4 R3 N1 M5 W13 W1 U4 W3 W4 T5 W2 V2 AC2 AA2 Y3 AB3 AA1 AB2 AC3 AA3 Y2 AB5 AC4 Y1 AC5 U5 Y4 AB1 U1 V4 V1 T4 U2 U3 Y5 W5 AB7 AC8 AA7 Y8 W7 AC6 W9 AC9 Y7 AA10 W8 AB8 AC10 AB13 AB10 AB9 AB11 Y10 AB16 AB12 Y11 AA6 Y9 AC12 W11 AC11 W12 AA11 AA13 Y13 Y12 AC14 AB6 AA15 AC15 Y14 AC13 AA14 AB14 Y17 Y15 AC17 AC16 Y6 AA18 AB15 W15 AB18 W17 AA17 W18 W16 AC19 Y16 AA5 AB19 Y18 AC18 AB17 AA9 V5 AC7 P1 R1 R4 T2 P4 R2 R5 N4 M2 N5 P2 N2 B 20 P6 V 17 F 14 F 10 F 8 F 7 V 16 V 15 V 14 V 10 V9 V8 V7 F 17 F 16 Y 22 K 11 K 10 L1 4 L1 3 L1 2 L1 1 L1 0 M 14 M 13 M 12 V 18 M 11 M 10 N 14 N 13 N 22 J2 2 Y 19 C 19 E 22 K 14 K 13 K 12 V6 U 18 AB4 P5 ADS# BNR# BPRI# DBSY# DEFER# DRDY# GTLREFA GTLREFB HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA3# HA30# HA31# HA4# HA5# HA6# HA7# HA8# HA9# HD0# HD1# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD2# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD3# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD4# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD5# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD6# HD60# HD61# HD62# HD63# HD7# HD8# HD9# HIT# HITM# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HTRDY# RESETB RS0# RS1# RS2# V C C 1_ 8[ 0] V C C 1_ 8[ 1] V C C _C O R E [0 ] V C C _C O R E [1 0] V C C _C O R E [1 1] V C C _C O R E [1 2] V C C _C O R E [1 3] V C C _C O R E [1 ] V C C _C O R E [2 ] V C C _C O R E [3 ] V C C _C O R E [4 ] V C C _C O R E [5 ] V C C _C O R E [6 ] V C C _C O R E [7 ] V C C _C O R E [8 ] V C C _C O R E [9 ] V S S [0 ] V S S [1 0] V S S [1 1] V S S [1 2] V S S [1 3