RTL8019AS-new

RTL8019AS Realtek Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP) SPECIFICATION REALTEK SEMI-CONDUCTOR CO., LTD. HEAD OFFICE 1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C. TEL:886-35-780211 FAX:886-35-776047 OFFICE 3F, NO. 56, WU-KUNG 6 RD., TAIPEI HSIEN, TAIWAN, R.O.C. TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097 LS003.7 1996.02.08 LS003.8 2000.07.31 2 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS CONTENTS 1. FEATURES 3 2. GENERAL DESCRIPTION 4 3. PIN CONFIGURATION 5 4. PIN DESCRIPTION 4.1. Power Pins 6 4.2. ISA Bus Interface Pins 6 4.3. Memory Interface Pins (including BROM, EEPROM) 7 4.4. Medium Interface Pins 8 4.5. LED Output Pins 8 5. REGISTER DESCRIPTIONS 5.1. Group 1: NE2000 Registers 9 5.1.1. Register Table 9 5.1.2. Register Functions 11 5.1.2.1. NE2000 Compatible Registers 11 5.1.2.2. RTL8019AS Defined Registers 16 5.2. Group 2: Plug and Play (PnP) Registers 23 5.2.1. Card Control Registers 24 5.2.2. Logical Device Control Registers 25 5.2.3. Logical Device Configuration Registers 25 6. FUNCTIONAL DESCRIPTIONS 6.1. RTL8019AS Configuration Modes 27 6.2. Plug and Play 29 6.2.1. Initiation Key 29 6.2.2. Isolation Protocol 30 6.2.3. Plug and Play Isolation Sequence 34 6.2.4. Reading Resource Data 35 6.2.5. PnP auto detect mode 36 6.3. 9346 Contents 37 6.4. Boot ROM 38 6.5. LED Behaviors 40 6.6. Loopback Diagnostic Operation 42 6.6.1. Loopback Operation 42 6.6.2. To implement Loopback Test 43 7. Electrical Specification and Timings 7.1. Absolute Maximum Ratings 46 7.2. D.C. Characteristics 46 7.3. A.C. Timing Characteristics 46 LS003.8 2000.07.31 3 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS 1. FEATURES ! 100-pin PQFP ! RTL8019 software compatible ! Supports PnP auto detect mode (RTL8019AS only) ! Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2, 10BaseT ! Software compatible with NE2000 on both 8 and 16-bit slots ! Supports both jumper and jumperless modes ! Supports Microsoft‘s Plug and Play configuration for jumperless mode ! Supports Full-Duplex Ethernet function to double channel bandwidth ! Supports three level power down modes: - Sleep - Power down with internal clock running - Power down with internal clock halted ! Built-in data prefetch function to improve performance ! Supports UTP, AUI & BNC auto-detect (RTL8019AS only) ! Supports auto polarity correction for 10BaseT ! Support 8 IRQ lines ! Supports 16 I/O base address options ― and extra I/O address fully decode mode (RTL8019AS only) ! Supports 16K, 32K, 64K and 16K-page mode access to BROM (up to 256 pages with 16K bytes/page) ! Supports BROM disable command to release memory after remote boot ! Supports flash memory read/write (RTL8019AS only) ! 16k byte SRAM built in (RTL8019AS only) ! Use 9346 (64*16-bit EEPROM) to store resource configurations and ID parameters ! Capable of programming blank 9346 on board for manufacturing convenience ! Support 4 diagnostic LED pins with programmable outputs LS003.8 2000.07.31 4 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS 2. General Description The RTL8019AS is a highly integrated Ethernet Controller which offers a simple solution to implement a Plug and Play NE2000 compatible adapter with full-duplex and power down features. With the three level power down control features, the RTL8019AS is made to be an ideal choice of the network device for a GREEN PC system. The full-duplex function enables simultaneously transmission and reception on the twisted-pair link to a full-duplex Ethernet switching hub. This feature not only increases the channel bandwidth from 10 to 20 Mbps but also avoids the performance degrading problem due to the channel contention characteristics of the Ethernet CSMA/CD protocol. The Microsoft's Plug and Play function can relieve the users from pains of taking care the adapter's resource configurations such as IRQ, I/O, and memory address, etc. However, for special applications not to be used as a Plug and Play compatible device, the RTL8019AS also supports the jumper and proprietary jumperless options. To offer a fully plug and play solution, the RTL8019AS provides the auto-detect capability between the integrated 10BaseT transceiver, BNC and AUI interface. Besides, the 10BaseT transceiver can automatically correct the polarity error on its receiving pair. Furthermore, 8 IRQ lines and 16 I/O base address options are provided for grand resource configuration flexibility. The RTL8019AS supports 16k, 32k & 64k byte BROM and fiash memory interface. It also offers the page mode function which can support up to 4M-byte BROM within only 16k-byte system memory space. Besides, the BROM disable command is provided to release the BROM memory space for other system usage (e.g. EMM386, etc.) after the BROM program is loaded. The RTL8019AS is built in with 16K-byte SRAM in a single chip. It is designed not only to provide more friendly functions but also to save the effort of SRAM sourcing and inventory. LS003.8 2000.07.31 5 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS 3. PIN CONFIGURATION 81 BD3 [IOS0] 82 BD2 [IOS1] 83 GND 84 BD1 [IOS2] 85 BD0 [IOS3] 86 GND 87 SD15 89 VDD 90 SD13 91 SD12 92 SD11 93 SD10 94 SD9 95 SD8 96 IOCS16B [SLOT16] 97 INT7 [IRQ15] 98 INT6 [IRQ12] 99 INT5 [IRQ11] 100 INT4 [IRQ10] 88 SD14 50 X1 49 TX+ 48 TX- 47 VDD 46 TPOUT- 45 TPOUT+ 44 GND 43 SD7 42 SD6 39 SD3 38 SD2 37 SD1 36 SD0 34 AEN 33 RSTDRV 32 SMEMWB 31 SMEMRB 41 SD5 40 SD4 2 INT2 [IRQ4] 3 INT1 [IRQ3] 4 INT0 [IRQ2/9] 5 SA0 6 VDD 7 SA1 8 SA2 9 SA3 10 SA4 11 SA5 12 SA6 13 SA7 14 GND 15 SA8 29 IORB 28 GND 27 SA19 26 SA18 25 SA17 24 SA16 23 SA15 22 SA14 21 SA13 20 SA12 30 IOWB 19 SA11 18 SA10 17 VDD 16 SA9 64 AUI 63 LED2 [LED_TX] 62 LED1 [LED_RX] [LED_CRS] 61 LED0 [LED_COL] [LED_LINK] 60 LEDBNC 59 TPIN+ 58 TPIN- 57 VDD 56 RX+ 55 RX- 54 CD+ 53 CD- 52 GND 51 X2 69 BA18 [BS2] 70 VDD 71 BA17 [BS3] 72 BA16 [BS4] 73 BA15 74 BA14 [PL0] 75 BCSB 76 EECS 77 BD7 [PL1][EEDO] 78 BD6 [IRQS0][EEDI] 79 BD5 [IRQS1][EESK] 80 BD4 [IRQS2] RTL8019AS 1 INT3 [IRQ5] 68 BA19 [BS1] 67 BA20 [BS0] 66 BA21 [PNP] 35 IOCHRDY 65 JP LS003.8 2000.07.31 6 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS 4. PIN DESCRIPTIONS 4.1. Power Pins No. Name Type Description 6, 17, 47, 57, 70, 89 VDD P +5V DC power 14, 28, 44, 52, 83, 86 GND P Ground 4.2. ISA Bus Interface Pins No. Name Type Descriptions 34 AEN I Address Enable. This ISA signal must be low for a valid I/O command. 97-100, 1-4 INT7-0 O Interrupt request lines which are mapped to IRQ15, IRQ12, IRQ11, IRQ10, IRQ5, IRQ4, IRQ3, IRQ2/9 respectively. Only one line is selected to reflect the interrupt requests at one time. All other lines are tri-stated. The RTL8019AS also uses these pins as inputs to monitor the actual state of the corresponding interrupt lines on ISA bus. The result is recorded in the INTR register, which may be used by software to detect interrupt conflict. 35 IOCHRDY O This ISA signal is driven low to insert wait cycles to current host read/write command. 96 IOCS16B [SLOT16] O Upon power-on reset, this pin acts as an input named SLOT16 to detect whether a 16-bit or 8-bit slot is in use. To do this, it is connected to a pull-down resistor (about 27KW) externally. At the falling edge of RSTDRV, the RTL8019AS senses this pin's state. If it is sensed high, the adapter is thought to be placed on a 16-bit slot where this pin is connected to the host's IOCS16B pin, which is typically pulled up by a 300W resistor on the mother board. If it is sensed low, the adapter is thought to be placed on an 8-bit slot where this pin is merely pulled low by the 27KW resistor. After having latched the input state, this pin is switched as the IOCS16B signal which is an open-drain output and is driven low during a 16-bit host data transfer. It is decoded from AEN and SA9-0. 29 IORB I Host I/O read command. 30 IOWB I Host I/O write command. 33 RSTDRV I High active hardware reset signal from the ISA bus. Pulses with high level less than 800ns are ignored. 27-18, 16-15, 13-7, 5 SA19-0 I Host address bus. SA10 is added to implement the fully decode of PnP ports, address 279h and A79h. In RTL8019, SA10 is not decoded. In RTL8019AS, SA10 should be 0 for a valid access to PnP ports. 87-88, 90-95, 43-36 SD15-0 I/O Host data bus. 31 SMEMRB I Host memory read command. LS003.8 2000.07.31 7 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS 32 SMEMWB I Host memory write command. This pin is added to decode the write command of a flash memory. 4.3. Memory Interface Pins (including BROM, EEPROM) No. Name Type Description 75 BCSB O BROM chip select. Active low signal, asserted when BROM is read. RTL8019AS drives this pin low when SA19-14 matches the selected BROM memory base address and either of the 2 conditions below meets: (1) SMEMRB is low (2) SMEMWB is low and RTL8019AS's flash memory write function is enabled. 76 EECS O 9346 chip select. Active high signal, asserted when 9346 is read/write. 66-69, 71-74 BA21-14 O BROM address.＊ 77-82, 84-85 BD7-0 I/O BROM data bus. [79] [EESK] O 9346 serial data clock [78] [EEDI] O 9346 serial data input [77] [EEDO] I 9346 serial data output The following pins are defined for jumper options. Their states are latched at the falling edge of RSTDRV, then they are changed to serve as the SRAM bus. Each of them is internally pulled down by a 100KW resistor. Therefore, the input will be low when left open and high when pulled up by a 10K resistor externally. [66] [PNP] I When it is high in jumperless mode (i.e. JP=low), the RTL8019AS is forced into Plug and Play mode regardless of the contents of 9346. The following pins are don't care in jumperless mode (JP=low). [72-71, 69-67] [BS4-0] I Select BROM size and base address. [85-84, 82-81] [IOS3-0] I Select I/O base address. [77, 74] [PL1-0] I Select network medium type. [80-78] [IRQS2-0] I Select one interrupt line among INT7-0. 65 JP I When high, this pin selects jumper mode. When low, it selects jumperless modes (including RT jumperless and Plug and Play). ＊ After RTL8019AS latches all jumper status upon power on reset, these pins always* reflect the value of BPAGE register directly in BROM page mode. In normal mode, BA16-21 are not used and BA14-15 act as: BROM Size BA14 BA15 16K high high 32K SA14 high 64K SA14 SA15 *Note: RTL8019AS doesn't drive BA14-21 until the SMEMRB goes from high to low. 4.4. Medium Interface Pins LS003.8 2000.07.31 8 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS No. Name Type Description 64 AUI I This input is used to detect the usage of an external MAU on the AUI interface. The input should be driven low for embedded BNC and high for external MAU. When the input is high, RTL8019AS sets the AUI bit (bit5) in CONFIG0 and drives LEDBNC low to disable the BNC. If this pin is not used, it should be connected to GND such that RTL8019AS acts like RTL8019. Please refer to section 5.1.2.2. CONFIG0 for more details. 54,53 CD+,CD- I This AUI collision input pair carries the differential collision input signal from the MAU. 56,55 RX+,RX- I This AUI receive input pair carries the differential receive input signal from the MAU. 49,48 TX+,TX- O This AUI transmit output pair contains differential line drivers which send Manchester encoded data to the MAU. These outputs are source followers and require 270 ohm pull- down resistors to GND. 59,58 TPIN+, TPIN- I This TP input pair receives the 10 Mbits/s differential Manchester encoded data from the twisted-pair wire. 45,46 TPOUT+, TPOUT- O This pair carries the differential TP transmit output. The output Manchester encoded signals have been pre-distorted to prevent overcharge on the twisted-pair media and thus reduce jitter. 50 X1 I 20Mhz crystal or external oscillator input. 51 X2 O Crystal feedback output. This output is used in crystal connection only. It must be left open when X1 is driven with an external oscillator. 4.5. LED Output Pins No. Name Type Description 60 LEDBNC O This pin goes high when RTL8019AS's medium type is set to 10Base2 mode or auto-detect mode with link test failure. Otherwise, this pin is low. This pin can be used to control the power of the DC convertor for CX MAU and connected to an LED to indicate the used medium type. 61 LED0 O When LEDS0 bit (in CONFIG3 register of RTL8019AS Page3) is 0, this pin acts as LED_COL. When LEDS0=1, it acts as LED_LINK. 62,63 LED1,LED2 O When LEDS1 bit (in CONFIG3 register of RTL8019AS Page3) is 0, these 2 pins act as LED_RX & LED_TX respectively. When LEDS1=1, these pins act as LED_CRS & MCSB. Please refer to section 6.5 for details of the lightening behavior of all LEDs. 5. Register Descriptions LS003.8 2000.07.31 9 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS The registers in RTL8019AS can be roughly divided into two groups by their address and functions -- one for NE2000, the other for Plug and Play (PnP). 5.1. Group 1: NE2000 Registers This group includes 4 pages of registers which are selected by bit PS0 & PS1 in the CR register. Each page contains 16 registers. Besides those registers compatible with NE2000, the RTL8019AS defines some registers for software configuration and feature enhancement. 5.1.1. Register Table No (Hex) Page0 Page1 Page2 Page3 [R] [W] [R/W] [R] [R] [W] 00 CR CR CR CR CR CR 01 CLDA0 PSTART PAR0 PSTART 9346CR 9346CR 02 CLDA1 PSTOP PAR1 PSTOP BPAGE BPAGE 03 BNRY BNRY PAR2 - CONFIG0 - 04 TSR TPSR PAR3 TPSR CONFIG1 CONFIG1 05 NCR TBCR0 PAR4 - CONFIG2 CONFIG2 06 FIFO TBCR1 PAR5 - CONFIG3 CONFIG3 07 ISR ISR CURR - - TEST 08 CRDA0 RSAR0 MAR0 - CSNSAV - 09 CRDA1 RSAR1 MAR1 - - HLTCLK 0A 8019ID0 RBCR0 MAR2 - - - 0B 8019ID1 RBCR1 MAR3 - INTR - 0C RSR RCR MAR4 RCR - FMWP 0D CNTR0 TCR MAR5 TCR CONFIG4 - 0E CNTR1 DCR MAR6 DCR - - 0F CNTR2 IMR MAR7 IMR - - 10-17 Remote DMA Port 18-1F Reset Port Notes: "-" denotes reserved. Registers with names typed in bold italic format are RTL8019AS defined registers and are not supported in a standard NE2000 adapter. LS003.8 2000.07.31 10 瑞昱半導體股份有限公司 SPECIFICATION RTL8019AS Page 0 (PS1=0, PS0=0) No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00H CR R/W PS1 PS0 RD2 RD1 RD0 TXP STA STP 01H CLDA0 R A7 A6 A5 A4 A3 A2 A1 A0 PSTART W A15 A14 A13 A12 A11 A10 A9 A8 02H CLDA1 R A15 A14 A13 A12 A11 A10 A9 A8 PSTOP W A15 A14 A13 A12 A11 A10 A9 A8 03H BNRY R/W A15 A14 A13 A12 A11 A10 A9 A8 04H TSR R OWC CDH 0 CRS ABT COL - PTX TPSR W A15 A14 A13 A12 A11 A10 A9 A8 05H NCR R 0 0 0 0 NC3 NC2 NC1 NC0 TBCR0 W TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 06H FIFO R D7 D6 D5 D4 D3 D2 D1 D0 TBCR1 W TBC15 TBC14 TBC13 TBC12 TBC11 TBC10 TBC9 TBC8 07H ISR R/W RST RDC CNT OVW TXE RXE PTX PRX 08H CRDA0 R A7 A6 A5 A4 A3 A2 A1 A0 RSAR0 W A7 A6 A5 A4 A3 A2 A1 A0 09H CRDA1 R A15 A14 A13 A12 A11 A10 A9 A8 RSAR1 W A15 A14 A13 A12 A11 A10 A9 A8 0AH 8019ID0 R 0 1 0 1 0 0 0 0 RBCR0 W RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 0BH 8019ID1 R 0 1 1 1 0 0 0 0 RBCR1 W RBC15 RBC14 RBC13 RBC12 RBC11 RBC10 RBC9 RBC8 0CH RSR R DFR DIS PHY MPA 0 FAE CRC PRX RCR W - - MON PRO AM AB AR SEP 0DH CNTR0 R CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 TCR W - - - OFST ATD LB1 LB0 CRC 0EH CNTR1 R CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 DCR W - FT1 FT0 ARM LS LAS BOS WTS 0FH CNTR2 R CNT7 CNT6 CNT5 CNT4 CNT3 CNT2