vhdl程序

2-4译码器 library ieee; use ieee.std_logic_1164.all; entity ym is port(a,b:in std_logic; y:out std_logic_vector(3 downto 0)); end ym; architecture a of ym is signal m:std_logic_vector(1 downto 0); begin m<=b&a; y<="1110" when m="00" else "1101" when m="01" else "1011" when m="10" else "0111" when m="11" else "0000"; end a; 4-1数据选择器 library ieee; use ieee.std_logic_1164.all; entity sjxz is port(a,b,m,n,p,q:in std_logic; y:out std_logic); end sjxz; architecture a of sjxz is signal h:std_logic_vector(1 downto 0); begin h<=a&b; y<=m when h="00" else n when h="01" else p when h="10" else q when h="11" else 'X'; end a; 4-2优先编码器 library ieee; use ieee.std_logic_1164.all; entity bm is port(i:in std_logic_vector(3 downto 0); y:out std_logic_vector(1 downto 0)); end bm; architecture a of bm is begin y<="11"when i(3)='0'else "10"when i(2)='0'else "01"when i(1)='0'else "00"when i(0)='0'else "XX"; end a; 按键去抖动 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity QDD is port(din:in std_logic; clk:in std_logic; y:out std_logic); end QDD; architecture A of QDD is signal m:integer range 0 to 102400; signal n:std_logic; type state_type is(s0,s1,s2,s3,s4,s5); signal state:state_type; begin process(clk) begin if(clk'event and clk='1')then if(m<102400)then m<=m+1; else m<=0; end if; end if; end process; n<='1'when m=0 else '0'; process(n) begin if(n'event and n='0')then case state is when s0=>if din='0'then state<=s1; else state<=s0; end if; when s1=>if din='0'then state<=s2; else state<=s0; end if; when s2=>if din='0'then state<=s3; else state<=s0; end if; when s3=>if din='0'then state<=s4; else state<=s0; end if; when s4=>if din='0'then state<=s5; else state<=s0; end if; when s5=>if din='0'then state<=s5; else state<=s0; end if; when others =>state<=s0; end case; end if; end process; y<='1'when (state=s5 and din='0') else '0'; end A; 七段译码器 library ieee; use ieee.std_logic_1164.all; entity ma is port(a:in std_logic_vector(3downto 0); b:out std_logic_vector(7 downto 0)); end ma; architecture a of ma is begin with a select b<="10000001"when"0000", "11111001"when"0001", "10010010"when"0010", "10000110"when"0011", "11001100"when"0100", "10100100"when"0101", "10100000"when"0110", "10001111"when"0111", "10000000"when"1000", "10000100"when"1001", "10001000"when"1010",------------------(A) "10000000"when"1011",------------------(B) "10110001"when"1100",------------------(C) "10000001"when"1101",------------------(D) "10110000"when"1110",------------------(E) "10111000"when"1111",------------------(F) "XXXXXXXX"when others; end a; 五人 表 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf 决器 library ieee; use ieee.std_logic_1164.all; entity ma is port(a:in std_logic_vector(3downto 0); b:out std_logic_vector(7 downto 0)); end ma; architecture a of ma is begin with a select b<="10000001"when"0000", "11111001"when"0001", "10010010"when"0010", "10000110"when"0011", "11001100"when"0100", "10100100"when"0101", "10100000"when"0110", "10001111"when"0111", "10000000"when"1000", "10000100"when"1001", "10001000"when"1010",------------------(A) "10000000"when"1011",------------------(B) "10110001"when"1100",------------------(C) "10000001"when"1101",------------------(D) "10110000"when"1110",------------------(E) "10111000"when"1111",------------------(F) "XXXXXXXX"when others; end a;