cpci_spec_v2_0

1 PICMG 2.0 R2.0 CompactPCI CompactPCI TM Specification Short Form February 17th, 1997 NOTE: This short form specification reflects the content of the DRAFT version of the Version 2.0 of the CompactPCI specification. It is for information only and will be updated when the final, released specification is available. ãCopyright 1995, 1996 PCI Industrial Computers Manufacturers Group (PICMG). PICMG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors or omissions that may appear in this document, nor is PICMG responsible for any incidental or consequential damages resulting from the use of any data contained in this document, nor does PICMG assume any responsibility to update or correct any information in this publication -2- DRAFT VERSION ONLY Overview This short form specification is a subset of the full CompactPCI specification, version 1.0 as approved by the PICMG. This document is meant as a guide for those considering CompactPCI, but is not a design document. Anyone wishing to design a system board, adapter board, or backplane for CompactPCI should obtain the full specification from PICMG. You can also download a PDF or HTML version of this short form specification from the PICMG Web Site at www.picmg.com. CompactPCI is an adaptation of the Peripheral Component Interconnect (PCI) Specification for industrial and/or embedded applications requiring a more robust mechanical form factor than desktop PCI. CompactPCI uses industry standard mechanical components and high performance connector technologies to provide an optimized system intended for rugged applications. CompactPCI provides a system that is electrically compatible with the PCI Specification, allowing low cost PCI components to be utilized in a mechanical form factor suited for rugged environments. CompactPCI is an open specification supported by the PICMG (PCI Industrial Computer Manufacturers Group), which is a consortium of companies involved in utilizing PCI for embedded applications. PICMG controls this specification. Form Factor The form factor defined for CompactPCI boards is based upon the Eurocard industry standard. Both 3U (100 mm by 160 mm) and 6U (233.35 mm by 160 mm) board sizes are defined. See Figure 1 opposite. The 3U form factor is the minimum for CompactPCI as is accommodates the full 64-Bit CompactPCI bus. The 6U extensions are defined for boards where the extra board area or connection space is needed. Rear connectors are numbered J1-J5 starting at the bottom connector. The Specification defines the locations for all these connectors but only the signal-pin assignments for the CompactPCI bus portion J1 and J2. Use of the remaining connectors (J3,J4,J5) are the subject of additional specification efforts, or can be user defined for specific applications. Front Panels CompactPCI boards provide a front plate interface that is consistent with Eurocard packaging and are compliant with IEEE 1101.1 or IEEE P1101.10 (EMC panels). Ejector/injector handles that are compliant with IEEE P1101.10 are also be used. One ejector handle is used for 3U boards. 6U boards use two handles. Filler panels do not require handles. Systems A CompactPCI system is composed of one or more CompactPCI bus segments. Each segment is composed of up to eight CompactPCI board locations (at 33 MHz) with 20.32 mm (0.8 inch) board center-to-center spacing. Each CompactPCI segment consists of one System Slot, and up to seven Peripheral Slots. The System Slot board provides arbitration, clock distribution, and reset functions for all boards on the segment. The System Slot is responsible for performing system initialization by managing each local board’s IDSEL signal. Physically, the System Slot may be located at any position in the backplane. For simplicity, this specification assumes one CompactPCI bus segment in which the System Slot is located on the left when the backplane is viewed from the front side. The Peripheral Slots may contain simple boards, intelligent slaves, or PCI bus masters. -3- DRAFT VERSION ONLY Figure 1. CompactPCI form factors Backplanes The default CompactPCI backplane is illustrated in Figure 2. As viewed from the front of the system chassis. Other topologies besides the linear arrangement illustrated are allowed by CompactPCI. However, this specification and all backplane simulations have assumed a linear topology using 20.32 mm (.8 inch) board center- to-center spacing. Any other topology must be simulated or otherwise verified to ensure compliance to the PCI specification. Slot Spacing Slot spacing SHALL be 20.32 mm (.8 inch). Bus segments SHALL not have more than eight slots without one or more PCI bridges. Slot Designation Physical backplane slots SHALL be designated 1, 2, 3, through N, where N is the number of slots. For example, an eight-slot backplane would des- ignate the backplane slots as 1 through 8 with the compatibility glyphs. Slot numbering SHALL start at the top left corner as viewed from the front. Logical slot numbers are used in the nomenclature to define the physical outline of a connector on a bus segment. Please see Chapter 3 for signal routing requirements. Each slot MAY be implemented with one or more connectors. Backplane connectors SHALL be designated as P1 through P5 corresponding in location to the board’s connectors. Any given connector SHALL be referenced by first specifying the logical slot number (1...8) followed by a hyphen and then the individual connector (P1...P5). For example, in a 32-bit 3U system the rear panel I/O connector in logical slot 5 would be designated by 5-P2. In a 64-bit 6U system the rear panel I/O connector in logical slot 1 would be designated by 1-P3. Bus Segments Bus segments MAY accommodate 64-bit operation or SHALL provide individual pull-up resistors at each board slot for the REQ64# and ACK64# signals. Refer to the PCI specification for details. The System Slot SHALL use both J1 and J2 to allow the arbitration and clock signals to be connected to the backplane from a System Slot board. Connectors require pin staging to accom- modate hot swap operation. CompactPCI bus segments SHALL bus all signals in all slots within the segment except the slot specific signals: CLK, REQ# and GNT#. Each logical slot also has a unique IDSEL signal con- nected to one of the upper ADxx signals for con- figuration (plug and play) decoding. Backplanes implementing the modular power supply connector SHALL provide connection for the power supply signals DEG#(P2:C16) and FAL# (P2:C15) at the System Slot that may be provided by the power supply. -4- DRAFT VERSION ONLY Figure 2. CompactPCI Backplane. Connector The CompactPCI connector is a shielded, 2 mm- pitch, 5-row connector as defined by IEC 917 and IEC 1076-4-101. Features of this connector include: · Pin and socket interconnect mechanism · Multi-vendor support · Coding Mechanism providing positive keying · Staggered make-break pin populations for optional hot swap capability · Rear pin option for through-the-backplane I/O applications · High density PCI capability · Shield for EMI/RFI protection · Expandability for end user applications CompactPCI is defined as a 5 row by 47 position array of pins divided logically into two groups corresponding to the physical connector implementation. 32-bit PCI and connector keying is implemented on one connector (J1). An additional connector (J2) is defined for 64-bit transfers or for rear panel I/O. The CompactPCI connector utilizes guide lugs located on the board connector to ensure correct polarized mating. Proper mating is further enhanced by the use of coding keys for 3.3V or 5V operation, with or without Hot-Swap capability, to prevent incorrect installation of boards. J1 (32-Bit PCI Signals) CompactPCI board connector J1 is used for the 32-bit PCI signals. 32-bit boards SHALL always use this connector. Use of the J2 connector is optional. J2 Connector J2 MAY be used for 64-bit PCI transfers or for rear-panel I/O. The keying of this connector function is provided by the IEEE 1101.10 front panel key. J2 SHALL be used on System Slot boards to provide arbitration and clock signals for peripheral boards. J2 SHALL be used if 64-bit PCI operation or rear panel I/O is supported. Bussed Reserved Pins The BRSVPxxx signals SHALL be bused between connectors and are reserved for future definition. Non-Bused Reserved Pins The RSV signals are non-bused signals that SHALL be reserved for future definition. Power Pins All CompactPCI connectors provide pins for +5V, +3.3V, +12V and -12V operating power. Additional power pins labeled +V(I/O) provide power for Universal boards utilizing I/O buffers driving backplane signals that MAY operate from +5V or +3.3V. On these boards, the PCI components I/O buffers shall be powered from V(I/O), not from +5V or +3.3V power pins. Backplane pins labeled V(I/O) are connected to +5V on 5V keyed systems and +3.3V on 3.3 V keyed systems. Alternatively, a separate V(I/O) power plane may be provided to supply 5V or 3.3V power. 5V/3.3V PCI Keying CompactPCI implements a keying mechanism to differentiate 5V or 3.3V signaling operation. The keying mechanism is designed to prevent a board built with one buffer technology (5V or 3.3V) from being inserted into a system designed for the other buffer technology (3.3V or 5V, respectively). Universal boards MAY operate in either +5V or +3.3V systems and are not keyed. Positions 12-14 of the CompactPCI connector are used for the keying mechanism. Backplanes SHALL be = PERIPHERAL SLOT 1 3 edcz a b f 1 1 2-P1 2 25 4 5 = SYSTEM SLOT 22 2-P2 1 7-P1 76 cz a b d e f 8 1 25 7-P2 22 -5- DRAFT VERSION ONLY configured as either 5V or 3.3V and SHALL provide the appropriate key. It is not possible to have a “universal” backplane. Refer to the “CompactPCI Keying Specification” for additional details on keying. Hot Swap Capability The CompactPCI Connector accommodates the mechanical prerequisites for hot swap by staging the pin sequence within the backplane connector. It is anticipated that adapters designated as "hot swap" will provide a means for insertion and withdrawal while bus activity continues. Additional work is ongoing in a PICMG committee to thoroughly define all aspects of a “hot swap” specification. That work will be incorporated into a supplementary specification. Adapter Cards CompactPCI board design SHALL adhere to the design requirements for standard desktop PCI boards as outlined in the PCI Specification. This section documents additional requirements and/or restrictions as needed. The design rules apply to PCI bus operation up to 33 MHz. Physical Outline CompactPCI defines two board sizes, 3U and 6U. 3U Boards 3U boards are 100 mm by 160 mm. The PCB is 1.6 mm thick. A 2 mm (IEC-1076-4-101) connector is used for interfacing to the CompactPCI bus segment.. 32-bit PCI is implemented on J1. J2 MAY be used for 64-bit PCI signaling, or rear panel I/O, or System Slot functions. Note that row Z is not present on system or peripheral boards. Refer to IEC-1076-4-101 docu- mentation for details. 6U Boards 6U boards are 233.35 mm by 160 mm. 32-bit PCI is implemented on J1. J2 is used for 64-bit PCI signaling, or rear panel I/O, or System Slot functions. J3, J4 and J5 MAY be used for rear panel I/O. Rear panel I/O MAY be defined by the user and/or utilize PICMG specifications. Contact PICMG for copies of these specifications. Note that row Z is not present on system or peripheral boards. Refer to IEC-1076-4-101 docu- mentation for details. Front entry of CompactPCI boards into the subrack is defined by IEEE 1101.1 and IEEE P1101.10. Rear entry of boards (real panel I/O) into the subrack is defined by IEEE P1101.11. Physical board locations within the subrack SHOULD be indicated by a numbering scheme visible from the front (and rear, if back panel I/O is utilized) of the subrack. CompactPCI Signal Additions CompactPCI defines some additional signals beyond the PCI specification that may be applicable to board designs. These signals are: Push Button Reset (PRST#), Power Supply Status (DEG#, FAL#), System Slot Identification (SYSEN#), System Enumeration (ENUM#) and Legacy IDE Interrupt Support. Signal Termination All bused PCI signals SHALL include a 10W stub termination resistor located on the board at the CompactPCI connector interface. The signals that SHALL be terminated are: AD0-AD31, C/BE0#- C/BE3#, PAR, FRAME#, IRDY#, TRDY#, STOP#, LOCK#, IDSEL, DEVSEL#, PERR#, SERR#, and RST#. If used by a board, the following signals SHALL also be terminated: INTA#, INTB#, INTC#, INTD#, SB0# , SDONE, AD32-AD63, C/BE4#- C/BE7#, REQ64#, ACK64#, and PAR64. The following signals do not require a stub termination resistor: CLK, REQ#, GNT#, TDI, TDO, TCK, TMS, and TRST#. The stub termination minimizes the effect of the stub on each board to the PCI backplane. The resistor SHALL be placed within 15.2 mm (0.6 -6- DRAFT VERSION ONLY inches) of the signal’s connector pin. This length SHALL be included in the overall length of trace that is allowed for the signal. Peripheral boards that drive REQ# SHOULD provide a series terminating resistor at the driver pin (not a stub termination resistor at the connector). On System Slot boards, a series resistor (sized according to the output characteristics of the clock buffer) SHALL be located at the driver for the CLK signal provided to each slot. Each System Slot board’s GNT# signal SHALL also be series terminated at the driver with a resistor as required by the driving buffer output characteristics. Peripheral Board Signal Stub Length Signal length for 32-bit signals (J1) SHALL be less than or equal to 38.1 mm (1.5 inches). Signal length for 64-bit signals (J2) SHALL be less than or equal to 50.8 mm (2.0 inches). These lengths are measured from the connector pin through the stub or series termination resistor to the PCI device pin. These lengths are consistent with the PCI Specification requirements but also include the resistor in the total trace length. A maximum of one PCI load SHALL be allowed on any PCI signal from the connector on any given board. Peripheral boards with more than one load are not compliant with the CompactPCI Specification and SHALL not be declared Com- pactPCI compatible. System Board Loading The System Slot MAY have two PCI loads on each signal on a PCI backplane segment to accommodate practical implementations of PCI based CPU designs. The CompactPCI system modeling was performed with this requirement. The second load SHALL not add more than 25.4 mm (1 inch) to the signal length for any PCI signal in addition to the 38.1 mm (1.5 inches) allowed for 32-bit PCI signals, or 50.8 mm (2.0 inches) allowed for 64-bit signals. Only one stub termi- nation resistor is required per PCI signal on System Slot designs and this SHALL be placed within 15.2 mm (0.6 inches) of the connector pin. Peripheral Board PCI Clock Signal Length On peripheral boards, the PCI clock signal length SHALL be 63.5 mm ± 2.54 mm (2.5 inches ±0.1 inches), and is allowed to drive one load only on the board. Pull-up Location Pull-up resistors required by the PCI specification SHALL be located on the System Slot board. The pull-up resistor, for those signals requiring a pull- up, SHALL be placed on the in-board side of the stub termination resistor. The System Slot board SHALL provide a pull-up resistor for the REQ64# and ACK64# signals even if the System Slot board does not use these signals, as in the case of a 32-bit System Slot board. This requirement accommodates 64-bit boards. They SHALL see the signal REQ64# as false during reset to properly connect to the 32-bit PCI bus. The pull-up resistor also prevents floating REQ64# or ACK64# signals on 64-bit boards. Connector Shield Requirements The CompactPCI connector SHALL load a shield at row F on the board. This shield covers the top of the IEC-1076 connector and helps to provide a low impedance return path for ground between the board and the CompactPCI backplane. This is required for CompactPCI compliance and was used in the simulation modeling of the CompactPCI environment. Boards that do not use this shield are not compliant and are not guaranteed to work in all CompactPCI system topologies. The lower shield option that is provided for in the IEC-1076 connector is not required for CompactPCI boards and SHALL not be loaded if it protrudes into the inter-board separation plane. Front Panel I/O Connector Recommendations CompactPCI boards SHOULD utilize metalized shell connectors for EMI/RFI protection. The shell SHOULD be electrically connected to the I/O plate through a low impedance path in accordance with IEEE P1101.10. The I/O plate is assumed to be connected to earth ground and isolated from logic ground. -7- DRAFT VERSION ONLY CompactPCI boards SHALL not connect earth ground (on front panel) through a low impedance path to logic ground used on-board. For applications requiring coupling between earth and logic ground, boards MAY implement a coupling method. Because coupling methods are application dependent, specification for coupling circuits are beyond the scope of the specification. Backplane Design Rules CompactPCI defines a backplane environment that MAY have up to eight boards. One slot, the System Slot, provides the clocking, arbitration, configuration, and interrupt processing for the other 7 slots. Fewer slots may be provided in a CompactPCI backplane, but the following sections assume that a maximum configuration is employed. Backplanes SHALL provide separate power planes for 3.3V, 5V, and ground. If V(I/O) is configurable as 3.3V or 5V, then a separate power plane SHALL be dedicated for V(I/O). Clock Routing Requirements A 2 ns maximum skew SHALL be maintained between any two PCI components (not connector to connector) per PCI specification requirements. Adherence to backplane and board rules contained in this specification help meet this requirement. The System Slot board drives five buffered clocks via CLK0-CLK4. Board slots receive their specific clock using the CLK pin (J1:D6). Signaling Environment Each CompactPCI backplane provides for either a 5V or 3.3V signaling environment. PCI allows for two types of buffer interfaces for inter-board connection. 5V signaling will generally be used for early systems. A gradual shift to 3.3V will occur as the semiconductor industry shifts to the lower power interface for speed and power dissipation reasons. The V(I/O) power pins on the connector are used to power the buffers on the peripheral boards, allowing a card to be designed to work in either interface. CompactPCI allows for this dual interface scheme by providing a unique backplane connector coding plug for either system. The CompactPCI backplane may be either a fixed signaling environment backplane (e.g., 5V only) or may be configurable. In any case, when configured for 5V operation, the 5V coding plug (Brilliant Blue) SHALL be used, and when configured for 3.3V operation, the 3.3V coding plug (Cadmium Yellow) SHALL be installed in the backplane connector. IDSEL Assignment The PCI signal IDSEL is used to provide unique access to each logical slot for configuration purposes. By connecting one of the address lines AD31 through AD25 to each board’s IDSEL pin (J1:B9), a unique address for each board is provided during configuration cycles. REQ#/GNT# Assignment The System Slot interfaces to seven pairs of REQx#/GNTx# pins called REQ0#-REQ6# and GNT0#-GNT6#. Each board slot interfaces to one pair of REQx#/GNTx# signals using pins called REQ# and GNT#. The System Slot on any given CompactPCI backplane segment SHALL support the full complement of REQ#/GNT# signals. Table 1. Power Specifications. If a System Slot board can not support the full complement of REQ#/GNT# signals, provisi