DE2-115_MB

5 5 4 4 3 3 2 2 1 1 D D C C B B A A 03 DISPLAY 07 ~ 08 SDRAM , SRAM , FLASH , SD CARD WM8731 Cyclone IV EP4CE115 BANK1..BANK8 , POWER , CONFIG 10 POWER 19 01 TOP 01 ~ 03 15 ~ 16 09 ~ 14 PAGE 21 ~ 25 04 ~ 06 SCHEMATIC ALTERA Cyclone IV Development & Education Board (DE2-115) 17 ~ 18 CONTENT Cover Page, Placement,TOP 05 ETHERNET CLOCK, IrDA, PS2 , RS232 , BUTTON , SWITCH , HSMC, EEPROM 09 FPGA LCD , LED , 7SEGMENT 08 USB DEVICE 20 02 MEMORY 88E1111 07 AUDIO ADV7123, ADV718006 VIDEO 04 IN/OUT ISP1362 POWER 1.2V, 1.8V, 2.5V, 3.3V, 5V 26 ~ 27 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. COVER PAGE B DE2-115 Main Board B 1 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. COVER PAGE B DE2-115 Main Board B 1 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. COVER PAGE B DE2-115 Main Board B 1 27Friday, September 24, 2010 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. PLACEMENT B DE2-115 Main Board B 2 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. PLACEMENT B DE2-115 Main Board B 2 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. PLACEMENT B DE2-115 Main Board B 2 27Friday, September 24, 2010 5 5 4 4 3 3 2 2 1 1 D D C C B B A A DRAM_DQ[31..0] DRAM_ADDR[12..0] DRAM_DQM[3..0] SRAM_DQ[15..0] SRAM_ADDR[19..0] FL_DQ[7..0] FL_ADDR[22..0] SD_DAT[3..0] LCD_DATA[7..0] HEX0[6..0] HEX1[6..0] HEX2[6..0] HEX3[6..0] HEX4[6..0] HEX5[6..0] HEX6[6..0] HEX7[6..0] LEDG[8..0] LEDR[17..0] SW[17..0] KEY[3..0] GPIO[35..0] HSMC_D[3..0] HSMC_TX_D_P[16..0] HSMC_TX_D_N[16..0] HSMC_RX_D_P[16..0] HSMC_RX_D_N[16..0] VGA_B[7..0] VGA_G[7..0] VGA_R[7..0] ENET1_RX_DATA[3..0] ENET0_TX_DATA[3..0] ENET0_RX_DATA[3..0]DRAM_DQ[31..0] SRAM_DQ[15..0] FL_DQ[7..0] SD_DAT[3..0] LCD_DATA[7..0] GPIO[35..0] SW[17..0] KEY[3..0] HSMC_TX_D_P[16..0] HSMC_TX_D_N[16..0] HSMC_RX_D_P[16..0] HSMC_RX_D_N[16..0] DRAM_ADDR[12..0] SRAM_ADDR[19..0] FL_ADDR[22..0] LEDR[17..0] LEDG[8..0] HEX0[6..0] HEX1[6..0] HEX2[6..0] HEX3[6..0] HEX4[6..0] HEX5[6..0] HEX6[6..0] HEX7[6..0] DRAM_BA1 DRAM_CAS_N DRAM_RAS_N DRAM_CKE DRAM_WE_N DRAM_CS_N DRAM_CLK SRAM_UB_N SRAM_LB_N SRAM_WE_N SRAM_OE_N SRAM_CE_N FL_WP_N FL_CE_N FL_OE_N FL_WE_N FL_RST_N SD_CLK SD_CMD FL_RY LCD_ON LCD_BLON LCD_EN LCD_RS LCD_RW SMA_CLKOUT CLOCK_50 CLOCK2_50 CLOCK3_50 SMA_CLKIN PS2_CLK2 PS2_DAT2 PS2_CLK PS2_DAT UART_RXD UART_RTS IRDA_RXD EEP_I2C_SDAT JTAG_TDO I2C_SDAT I2C_SCLK HSMC_CLKOUT0 HSMC_CLKIN_P1 HSMC_CLKIN_N1 HSMC_CLKIN_P2 HSMC_CLKIN_N2 HSMC_CLKIN0 UART_TXD UART_CTS EEP_I2C_SCLK FPGA_TDO JTAG_TMS JTAG_TCK HSMC_CLKOUT_P1 HSMC_CLKOUT_N1 DRAM_CAS_N DRAM_RAS_N DRAM_BA0 DRAM_BA1 DRAM_CKE DRAM_WE_N DRAM_CS_N DRAM_CLK SRAM_CE_N SRAM_OE_N SRAM_WE_N SRAM_UB_N SRAM_LB_N FL_RST_N FL_WE_N FL_CE_N FL_WP_N FL_OE_N FL_RY SD_CLK SD_WP_N SD_CMD LCD_ON LCD_EN LCD_RW LCD_RS LCD_BLON CLOCK_50 CLOCK2_50 CLOCK3_50 SMA_CLKIN SMA_CLKOUT IRDA_RXD UART_TXD UART_RXD UART_RTS UART_CTS PS2_CLK PS2_DAT PS2_CLK2 PS2_DAT2 HSMC_CLKIN_P1 HSMC_CLKIN_N1 HSMC_CLKIN_P2 HSMC_CLKIN_N2 HSMC_CLKOUT_P1 HSMC_CLKOUT_N1 HSMC_CLKOUT_P2 HSMC_CLKOUT_N2 HSMC_CLKIN0 HSMC_CLKOUT0 ENET0_RX_ER ENET0_RX_COL ENET0_RX_CRS ENET0_RX_DV ENET0_RX_CLK ENET0_TX_CLK ENET0_GTX_CLK ENET0_TX_EN ENET0_TX_ER ENET0_INT_N ENET0_RST_N ENET0_MDC ENET0_MDIO ENET1_RX_ER ENET1_RX_COL ENET1_RX_CRS ENET1_RX_DV ENET1_RX_CLK ENET1_TX_CLK ENET1_GTX_CLK ENET1_TX_EN ENET1_TX_ER ENET1_INT_N ENET1_RST_N ENET1_MDC ENET1_MDIO VGA_CLK AUD_XCK AUD_BCLK AUD_ADCDAT AUD_ADCLRCK AUD_DACDAT AUD_DACLRCK JTAG_TMS JTAG_TCK JTAG_TDI FPGA_TDO NSTATUS CONF_DONE NCONFIG NCE DCLK DATA0 NCSO ASDO EEP_I2C_SCLK EEP_I2C_SDAT ENET0_TX_DATA[3..0] ENET0_RX_DATA[3..0] ENET1_TX_DATA[3..0] ENET1_RX_DATA[3..0] VGA_R[7..0] VGA_G[7..0] VGA_B[7..0] ENET0_RX_DV ENET0_RX_ER ENET0_RX_CRS ENET0_RX_COL ENET0_RX_CLK ENET0_TX_CLK ENET0_INT_N ENET0_MDIO ENET0_GTX_CLK ENET0_TX_EN ENET0_TX_ER ENET0_RST_N ENET0_MDC ENET1_MDC ENET1_GTX_CLK ENET1_TX_EN ENET1_TX_ER ENET1_RST_N ENET1_RX_DV ENET1_RX_ER ENET1_RX_CRS ENET1_RX_COL ENET1_RX_CLK ENET1_TX_CLK ENET1_INT_N ENET1_MDIO VGA_SYNC_N VGA_CLK VGA_VS VGA_HS AUD_ADCDAT AUD_BCLK AUD_DACLRCK AUD_ADCLRCK AUD_DACDAT AUD_XCK I2C_SDAT I2C_SCLK DRAM_DQM[3..0] DRAM_BA0 SD_WP_N HSMC_D[3..0] HSMC_CLKOUT_P2 HSMC_CLKOUT_N2 VGA_BLANK_N TD_RESET_N TD_DATA[7..0] TD_VS TD_HS TD_CLK27 I2C_SCLK I2C_SDAT ENET1_TX_DATA[3..0] EX_IO[6..0] EX_IO[6..0] VGA_BLANK_N VGA_SYNC_N VGA_VS VGA_HS OTG_DATA[15..0] OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_FSPEED OTG_LSPEED OTG_DACK_N1 OTG_DACK_N0 OTG_ADDR1 OTG_ADDR0 OTG_RD_N OTG_WR_N OTG_CS_N OTG_RST_N OTG_DATA[15..0] OTG_FSPEED OTG_LSPEED OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_ADDR1 OTG_ADDR0 OTG_CS_N OTG_WR_N OTG_RD_N OTG_DACK_N1 OTG_DACK_N0 OTG_RST_N USB_12MHz TD_RESET_N TD_CLK27 TD_HS TD_VS TD_DATA[7..0] I2C_SDAT I2C_SCLK ENET1_LINK100 ENETCLK_25 ENET0_LINK100 ENET0_LINK100 ENET1_LINK100 ENETCLK_25 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. TOP B DE2-115 Main Board C 3 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. TOP B DE2-115 Main Board C 3 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. TOP B DE2-115 Main Board C 3 27Friday, September 24, 2010 PAGE 2008 USB DEVICE OTG_INT0 OTG_LSPEED OTG_DATA[15..0] OTG_INT1 OTG_FSPEED OTG_DREQ0 OTG_DREQ1 USB_12MHz OTG_CS_N OTG_ADDR0 OTG_ADDR1 OTG_RST_N OTG_DACK_N0 OTG_DACK_N1 OTG_RD_N OTG_WR_N PAGE 17-1806 VIDEO VGA_HS VGA_VS VGA_CLK TD_HS TD_VS TD_RESET_n TD_CLK27 TD_DATA[7..0] VGA_G[7..0] VGA_R[7..0] VGA_B[7..0] VGA_BLANK_N VGA_SYNC_N I2C_SDAT I2C_SCLK PAGE 15-1605 ETHERNET ENET0_GTX_CLK ENET1_TX_ER ENET0_RX_CLK ENET1_MDIO ENET0_MDIO ENET0_MDC ENET1_TX_DATA[3..0] ENET0_RX_DV ENET0_RX_CRS ENET1_RX_DV ENET1_LINK100 ENET1_MDC ENET0_TX_EN ENET1_TX_EN ENET1_GTX_CLK ENET0_TX_DATA[3..0] ENET0_TX_ER ENET0_RX_DATA[3..0] ENET1_TX_CLK ENET1_RX_COL ENETCLK_25 ENET1_RX_CLK ENET0_LINK100 ENET0_INT_N ENET1_INT_N ENET1_RX_CRS ENET1_RX_DATA[3..0] ENET0_RX_ER ENET1_RX_ER ENET0_TX_CLK ENET0_RX_COLENET0_RST_N ENET1_RST_N PAGE 9 - 1404 IN/OUT HSMC_TDI HSMC_CLKIN0 HSMC_CLKOUT0 HSMC_SCL HSMC_SDAHSMC_TMS HSMC_TCK UART_TXD UART_RXD JTAG_TDO SW[17..0] KEY[3..0] UART_CTS SMA_CLKOUT UART_RTS SMA_CLKIN IRDA_RXD HSMC_D[3..0] EX_IO[6..0] CLOCK_50 CLOCK3_50 CLOCK2_50 HSMC_CLKIN_P1 HSMC_CLKIN_P2 HSMC_CLKIN_N1 HSMC_CLKIN_N2 HSMC_CLKOUT_P1 HSMC_CLKOUT_P2 HSMC_CLKOUT_N1 HSMC_CLKOUT_N2 HSMC_TX_D_P[16..0] HSMC_TX_D_N[16..0] HSMC_RX_D_P[16..0] HSMC_RX_D_N[16..0] GPIO[35..0] PS2_DAT2 PS2_CLK PS2_CLK2 PS2_DAT EEP_I2C_SCLK EEP_I2C_SDAT PAGE 7-803 DISPLAY LCD_BLON LCD_ON LCD_EN LCD_RS LCD_RW LEDG[8..0] LEDR[17..0] LCD_DATA[7..0] HEX1[6..0] HEX2[6..0] HEX4[6..0] HEX3[6..0] HEX5[6..0] HEX7[6..0] HEX6[6..0] HEX0[6..0] PAGE 1907 AUDIO AUD_BCLK AUD_DACLRCK AUD_ADCLRCK AUD_DACDAT AUD_XCK AUD_ADCDAT I2C_SDAT I2C_SCLK PAGE 26 -2711 POWER PAGE 21-2510 EP4CE115 DRAM_BA0 DRAM_BA1 DRAM_CLK DRAM_CKE LCD_ON LCD_BLON LCD_RS NCSO DATA0 DRAM_DQ[31..0] LCD_DATA[7..0] SRAM_DQ[15..0] NSTATUS NCONFIG LCD_RW DRAM_DQM[3..0] IRDA_RXD SRAM_ADDR[19..0] SD_CLK SD_DAT[3..0] CONF_DONE DRAM_ADDR[12..0] LCD_EN ASDO NCE DCLK SD_CMD SW[17..0] LEDG[8..0] HSMC_CLKOUT0 UART_RXD UART_RTS UART_TXD HSMC_D[3..0] UART_CTS SMA_CLKOUT LEDR[17..0] SMA_CLKIN HSMC_CLKIN0 KEY[3..0] AUD_DACDAT AUD_ADCLRCK AUD_ADCDAT AUD_BCLK TDO AUD_DACLRCK AUD_XCK VGA_CLK VGA_HS VGA_VS TDI TMS TCK EX_IO[6..0] OTG_DATA[15..0] OTG_LSPEED TD_HS OTG_INT0 OTG_INT1 TD_VS OTG_FSPEED TD_CLK27 OTG_DREQ0 OTG_DREQ1 TD_DATA[7..0] VGA_G[7..0] VGA_R[7..0] VGA_B[7..0] HEX1[6..0] HEX2[6..0] HEX4[6..0] HEX3[6..0] HEX5[6..0] HEX6[6..0] HEX7[6..0] HEX0[6..0] CLOCK_50 CLOCK3_50 CLOCK2_50 HSMC_CLKIN_P1 HSMC_CLKIN_P2 HSMC_CLKIN_N1 HSMC_CLKIN_N2 HSMC_CLKOUT_P1 HSMC_CLKOUT_P2 HSMC_CLKOUT_N1 HSMC_CLKOUT_N2 HSMC_TX_D_P[16..0] HSMC_TX_D_N[16..0] HSMC_RX_D_P[16..0] HSMC_RX_D_N[16..0] GPIO[35..0] VGA_BLANK_N VGA_SYNC_N I2C_SDAT I2C_SCLK PS2_DAT2 PS2_CLK PS2_CLK2 PS2_DAT ENET0_GTX_CLK ENET1_TX_ER ENET0_RX_CLK ENET1_MDIO ENET0_RX_DV ENET0_MDC ENET0_MDIO ENET1_RX_DV ENET0_RX_CRS ENET1_LINK100 ENET1_TX_CLK ENET1_RX_COL ENET0_RX_DATA[3..0] ENETCLK_25 ENET1_RX_CLK ENET0_INT_N ENET0_LINK100 ENET1_TX_DATA[3..0] ENET1_MDC ENET0_TX_EN ENET1_TX_EN ENET1_GTX_CLK ENET0_TX_ER ENET0_TX_DATA[3..0] ENET1_INT_N ENET1_RX_CRS ENET1_RX_DATA[3..0] ENET0_RX_ER ENET1_RX_ER ENET0_TX_CLK ENET0_RX_COL TD_RESET_N OTG_CS_N OTG_ADDR0 OTG_ADDR1 SRAM_UB_N SRAM_WE_N SRAM_CE_N SRAM_OE_N SRAM_LB_N FL_CE_N FL_ADDR[22..0] FL_OE_N FL_DQ[7..0] FL_WP_N FL_RY FL_WE_N EEP_I2C_SCLK EEP_I2C_SDAT SD_WP_N OTG_RST_N OTG_DACK_N0 OTG_DACK_N1 DRAM_CAS_N DRAM_WE_N DRAM_CS_N DRAM_RAS_N OTG_RD_N OTG_WR_N ENET0_RST_N ENET1_RST_N FL_RST_N PAGE 4-602 MEMORY SD_CMDSD_CLK DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_DQM[3..0] SD_DAT[3..0] DRAM_DQ[31..0] SRAM_DQ[15..0] SRAM_ADDR[19..0] DRAM_ADDR[12..0] SRAM_UB_N SRAM_WE_N SRAM_CE_N SRAM_LB_N SRAM_OE_N FL_CE_N FL_ADDR[22..0] FL_OE_N FL_DQ[7..0]FL_WP_N FL_WE_N FL_RY SD_WP_N DRAM_CAS_N DRAM_CS_N DRAM_WE_N DRAM_RAS_N FL_RST_N 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SDRAM0 SDRAM1 DRAM_DQM2 DRAM_DQM3 DRAM_CKE DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_WE_N DRAM_ADDR3 DRAM_ADDR0 DRAM_ADDR2 DRAM_ADDR1 DRAM_ADDR10 DRAM_DQM0 DRAM_DQ5 DRAM_DQ0 DRAM_DQ7 DRAM_DQ6 DRAM_DQ3 DRAM_DQ2 DRAM_DQ4 DRAM_DQ1 DRAM_ADDR3 DRAM_ADDR0 DRAM_ADDR2 DRAM_ADDR1 DRAM_ADDR10 DRAM_DQ21 DRAM_DQ16 DRAM_DQ23 DRAM_DQ22 DRAM_DQ19 DRAM_DQ18 DRAM_DQ20 DRAM_DQ17 DRAM_ADDR12 DRAM_ADDR5 DRAM_ADDR7 DRAM_ADDR6 DRAM_ADDR8 DRAM_ADDR11 DRAM_ADDR4 DRAM_ADDR9 DRAM_DQ24 DRAM_DQ31 DRAM_DQ27 DRAM_DQ25 DRAM_DQ26 DRAM_DQ29 DRAM_DQ30 DRAM_DQ28DRAM_ADDR12 DRAM_ADDR5 DRAM_ADDR7 DRAM_ADDR6 DRAM_ADDR8 DRAM_ADDR11 DRAM_ADDR4 DRAM_ADDR9 DRAM_DQM1 DRAM_DQ8 DRAM_DQ15 DRAM_DQ11 DRAM_DQ9 DRAM_DQ10 DRAM_DQ13 DRAM_DQ14 DRAM_DQ12 DRAM_CLK DRAM_CKE DRAM_WE_n DRAM_CAS_n DRAM_RAS_n DRAM_CS_n DRAM_BA0 DRAM_BA1 DRAM_DQ[31..0] DRAM_ADDR[12..0] DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_WE_N DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_DQM[3..0] DR_VCC3P3 DR_VCC3P3 DR_VCC3P3 DR_VCC3P3 DR_VCC3P3DR_VCC3P3 VCC3P3 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. SDRAM B DE2-115 Main Board A 4 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. SDRAM B DE2-115 Main Board A 4 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. SDRAM B DE2-115 Main Board A 4 27Friday, September 24, 2010 C287 0.1u C284 0.1u C281 0.1u C282 0.1u U13 SDRAM 32Mx16 A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 nCAS17 nRAS18 LDQM15 nWE16 nCS19 CKE37 CLK38 UDQM39 D0 2 D1 4 D2 5 D3 7 D4 8 D5 10 D6 11 D7 13 D8 42 D9 44 D10 45 D11 47 D12 48 D13 50 D14 51 D15 53 A1236 BA020 V D D 1 V D D 2 7 V S S 2 8 V S S 4 1 A1022 V D D Q 3 V D D Q 9 V D D Q 4 3 V D D Q 4 9 V S S Q 6 V S S Q 1 2 V S S Q 4 6 V S S Q 5 2 A1135 BA121 V S S 5 4 V D D 1 4 R223 4.7K C85 10u R224 4.7K U15 SDRAM 32Mx16 A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 nCAS17 nRAS18 LDQM15 nWE16 nCS19 CKE37 CLK38 UDQM39 D0 2 D1 4 D2 5 D3 7 D4 8 D5 10 D6 11 D7 13 D8 42 D9 44 D10 45 D11 47 D12 48 D13 50 D14 51 D15 53 A1236 BA020 V D D 1 V D D 2 7 V S S 2 8 V S S 4 1 A1022 V D D Q 3 V D D Q 9 V D D Q 4 3 V D D Q 4 9 V S S Q 6 V S S Q 1 2 V S S Q 4 6 V S S Q 5 2 A1135 BA121 V S S 5 4 V D D 1 4 R226 4.7K R225 4.7K C286 0.1u C260 0.1u C272 0.1u C258 0.1u C261 0.1u C259 0.1u C280 0.1u C283 0.1u R235 0 R234 4.7K C262 0.1u C273 0.1u C82 10u 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SRAM_ADDR19 SRAM_ADDR18 SRAM_ADDR17 SRAM_ADDR16 SRAM_ADDR15 SRAM_ADDR14 SRAM_ADDR13 SRAM_ADDR12 SRAM_ADDR11 SRAM_ADDR10 SRAM_ADDR7 SRAM_ADDR6 SRAM_ADDR5 SRAM_ADDR4 SRAM_ADDR3 SRAM_ADDR2 SRAM_ADDR1 SRAM_ADDR0 SRAM_DQ0 SRAM_DQ1 SRAM_DQ2 SRAM_DQ3 SRAM_DQ4 SRAM_DQ5 SRAM_DQ6 SRAM_DQ7 SRAM_DQ8 SRAM_DQ9 SRAM_DQ10 SRAM_DQ11 SRAM_DQ12 SRAM_DQ13 SRAM_DQ14 SRAM_DQ15 SRAM_ADDR8 SRAM_ADDR9 SRAM_CE_N SRAM_DQ[15..0] SRAM_ADDR[19..0] SRAM_CE_N SRAM_OE_N SRAM_WE_N SRAM_UB_N SRAM_LB_N SR_VCC3P3VCC3P3 SR_VCC3P3 SR_VCC3P3 SR_VCC3P3 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. SRAM B DE2-115 Main Board A 5 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. SRAM B DE2-115 Main Board A 5 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. SRAM B DE2-115 Main Board A 5 27Friday, September 24, 2010 C289 0.1u U17 SRAM 1Mx16 A05 A14 A23 A32 A41 A548 A647 A746 A845 A930 A1029 A1128 A1227 A1326 A1425 A1524 A1623 A1722 A1821 A1920 I/O0 8 I/O1 9 I/O2 10 I/O3 11 I/O4 14 I/O5 15 I/O6 16 I/O7 17 I/O8 32 I/O9 33 I/O10 34 I/O11 35 I/O12 38 I/O13 39 I/O14 40 I/O15 41 CE_n7 WE_n18 OE_n44 UB_n43 LB_n42 V D D 1 2 V D D 3 6 G N D 1 3 G N D 3 7 NC1 6 NC2 19 NC3 31 C290 0.1u R78 0 R240 4.7K C86 10u 5 5 4 4 3 3 2 2 1 1 D D C C B B A A FL_ADDR0 FL_CE_N FL_RY FL_ADDR2 FL_ADDR18 FL_ADDR21 FL_ADDR17 FL_ADDR16 FL_ADDR15 FL_ADDR14 FL_ADDR13 FL_ADDR12 FL_ADDR11 FL_ADDR10 FL_ADDR20 FL_ADDR19 FL_ADDR9 FL_ADDR8 FL_ADDR7 FL_ADDR6 FL_ADDR5 FL_ADDR4 FL_ADDR3 FL_ADDR22 FL_ADDR1 FL_DQ7 FL_DQ6 FL_DQ5 FL_DQ4 FL_DQ3 FL_DQ2 FL_DQ1 FL_DQ0 SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_DAT1 SD_DAT3 SD_DAT2 SD_CMD SD_DAT0 SD_WP_N FL_RY FL_DQ[7..0] FL_ADDR[22..0] FL_CE_N FL_OE_N FL_WE_N FL_RST_N FL_WP_N SD_CMD SD_CLK SD_DAT[3..0] SD_WP_N F_VCC3P3 F_VCC3P3 F_VCC3P3 F_VCC3P3VCC3P3 F_VCC3P3 F_VCC3P3 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Flash & SD B DE2-115 Main Board A 6 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Flash & SD B DE2-115 Main Board A 6 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Flash & SD B DE2-115 Main Board A 6 27Friday, September 24, 2010 9 1 2 3 4 5 6 7 8 11 U26 SD Card Socket DAT3 CMD VSS VCC CLK VSS DAT0 DAT1 DAT2 VSS WP VSSVSSVSSVSS C274 10u C285 0.1u C291 0.1u R238 4.7K C288 0.1u U18 FLASH 8Mx8 A153 A144 A135 A126 A117 A108 A99 A810 A1911 A2012 WE#13 RESET#14 A2115 WP#ACC16 RY/BY#17 A1818 A1719 A720 A621 A522 A423 A324 A225 A126 A1654 BYTE#53 VSS 52 DQ15/A-1 51 DQ7 50 DQ14 49 DQ6 48 DQ13 47 DQ5 46 DQ12 45 DQ4 44 VCC 43 DQ11 42 DQ3 41 DQ10 40 DQ2 39 DQ9 38 DQ1 37 DQ8 36 DQ0 35 OE#34 VSS 33 CE#32 A031 A222 A231 A2456 A2555 VIO 29 RFU0 27 RFU1 28 RFU2 30 C87 10u R236 10K RN2410K 1 2 3 45 6 7 8 R239 4.7K R79 0 R237 10K 5 5 4 4 3 3 2 2 1 1 D D C C B B A A L C D _ V C C L C D _ B L LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 L C D _ C O N T L C D _ D A T A 6 L C D _ D A T A 7 L C D _ D A T A 5 L C D _ D A T A 2 L C D _ D A T A 1 L C D _ D A T A 4 L C D _ D A T A 3 L C D _ D A T A 0 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LEDR9 LEDR8 LEDG8 LEDR3 LEDR2 LEDR1 LEDR0 LEDR4 LEDR5 LEDR7 LEDR6 LEDR13 LEDR12 LEDR10 LEDR11 LEDR16 LEDR15 LEDR14 LEDR17 LEDG2 LEDG1 LEDG3 LEDG0 LEDG4 LEDG7 LEDG6 LEDG5 LCD_BLON LCD_ON L C D _ E N L C D _ R S LEDR[17..0] L C D _ R W LCD_DATA[7..0] LEDG[8..0] VCC43 VCC43 VCC43 VCC5 VCC3P3 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. LCD & LED B DE2-115 Main Board B 7 27Friday, September 24, 2010 Title Size Document Number Rev Date: Sheet of Copyright (c) 2007 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. LCD & LED B DE2-115 Main Board B 7 27Friday, September 24, 2010 Title Size