ADC0801/ADC0802/ADC0803/ADC0804/ADC0805/

TL/H/5671 A D C 0 8 0 1 / A D C 0 8 0 2 / A D C 0 8 0 3 / A D C 0 8 0 4 / A D C 0 8 0 5 8 -B it m P C o m p a tib le A / D C o n v e rte rs December 1994 ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit mP Compatible A/D Converters General Description The ADC0801, ADC0802, ADC0803, ADC0804 and ADC0805 are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric ladderÐ similar to the 256R products. These converters are de- signed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATEÉ output latches di- rectly driving the data bus. These A/Ds appear like memory locations or I/O ports to the microprocessor and no inter- facing logic is needed. Differential analog voltage inputs allow increasing the com- mon-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Features Y Compatible with 8080 mP derivativesÐno interfacing logic needed - access time - 135 ns Y Easy interface to all microprocessors, or operates ‘‘stand alone’’ Y Differential analog voltage inputs Y Logic inputs and outputs meet both MOS and TTL volt- age level specifications Y Works with 2.5V (LM336) voltage reference Y On-chip clock generator Y 0V to 5V analog input voltage range with single 5V supply Y No zero adjust required Y 0.3× standard width 20-pin DIP package Y 20-pin molded chip carrier or small outline package Y Operates ratiometrically or with 5 VDC, 2.5 VDC, or ana- log span adjusted voltage reference Key Specifications Y Resolution 8 bits Y Total error g(/4 LSB, g(/2 LSB and g1 LSB Y Conversion time 100 ms Typical Applications TL/H/5671–1 8080 Interface TL/H/5671–31 Error Specification (Includes Full-Scale, Zero Error, and Non-Linearity) Part Full- VREF/2e2.500 VDC VREF/2eNo Connection Number Scale (No Adjustments) (No Adjustments) Adjusted ADC0801 g(/4 LSB ADC0802 g(/2 LSB ADC0803 g(/2 LSB ADC0804 g1 LSB ADC0805 g1 LSB TRI-STATEÉ is a registered trademark of National Semiconductor Corp. Z-80É is a registered trademark of Zilog Corp. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A. Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) (Note 3) 6.5V Voltage Logic Control Inputs b0.3V to a18V At Other Input and Outputs b0.3V to (VCCa0.3V) Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260§C Dual-In-Line Package (ceramic) 300§C Surface Mount Package Vapor Phase (60 seconds) 215§C Infrared (15 seconds) 220§C Storage Temperature Range b65§C to a150§C Package Dissipation at TAe25§C 875 mW ESD Susceptibility (Note 10) 800V Operating Ratings (Notes 1 & 2) Temperature Range TMINsTAsTMAX ADC0801/02LJ, ADC0802LJ/883 b55§CsTAsa125§C ADC0801/02/03/04LCJ b40§CsTAsa85§C ADC0801/02/03/05LCN b40§CsTAsa85§C ADC0804LCN 0§CsTAsa70§C ADC0802/03/04LCV 0§CsTAsa70§C ADC0802/03/04LCWM 0§CsTAsa70§C Range of VCC 4.5 VDC to 6.3 VDC Electrical Characteristics The following specifications apply for VCCe5 VDC, TMINsTAsTMAX and fCLKe640 kHz unless otherwise specified. Parameter Conditions Min Typ Max Units ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. g(/4 LSB (See Section 2.5.2) ADC0802: Total Unadjusted Error (Note 8) VREF/2e2.500 VDC g(/2 LSB ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj. g(/2 LSB (See Section 2.5.2) ADC0804: Total Unadjusted Error (Note 8) VREF/2e2.500 VDC g1 LSB ADC0805: Total Unadjusted Error (Note 8) VREF/2-No Connection g1 LSB VREF/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kX ADC0804 (Note 9) 0.75 1.1 kX Analog Input Voltage Range (Note 4) V(a) or V(b) Gnd–0.05 VCCa0.05 VDC DC Common-Mode Error Over Analog Input Voltage g(/16 g(/8 LSB Range Power Supply Sensitivity VCCe5 VDC g10% Over g(/16 g(/8 LSB Allowed VIN(a) and VIN(b) Voltage Range (Note 4) AC Electrical Characteristics The following specifications apply for VCCe5 VDC and TAe25§C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units TC Conversion Time fCLKe640 kHz (Note 6) 103 114 ms TC Conversion Time (Note 5, 6) 66 73 1/fCLK fCLK Clock Frequency VCCe5V, (Note 5) 100 640 1460 kHz Clock Duty Cycle (Note 5) 40 60 % CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s Mode CSe0 VDC, fCLKe640 kHz tW(WR)L Width of WR Input (Start Pulse Width) CSe0 VDC (Note 7) 100 ns tACC Access Time (Delay from Falling CLe100 pF 135 200 ns Edge of RD to Output Data Valid) t1H, t0H TRI-STATE Control (Delay CLe10 pF, RLe10k 125 200 ns from Rising Edge of RD to (See TRI-STATE Test Hi-Z State) Circuits) tWI, tRI Delay from Falling Edge 300 450 ns of WR or RD to Reset of INTR CIN Input Capacitance of Logic 5 7.5 pF Control Inputs COUT TRI-STATE Output 5 7.5 pF Capacitance (Data Buffers) CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical ‘‘1’’ Input Voltage VCCe5.25 VDC 2.0 15 VDC (Except Pin 4 CLK IN) 2 AC Electrical Characteristics (Continued) The following specifications apply for VCC e 5VDC and TMIN s TA s TMAX, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (0) Logical ‘‘0’’ Input Voltage VCCe4.75 VDC 0.8 VDC (Except Pin 4 CLK IN) IIN (1) Logical ‘‘1’’ Input Current VINe5 VDC 0.005 1 mADC (All Inputs) IIN (0) Logical ‘‘0’’ Input Current VINe0 VDC b1 b0.005 mADC (All Inputs) CLOCK IN AND CLOCK R VTa CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 VDC Threshold Voltage VTb CLK IN (Pin 4) Negative 1.5 1.8 2.1 VDC Going Threshold Voltage VH CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 VDC (VTa)b(VTb) VOUT (0) Logical ‘‘0’’ CLK R Output IOe360 mA 0.4 VDC Voltage VCCe4.75 VDC VOUT (1) Logical ‘‘1’’ CLK R Output IOeb360 mA 2.4 VDC Voltage VCCe4.75 VDC DATA OUTPUTS AND INTR VOUT (0) Logical ‘‘0’’ Output Voltage Data Outputs IOUTe1.6 mA, VCCe4.75 VDC 0.4 VDC INTR Output IOUTe1.0 mA, VCCe4.75 VDC 0.4 VDC VOUT (1) Logical ‘‘1’’ Output Voltage IOeb360 mA, VCCe4.75 VDC 2.4 VDC VOUT (1) Logical ‘‘1’’ Output Voltage IOeb10 mA, VCCe4.75 VDC 4.5 VDC IOUT TRI-STATE Disabled Output VOUTe0 VDC b3 mADC Leakage (All Data Buffers) VOUTe5 VDC 3 mADC ISOURCE VOUT Short to Gnd, TAe25§C 4.5 6 mADC ISINK VOUT Short to VCC, TAe25§C 9.0 16 mADC POWER SUPPLY ICC Supply Current (Includes fCLKe640 kHz, Ladder Current) VREF/2eNC, TAe25§C and CSe5V ADC0801/02/03/04LCJ/05 1.1 1.8 mA ADC0804LCN/LCV/LCWM 1.9 2.5 mA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd. Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC. Note 4: For VIN(b)t VIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 5: Accuracy is guaranteed at fCLK e 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 2 and section 2.0. Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 5. Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kX. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kX. Note 10: Human body model, 100 pF discharged through a 1.5 kX resistor. 3 Typical Performance Characteristics Logic Input Threshold Voltage vs. Supply Voltage Delay From Falling Edge of RD to Output Data Valid vs. Load Capacitance CLK IN Schmitt Trip Levels vs. Supply Voltage fCLK vs. Clock Capacitor Full-Scale Error vs Conversion Time Effect of Unadjusted Offset Error vs. VREF/2 Voltage Output Current vs Temperature Power Supply Current vs Temperature (Note 9) Linearity Error at Low VREF/2 Voltages TL/H/5671–2 4 TRI-STATE Test Circuits and Waveforms t1H t1H, CLe10 pF tre20 ns t0H t0H, CLe10 pF tre20 ns TL/H/5671–3 Timing Diagrams (All timing is measured from the 50% voltage points) Output Enable and Reset INTR Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR. TL/H/5671–4 5 Typical Applications (Continued) 6800 Interface Ratiometric with Full-Scale Adjust Note: before using caps at VIN or VREF/2, see section 2.3.2 Input Bypass Capacitors. Absolute with a 2.500V Reference *For low power, see also LM385-2.5 Absolute with a 5V Reference Zero-Shift and Span Adjust: 2VsVINs5V Span Adjust: 0VsVINs3V TL/H/5671–5 6 Typical Applications (Continued) Directly Converting a Low-Level Signal VREF/2e256 mV A mP Interfaced Comparator For: VIN(a)lVIN(b) OutputeFFHEX For: VIN(a)kVIN(b) Outpute00HEX 1 mV Resolution with mP Controlled Range VREF/2e128 mV 1 LSBe1 mV VDACsVINs(VDACa256 mV) Digitizing a Current Flow TL/H/5671–6 7 Typical Applications (Continued) Self-Clocking Multiple A/Ds *Use a large R value to reduce loading at CLK R output. External Clocking 100 kHzsfCLKs1460 kHz Self-Clocking in Free-Running Mode *After power-up, a momentary grounding of the WR input is needed to guarantee operation. mP Interface for Free-Running A/D Operating with ‘‘Automotive’’ Ratiometric Transducers *VIN(b)e0.15 VCC 15% of VCCsVXDRs85% of VCC Ratiometric with VREF/2 Forced TL/H/5671–7 8 Typical Applications (Continued) mP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis) *See Figure 5 to select R value DB7e‘‘1’’ for VIN(a)lVIN(b)a(VREF/2) Omit circuitry within the dotted area if hysteresis is not needed Handling g10V Analog Inputs *Beckman Instruments Ý694-3-R10K resistor array Low-Cost, mP Interfaced, Temperature-to-Digital Converter mP Interfaced Temperature-to-Digital Converter *Circuit values shown are for 0§CsTAsa128§C **Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage. TL/H/5671–8 9 Typical Applications (Continued) Handling g5V Analog Inputs TL/H/5671–33 *Beckman Instruments Ý694-3-R10K resistor array Read-Only Interface TL/H/5671–34 mP Interfaced Comparator with Hysteresis TL/H/5671–35 Analog Self-Test for a System TL/H/5671–36 Protecting the Input TL/H/5671–9 A Low-Cost, 3-Decade Logarithmic Converter TL/H/5671–37*LM389 transistors A, B, C, D e LM324A quad op amp Diodes are 1N914 10 Typical Applications (Continued) 3-Decade Logarithmic A/D Converter Noise Filtering the Analog Input fCe20 Hz Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order, low-pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Multiplexing Differential Inputs Output Buffers with A/D Data Enabled *A/D output data is updated 1 CLK period prior to assertion of INTR Increasing Bus Drive and/or Reducing Time on Bus *Allows output data to set-up at falling edge of CS TL/H/5671–10 11 Typical Applications (Continued) Sampling an AC Input Signal Note 1: Oversample whenever possible [keep fs l 2f(b60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter. Note 2: Consider the amplitude errors which are introduced within the passband of the filter. 70% Power Savings by Clock Gating (Complete shutdown takes & 30 seconds.) Power Savings by A/D and VREF Shutdown TL/H/5671–11 *Use ADC0801, 02, 03 or 05 for lowest power consumption. Note: Logic inputs can be driven to VCC with A/D supply at zero volts. Buffer prevents data bus from overdriving output of A/D when in shutdown mode. 12 Functional Description 1.0 UNDERSTANDING A/D ERROR SPECS A perfect A/D transfer characteristic (staircase waveform) is shown in Figure 1a. The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digital output codes that correspond to these inputs are shown as Db1, D, and Da1. For the perfect A/D, not only will center- value (Ab1, A, Aa1, . . . . ) analog inputs produce the cor- rect output ditigal codes, but also each riser (the transitions between adjacent output codes) will be located g(/2 LSB away from each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be pro- vided for a range of analog input voltages that extend g(/2 LSB from the ideal center-values. Each tread (the range of analog input voltage that provides the same digital output code) is therefore 1 LSB wide. Figure 1b shows a worst case error plot for the ADC0801. All center-valued inputs are guaranteed to produce the cor- rect output codes and the adjacent risers are guaranteed to be no closer to the center-value points than g(/4 LSB. In other words, if we apply an analog input equal to the center- value g(/4 LSB,we guarantee that the A/D will produce the correct digital code. The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guaranteed to be no more than (/2 LSB. The error curve of Figure 1c shows a worst case error plot for the ADC0802. Here we guarantee that if we apply an analog input equal to the LSB analog voltage center-value the A/D will produce the correct digital code. Next to each transfer function is shown the corresponding error plot. Many people may be more familiar with error plots than transfer functions. The analog input voltage to the A/D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC. Notice that the error is con- tinuously displayed and includes the quantization uncertain- ty of the A/D. For example the error at point 1 of Figure 1a is a(/2 LSB because the digital code appeared (/2 LSB in advance of the center-value of the tread. The error plots always have a constant negative slope and the abrupt up- side steps are always 1 LSB in magnitude. Transfer Function Error Plot a) Accuracyeg0 LSB: A Perfect A/D Transfer Function Error Plot b) Accuracyeg(/4 LSB Transfer Function Error Plot c) Accuracyeg(/2 LSB TL/H/5671–12 FIGURE 1. Clarifying the Error Specs of an A/D Converter 13 Functional Description (Continued) 2.0 FUNCTIONAL DESCRIPTION The ADC0801 series contains a circuit equivalent of the 256R network. Analog switches are sequenced by succes- sive approximation logic to match the analog difference in- put voltage [VIN(a) b VIN(b)] to a corresponding tap on the R network. The most significant bit is tested first and after 8 comparisons (64 clock cycles) a digital 8-bit binary code (1111 1111 e full-scale) is transferred to an output latch and then an interrupt is asserted (INTR makes a high- to-low transition). A conversion in process can be interrupt- ed by issuing a second start command. The device may be operated in the free-running mode by connecting INTR to the WR input with CSe0. To ensure start-up under all pos- sible conditions, an external WR pulse is required during the first power-up cycle. On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. As long as the CS input and WR input remain low, the A/D will re- main in a reset state. Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low-to- high transition . A functional diagram of the A/D converter is shown in Fig- ure 2. All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines. The converter is started by having CS and WR simulta- neously low. This sets the start flip-flop (F/F) and the result- ing ‘‘1’’ level resets the 8-bit shift register, resets the Inter- rupt (INTR) F/F and inputs a ‘‘1’’ to the D flop, F/F1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this ‘‘1’’ to the Q output of F/F1. The AND gate, G1, combines this ‘‘1’’ output with a clock signal to provide a reset signal to the start F/F. If the set signal is no longer present (either WR or CS is a ‘‘1’’) the start F/F is reset and the 8-bit shift register then can have the ‘‘1’’ clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would momentarily be at a ‘‘1’’ level) and the 8-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS and WR signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F/F. TL/H/5671–13 Note 1: CS shown twice for clarity. Note 2: SAR e Successive Approximation Register. FIGURE 2. Block Diagram 14 Functional Description (Continued) After the ‘‘1’’ is clocked through the 8-bit shift register (which completes the SAR search) it appears as the input to the D-type latch, LATCH 1. As soon as this ‘‘1’’ is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the TRI-STATE output latches. When LATCH 1 is subsequently enabled, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR input sig- nal. Note that this SET control of the INTR F/F remains low for 8 of the external clock periods (as the internal clocks run at (/8 of the frequency of the external clock). If the data output is continuously enabled (CS and RD both held low), the INTR output will still signal the end of conversion (by a high- to-low transition), because the SET input can control the Q output of the INTR F/F even though the RESET input is constantly at a ‘‘1’’ level in this operating mode. This INTR output will therefore stay low for the duration of the SET signal, which