Flash Memory测试简介

Memory测试原理5300PreparationandIntroduction1.Makesureallstudentshavefilledoutthesignupsheetandlunchmenu. IfclassatAdvantestLocation:FaxsignuptoLisa Ifon-site:signuplisttoLisaafterclass2.Attentiongetter3.Welcome Unit1: IntroductiontoFlashTechnologyUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresOverviewofMemoryDevicesCourseContentsTwoBasicMemoryCategories VolatileMemory易挥发存储器Dataislostwhenpowerisremoved. NonvolatileMemory非易挥发存储器 Dataremainsevenwhenpowerisremoved.Therearetwobasiccharacteristicsofmemorydevices.TheyfallunderthecategoriesofVolatileMemoryandNonvolatileMemory.VolatileMemoryismemorythatwhenyouunplugyourcomputerthememorythatwasstoredislost.Nonvolatilememoryissavedevenwhenthecomputerisunplugged.Anotherexampleisapagerthathasstoredinformation.Whenyourbatterywearsoutandyoureplaceitwithanewbattery,youdon’tloseyourinformationsimplybecauseyouremovedthebattery.VolatileMemory RAM–RandomAccessMemorySRAM-StaticRAMiscommonlyusedas640Kbcachememoryincomputers.DRAM-DynamicRAMiscommonlyusedforread-writememoryincomputers.OneformofVolatileMemoryisRandomAccessMemory–RAM.TherearetwotypesofRAM:StaticRAM(SRAM)andDynamicRAM(DRAM).Bothtypesareusedcommonlyincomputers(PC’s).Botharevolatilememoriessothatwhenyoushutoffthecomputeryoulosethememory.NonvolatileMemory ROM–ReadOnlyMemory,ROM,areprogrammedinawaferfabandcannotbeerasedorreprogrammedinthefield. PROM–ProgrammableROMcanbereprogrammedinthefieldbyapplyinglargervoltageswithspecialequipment. EPROM–ErasablePROMcanbeerasedwithUVlightandreprogrammedwithspecialequipment. EEPROM–ElectricallyErasablePROMcanbeerasedwithhighervoltagesandreprogrammedinthefield.ROMisaReadOnlyMemory.TherearethreetypesofROMs:ProgrammableROMs,EPROMs,andEEPROMs.TheProgrammableROM(PROM)isonethatisprogrammedbasicallybythepatterningprocessinPhotolithography.Thepatternsthatareareonthereticlesinphotolithographyaretransferredontothemetallayersoftheproductasitisbeingbuilt.Themetallayersarethenetchedeventuallyaccordingtothewaythepatternneedstobesetuptoprovidespecificlogicoperationsinthedevice.APROMisnoterasable.OnceyouhaveassembledinthewaferFabithastheinstructionsetforthemachineorthecomputer.YoucanonlychangeitbydiscardingthatPROMandreplacingitwithaPROMthathasadifferentprogram.AnEPROMisanErasablePROM.Itcanbeerasedoutinthefieldbutithastoberemovedfromthecomputertocompletethere-programming.UltravioletlightisusedtoerasethePROMandthenitgoesintoaparticulardevicetore-programmed.Itisnotreprogrammedinthecomputer.Thisisnotveryconvenient.ItlookslikeaPROMwiththeexceptionofawindowfortheultraviolettopenetrateinordertoerasetheprogramming.TheEEPROMwasdevelopedtoenablecomputeruserstoreprogramthePROMwithoutspecialequipmentandwithoutremovingitfromthecomputer.Itdoesrequire,though,highervoltagestoerasetheinformationandhighervoltagestoreprogram.Noneoftheseareveryconvenient.ThisledtothedevelopmentoftheFlashdevice.NonvolatileMemory NVRAM–NonvolatileRAM(Flash)issmallerthanPROMs,lessexpensive,andeasiertoprogramanderase. Magnetic–Magneticdiskandtapecanbeeasilyprogrammedanderasedbyuser,butareslowerthanFlash. Optical–CDROMcanbeeasilyprogrammedbyuserbutisslowerthanFlash.TheFlashMemoryDevicefallsunderthecategoryofNON-VolatileRAM.TheFlashMemoryDeviceissmallerthanthePROM,lessexpensiveandmucheasiertoeraseandreprogram.Itstillrequireshighvoltage.TherearetwoothercategoriesofNonvolatilememory:magneticandoptical.Magneticincludesmagneticdisks,magnetictape.OpticalincludesCDROMs.BenefitsofFlashMemoryChips SmallerthanEPROMSandEEPROMS Requiresonlyonetransistorandastoragecapacitorperbitcell. Canbequicklyandeasilyerasedandreprogrammedwithouttheneedofspecialequipment. Excellentforuseincellphones,pagers,calculators,portabledigitaldevices,automotive,flightdatarecorders,andpersonalcomputers. TheFlashdeviceisconvenientbecauseitissmallerthanEPROMSandEEPROMS.Italsoonlyrequiresonetransistorandonestoragecapacitorperbitcell.Acapacitorstoresacharge.So,whenaFlashdeviceisusedandtheelectricityisremovedthememoryremainsbecauseofthestoredcharge.Theinformationwillremainforawhilesothatyoucantakethetimetoreplacetheenergysource.Flashcanbequicklyandeasilyerasedandreprogrammedwithouttheneedforspecialequipment.Theyareexcellentdevicesforcellphones,pagers,andanyportabledigitaldevice.Forexample:theblackboxthatcontainsaudiorecordingsanddatagatheringofairlinecockpitactivity.SimpleROMMemoryArrayROM–ReadOnlyMemory.RememberthatROMisactuallyprogrammedbythewaferfab.Byutilizingthephotolithographyprocessthattransfersapatternonmetalbyamask.Thispatternfollowsinstructionsetsthatareneededtoperformcertainlogicoperationsinacomputeroramachine.ThenexttimeyouturnonyourcomputeroramachineinthefabnotethatanythingthatisdrivenbysomekindofmicroprocessorhastohavesomekindofROMinit.TheROMhastheinstructionsetwhichtellsthemachinewhattododuringtheinitializationphase.Inthetopdiagramwehaveatransistorwherethegateisnotconnected–thereforethegateisOFF.Inthebottomdiagramthegateisconnected,thereforeitisturnedON.SimpleDRAMMemoryArrayCapacitorcharged,Nocurrent,“0”Capacitoruncharged,Currentflow,“1” ActivateRowtoread Ifcapacitorwascharged,nocurrentflowsonbitline Ifcapacitornotcharged,currentflowsonbitline BufferoncolumnsenseampsRememberwetalkedaboutDynamicRAMusingtrenchcapacitorstoholdacharge.Thisdiagramshowsatransistorwiththetrenchcapacitorsontheside.Noticetheyoccupyspacehorizontally.Inorderforthiscapacitortobechargedthetransistorhastobeturnedon.ThegatesofthetransistorsareallconnectedtothisonelinecalledaWordline.AWordlineisalwaysunderstoodtobeconnectedtothegatesoftransistors.ThisholdstrueforFlashdevicesaswell.Thedrainsonthetransistorsareconnectedtobitlines.Thesourcesareconnectedtothecapacitors–inthiscasethetrenchcapacitors.ThebitlineismonitoredforelectricalcurrentinordertocommunicatetothesensingamplifierswhatkindofinformationisstoredintheRAM.Whenacapacitorisalreadychargedthereisnocurrentflowingthroughthetransistorandthereforethetransistorisshutoff.Ifitisturnedoffitisgiventhelogicstate“0”.Whenatransistorisconductingcurrentitisgivenalogicstateof“1”.SimpleEPROMMemoryArrayAsecond“floatinggate”servesasthestorageelementinanEPROM.TheEPROMislikeatransistorandithasanadditionalpolysilicongatebetweenthesubstrateandthecontrolgate.So,everyoneofthesememorycellshasafloatinggate.ThisisthedifferencebetweenanEPROMandtheDRAM.Thisisveryimportantintermsofspace.TheEPROMisabletobemorecompactbecausenowyoudon’thavetrenchcapacitorsonthesideandlaterallythetransistorscanbeplacedclosertogether.Nowyouhaveafloatinggatewhichactuallyservesasastoragecapacitor.ThisisthewholeideabehindtheEPROM.BasicFlashMemoryCellFloatingGateSourceGateFloatingGate(electricallyisolated)isthestorageelement charged=“programmed” neutral=“erased”FlashCellStructure-SimilartoEPROM,exceptElectrically-erasablep+SubstrateControlGateFloatingGateTheFlashdevicelooksverymuchliketheEPROM.Thestructureisthesame.ThefirstdielectriclayerisoxideandthelayerbetweenthefloatinggateandcontrolgateisONO.FlashCellOperation-ProgramModeChannelHot-ElectronInjectionGNDVG=+9.3VVD=+4.5VSourceDrainLookingattheoperationofthistransistorweseethatwebeginwithaSourcethatisgrounded.We’llapply9.3VtotheControlgateand4.5VtotheDrain.Whydoweneedsomuchvoltagetoturnonthistransistor?Wehavetwodielectricsandanextralayerofpolysilicon,soitwilloperatelikea1993transistor.Youneedalotofvoltagetoturnitonbecauseoftheverythicklayerofseparatingthecontrolgatefromthesubstrate.Theeffectofapplythevoltagescreatesanelectricfieldintwoareas.FlashCellOperation-ProgramModeChannelHot-electronInjectionGNDVG=+9.3VVD=+4.5VSourceDrainp+SubstrateControlGateFloatingGatee-e-e-e-e-e-e-e-e-e-e-e-e-e-Becauseoftheelectricfield,electronsoutofthesourceareattractedtowardsthedrain.Thisisexpectedbehaviorofatransistor.Alongthewayelectronscrashintosiliconatomsandcauseelectronstobeenergeticallyejectedthroughthetunneloxideandintothegate.Theseelectronsbecomestoredinthegate.FlashCellOperation-ProgramModeIDSConduction&FloatingGateCharge(Q)p+SubstrateGNDVG=+9.3VVD=+4.5VControlGateFloatingGateSourceDrainLogicstate“0”Overtimeasthecurrentcontinuesyouwillhaveafloatinggatethatisfullychargedwithelectrons.Youhaveastoredcharge.ThesymbolQindicatesacharge.AMDtechnologyconsidersthisalogicstate“0”.FlashCellOperation-EraseModeNegativeGate---F－NTunnelingp+SubstrateControlGatee-e-e-e-e-e-e-e-e-e-e-e-e-e-e-Electrically-erasablechargefromgateSourceDrainLogicstate“1”Toerasethedeviceyouhavetodisconnectthevoltages.Alloftheconnectionsarefloatingandultravioletlightisaddedtogettheelectronstoneutralizethecharge.Theelectronsfloatawayfromthefloatinggateintothesubstrate.ThereasonwebeginwithhowEPROMworksisbecauseaFlashstructureisjustlikeanEPROM,butthedifferenceisthatinordertoeraseanEPROMultravioletlightisrequired.ThisprocessisalsoperformedonthewafersinFab25about4timesintheprocessflowinordertoneutralizethechargeinthefloatinggates.Duringtheprocessachargewillbuildupinthetransistorsonthewaferbecausethewafersgothroughplasmachambersintheetchandthinfilmsmodules.Theseplasmashavehighelectricfieldsinsidethemandwillactuallycausetheelectronstobeinjectedintothefloatinggatecausingcharges.Lateronwhenyouwanttotesttheflashdevicesyouwanttomakethereiszerochargeinthefloatinggate.FlashMemoryBitThresholdVoltagesTheoperationoftheflashdevicerequiresthreehighvoltagetoreachthresholdvoltages.Itneedsoneparticularthresholdvoltagetoprogramit.Itneedsanotherparticularthresholdvoltagetoeraseit.Lastly,itneedsaparticularthresholdvoltageinordertoreadwhatisonit.FlashArrayArchitecture(schematic)Corememory(core)Eachofthesetransistorswithafloatinggateisamemorycell.Thisdiagramiscalledamemorycellarray.Intheformationofamemorydevicethegatesareconnectedasshownaboveinthepink.ThesearecalledWordlines.ThelinesthatconnecttothesourcesarecalledGroundlines.ThelinesthatconnectthedrainarecalledBitlines.TheBitlinesrun90degreeswithrespecttotheWordlines.ThewholearrayiscalledaMemoryCore.FlashArrayCellAddressingRowDecoderColumnDecoderSourceSwitchThesememorycellsneedtobeactivatedindividuallyinordertowork.Soifyouhave64millionoftheseinaFlashdeviceeachoneisaccessedindividually.Thisrequiresanelectronicinterfacetobeabletoaccessindividualmemorycells.Adecoderwillallowthis. RowDecodertoselectthegates Columndecodertoselectthedrains SourcedecodertoselectthesourcesThemicroprocessorcontrolsallofthesedecodersbydigitaladdresslinesorbinarylines.Ifwewantedtoactivateaparticularwordlineandabitlineandasourceline,thememorycellwhereallofthemintersectistheonethatisactivated.BasicMemoryDeviceInternalArchitecture1111000000000000A0A1A2A3A4A5A6A7Memorycell MemoryCellblock:每个CELL存储data（1/0） AddressDecoderCircuitry：地址译码以(A0～)来选择不同的memorycellorblock进行读写操作。 Input/OutputI/O)circuitry：是memoryCell和外界的输入输出接口，将data在(D0～)与Cell间传输。 ControlCircuitry：控制memoryCell工作状态的电路CE/OE/WE(ChipEnable/OutputEnable/WriteEnable)UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructures Unit2:DeviceTesting DCparametrictest ACparametrictest FunctionalTestUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresDCparametrictestISVM：ForcecurrentmessagevoltageVSIM:ForcevoltagemessagecurrentDCParametricTests：测试AddressDecoder和I/O回路中Input/OutputBuffer的DC特性。在DCTest中一般使用VSIM及ISVM的方法。 DCContactCheck开路/短路测试OPEN/SHORT Input/OutputLeakageCheck输入/输出漏电流测试INLEAK/OUTLEAK CMOSAutomaticSleepCMOS自动睡眠模式电流测试CMOSASM StandbyCurrentCheckDevice不工作时待机电流测试ICCSB OutputDriveVoltage&CurrentDevice电压及电流驱动能力测试VOH/VOLUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructures DCParametricTest OPEN/SHORTest INLEAK/OUTLEAKTest CMOSASM ICCSBTest VOH/VOLTestUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresOpenTestPurpose:测量devicepins是否correctlytoDUT/Testerchannel测量Device内部管脚是否有开路。 Groundallpins(includingVCC); SetVoltageClamp3.0volts; UsingPMU,forcepositiveornegativecurrent,onepinatatime; Measureresultantvoltage; Failstest(open)iftheabsolutevoltagemeasuredisgreaterthan1.5V;TestMethodUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresShortTestPurpose:测试thedevicepins是否有短路TestMethod: Groundallpins(includingVCC); SetVoltageClamp3.0volts; UsingPMU,forcepositiveornegativeVoltage,onepinatatime; Measureresultantcurrent; Failstest(short)iftheabsolutevoltagemeasuredislessthan0.2V.UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresDefinitionIIL --Inputleakagelow Thecurrentinaninputwhenitisforcedlowvoltage.IIH --Inputleakagehigh Thecurrentinaninputwhenitisforcedhighvoltage.Whytest? TheIILtestmeasurestheresistancefromaninputpintoVCC,IIHtestmeasurestheresistancefromaninputpintoVSS.Thetestinsuresthattheinputbuffersofferahighresistancewhenapply0vandVCC.InputLeakageTest(INLEAK)InputLeakageLowTest---IILTestMethod ApplyVCCmax. Preconditioningallinputstologic1withpindrivers. Inputdisable UsingPMU,forceindividualinputstoVSS. MeasurethecurrentflowsfromVCCtothepinbeingtested. Repeatthesametestoneachpin. FailsIILifmeasuredcurrentisoutsideofthespec.0VInputLeakageHighTest---IIHTestMethod ApplyVCCmax. Preconditioningallinputstologic0withpindrivers. Inputdisable UsingPMU,forceindividualinputstoVCC. MeasurethecurrentflowsfromthepinbeingtestedtoVSS. Repeatthesametestoneachpin. FailsIIHifmeasuredcurrentisoutsideofthespec.3.5VOutputLeakageTest---IOLPurpose:Tomeasuretheoutputcurrentleakage(1uAspec) ApplyVCCmax. PreconditioningallOutputstologic1withpindrivers. OutputDisable UsingPMU,forceindividualinputstoVCC. MeasurethecurrentflowsfromthepinbeingtestedtoVSS. Repeatthesametestoneachpin. FailsIOLifmeasuredcurrentisoutsideofthespec.TestMethodUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresOutputLeakageTest---IOHPurpose:Tomeasuretheoutputcurrentleakage(1uAspec) ApplyVCCmax. PreconditioningallOutputstologic0withpindrivers. OutputDisable UsingPMU,forceindividualinputstoVCC. MeasurethecurrentflowsfromthepinbeingtestedtoVSS. Repeatthesametestoneachpin. FailsIOHifmeasuredcurrentisoutsideofthespec.TestMethodUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresCMOSASMTestPurpose:ThistestcheckstheCMOSAutomaticSleepMode.ItisaguardbandedtestsusingaVccwhichis15-30%higherthanMax.Vccandtestsagainstalimitof10%guardband).Theinputpinsarebiasedattheworstpossibleconditionaswell(lowestVIHandhighestVIL). ApplyVCCmax. chipenabled,butatoutputdisablestate.(AutomaticSleepMode) MeasurecurrentflowingintoVCCpinatVIH&VIL FailureCMOSASMwhencurrentisoutofSPECTestMethodUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresICCSBTestPurpose:ThistestscheckstheIccStandbyCurrent(Icc3intheTTLTable).Thistestshouldbedonewithallinputshigh(VIH)andallinputslow(VIL).WiththemovetoeliminatetheTTLtable(mostcompaniesdoNOTuseTTLlogicanymore),thistesthasdecreasingimportance.TestMethod ApplyVCCmax. chipdisabled,butatoutputdisablestate.(StandbyMode) MeasurecurrentflowingintoVCCpinatVIH&VIL FailureICCSBwhencurrentisoutofSPECUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresOutputvoltagestesting VOH/IOH VOL/IOLUnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresOutputvoltagestesting---VOH/IOHDefinitionVOH--representstheminimumvoltage(V)producedbyanoutput(O)whentheoutputisinthelogic1(High)state.IOH--representsthecurrentsourcingcapabilities(I)ofanoutput(O)whentheoutputisinthelogic1(High)state.Whytest? VOH/IOHtestmeasurestheresistanceofanoutputpinwhentheoutputisinthelogic1state.ThistestinsuresthattheresistanceoftheoutputmeetsthedesignparametersandguaranteesthattheoutputwillprovidethespecifiedIOHcurrentwhilemaintainingtheproperVOHvoltage.TestMethod ApplyVCCmin. Preconditionoutputtologic1(outputhigh). UsingPMU,forceIOHcurrentperspecification. Wait1to5msec(SetPMUdelay). Measureresultantvoltage. FailsVOHofmeasuredvoltageislessthanthelimit.Outputvoltagestesting---VOH/IOHDefinitionVOL--representsthemaximumvoltage(V)producedbyanoutput(O)whentheoutputisinthelogic0(Low)state.IOL--representsthecurrentsinkingcapabilities(I)ofanoutput(O)whentheoutputisinthelogic0(Low)state.Whytest? VOL/IOLtestmeasurestheresistanceofanoutputpinwhentheoutputisinthe0state.ThistestinsuresthattheresistanceoftheoutputmeetsthedesignparametersandguaranteesthattheoutputwillprovidethespecifiedIOLcurrentwithoutexceedingtheVOLvoltage.Outputvoltagestesting---VOL/IOLTestMethodDUT ApplyVCCmin. Preconditionoutputtologic0(outputlow). UsingPMU,forceIOLcurrentperspecification. Wait1to5msec(SetPMUdelay). Measureresultantvoltage. FailsVOLofmeasuredvoltageisgreaterthanthelimit.OutputvoltagestestingACParametricTesting Outputsignal: -therise&falltimes. Relationshipbetweeninputsignals: -thesetup&holdtimes. Relationshipbetweeninputandoutputsignals: -thedelaytimes Successiverelationshipbetweeninputandoutputsignals: -thespeedtest.ACparametrictest---RiseandFallTime RiseandFalltime-Toguaranteethatoutputdatariseandfallrate.UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresACparametrictest---SetupTimeTSD Setuptime-TSDtoguaranteethatinputdatacanbereadwithinaminimumamountoftimebeforeareferencesignaloccurs.UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresACparametrictest---HoldTimeTHD Holdtime-THDtoguaranteethatinputdatacanbereadwithinaminimumamountoftimeafterareferencesignaloccurs.UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresACparametrictest---ProgramDelayTime PropagationDelayMeasurements-TAAtoguaranteethatanoutputsignalcanoccurwithinaspecifiedamountoftimeaftertheoccurrenceofareferencesignal.UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresFunctionalTestFunctionalTest：是为了保证Device的工作是Match它的TruthTable而进行的测试。由PatternGenerator模拟正常的工作状态，输出Pattern加入Device，将输出值与期望值相比较，Match的为Pass，不Match的为Fail。UnitonetopicsandobjectivesSystemOverview HardwareBlockDiagrams SystemResources ProgramTypes ProgramStructuresHierarchyinReducedfunctionalFaults Stuck-AtFault TransitionFault CouplingFault NPSF NeighborhoodPatternSensitiveFaultStuck-AtFault*Thelogicvalueofastuck-at(SA)cellorlineisalways0or1;itisalwaysinstate0orinstate1andcannotbechangedtotheoppositestate.TransitionFault*Acellorlinewhichfailstoundergoa0->1transitionwhenitiswrittenissaidtocontainanuptransitionfault;similarly,adowntransitionfaultistheimpossibilityofmakinga1->0transition.CouplingFault AwriteoperationwhichgeneratesanUoraYtransitioninonecellchangesthecontentsofasecondcell,where Udenotesawrite1operationtoacellcontaininga0andYdenotesawrite0operationtoacellcontaininga1. ThetypesofcouplingfaultsusedforDRAMarebasedonthefollowingassumptionsforread/writeoperations: Areadoperationwillnotcauseanerror. Anon-transitionwriteoperationwillnotcauseafault. Atransitionwriteoperationmaycauseafault.NeighborhoodPatternSensitiveFault APatternSensitiveFault(PSF)isdefinedasfollows:Thecontentsofacell,ortheabilitytochangethecontents,isinfluencedbythecontentsofallothercellsinthememory. ThePSFcanbeconsideredthemostgeneralcaseofthek-couplingfault. ThePSFmodelallowstheneighborhoodtotakeonanypositioninthememoryarray. Whentheneighborhoodisallowedtotakeononlyasingleposition,onespeaksaboutaNeighborhoodPatternSensitiveFault(NPSF).FunctionTestItemExample READ0/READALL+EMBERASE+BLANK PRGDIAG VERDIAG PRGRVCK RVCKSP P