eetop.cn_Interview_vlsi

Definition of Set-up, Hold and Propagation in Flip-Flops Figure 1 shows a basic diagram of a D Flip-Flop. Flip-Flops are very common elements in synchronous designs where clock signal provides the timing to various elements and clock domains. click here if you don’t see pictures 4 4 ����� ��� � ''DWD 4 &ON Figure Error! Bookmark not defined.: D Flip-Flop Setup time and hold time describe the timing requirements on the D input of a Flip-Flop with respect to the Clk input. Setup and hold time define a window of time which the D input must be valid and stable in order to assure valid data on the Q output. Setup Time (Tsu) – Setup time is the time that the D input must be valid before the Flip-Flop samples. Hold Time (Th) – Hold time is the time that D input must be maintained valid after the Flip-Flop samples. Propagation Delay (Tpd) – Propagation delay is the time that takes to the sampled D input to propagate to the Q output. &ON 4 W �� ��� W ����� � 'DWD Figure Error! Bookmark not defined.: Timing Diagram Simple Encryption System The question is to design minimal hardware system, which encrypts 8-bit parallel data. A synchronized clock is provided to this system as well. The output- encrypted data should be at the same rate as the input data but no necessarily with the same phase. The solution is presented in figure 1. click here if you don’t see pictures �����ff��fi fl�ffi�� �! fi ffi!" # �%$&fi ' &6 2( $>���@ '>���@'DWDBLQ>���@ 'DWDBRXW>���@ &ON 0HPRU\ Figure Error! Bookmark not defined.: Block Diagram of Encryption System The encryption system is centered around a memory device that perform a LUT (Look-Up Table) conversion. This memory functionality can be achieved by using a PROM, EPROM, FLASH and etc. The device contains an encryption code, which may be burned into the device with an external programmer. In encryption operation, the data_in is an address pointer into a memory cell and the combinatorial logic generates the control signals. This creates a read access from the memory. Then the memory device goes to the appropriate address and outputs the associate data. This data represent the data_in after encryption. $GGUHVV 'DWD �� �� �� �� �� �� �� �� )) �� Table Error! Bookmark not defined.: Example of Memory Content Pulse Duration Extender The question is to design a black box that receive a signal input (pulse) and multiply the duration of it by five. Note: the longer pulse can be transmitted at any time. The length of the longer pulse may not be accurate. click here if you don’t see pictures (�) *�+!, (.-!/ ,QSXW 2XWSXW W �W Fig ure Error! Bookmark not defined.: Pulse Duration Extender Figure 2 shows a general block diagram of the solution. &RXQWHU &ONBXS 021 35476!8�9;:<9;= >��Q@ 6WRSBFQW 6WRSBFQW Figure Error! Bookmark not defined.: General Block Diagram of Duration Extender After reset (or power-up), the counter, and Cnt_dn are de-asserted. When the Signal_in set to high (externally), the counter starts receiving clocks and counts up. The clock frequency must by higher then the Signal_in, could be about 100-1000 times to achieve good resolution on the output. When the Signal_in set to low, the counter stop counting up and the Cnt_dn set to high. Now the Clk_dn pin on the counter receives the clocks and start counting down. When the counter stop counting up and start counting down, the value its’ holds represents the number of “Clock Generator” ticks that happened when the Signal_in was high. The idea now is to count down but with slower clock, in this solution we are using a clock divider to divide the “Clock Generator” by 5. Therefore the counter will counter five times slower. When the counter reaches zero. It means that it finishes to count down and the time passed was five times longer then the Signal_in duration. Stop_cnt create a pulse, which reset the Cnt_dn and put the system in its idle state. The output of the system can be the Cnt_dn signal. Note: The above describe general block diagram and general concept. The details are not mention. Odd Number Clock Divider This question is really common. Design a clock divider that divides by odd number. The following answer shows how to design a divider by 3 which is asymmetrical. The trivial way is to use a state-machine concept; therefore the answer explains state-machine design step-by-step, from functional specifications towards a complete detailed design and implementation. A functional description of the asymmetrical divider is shown in Figure 1. click here if you don’t see pictures &ON 2XWSXW Figure Error! Bookmark not defined.: Functional Description of the Divider The first step is to draw a state diagram that describes the logical behavior of the circuit. Figure 2 introduces the state diagram of the divider. We can easily see that the divider consist of 3 states which means 2 Flip-Flops. Each step is done every clock cycle. W�X!Y2Z�[Q\ ] \_^ W�X!Y2Z�[ ` ] a ^ W�X!Y2Z�[ b ] a ^ c.d2e�d [ Figure Error! Bookmark not defined.: State diagram of the Divider We name the state with a unique name and define the outputs in the square brackets. Whenever the state-machine is in Count1, the output shall be 1. Whenever the state-machine is in Count2 or Count3, the output shall be 0. After obtaining the state diagram it is possible to describe the design with a symbolic state transition table. In this step we put all the information we gathered as shown in the following table. 3UHVHQW�6WDWH 1H[W�6WHS &RXQW� &RXQW� &RXQW� &RXQW� &RXQW� &RXQW� 2XWSXW � � � Table Error! Bookmark not defined.: Symbolic State Transition Table The next step is to go into details. We have 2 Flip-Flops and one output. This information is entered into an encoded state transition table. The functions can be extracted from a Karnaugh map, or in this case, use the table as a truth table. fhg i2j�i&k�l&mnl o�l i phi�q�l&mnl i!r 4� 4� '� '� � � � � ��� � � �� � 2XWSXW � � � Table Error! Bookmark not defined.: Encoded State Transition Table We can write the functions as: • D0 = Q1 • • D1 = NOT(Q0+Q1) • • OUT = D1 The implement of the divider by 3 is shown in Figure 3. The output can be connected to Q1 pin. 4 4 s7t u v5w x ' y�z 4 4 s7t u v5w x ' y�{ Figure Error! Bookmark not defined.: Implementation of the Divider Comments and suggestions: interview@hardware-guru.com Digital One Shot This “ one-shot” shall produce a single output pulse for any long pulse in the input. The length of the output pulse shall be one clock cycle. Assume that the input pulse is as you see in the following figure. click here if you don’t see pictures Figure Error! Bookmark not defined.: One Shot Timing Diagram The answer is showed in Figure 2. It’s based on two flip-flops, which create a delay on the signal input. Then the result of the outputs (Q0, Q1) are logically AND, and output the result. 4 4 |7} ~ 5€  ' ‚�ƒ 4 4 |7} ~ 5€  ' ‚�„ ,QSXW 2XWSXW &ON Figure Error! Bookmark not defined.: One Shot Schematics Figure Error! Bookmark not defined.: One Shot Detailed Timing Diagram This is a simplified design and thus has some problems (hint: asynchronous input). Please write to us with your improvement ideas and we will update the entire solution with your inputs. Comments and suggestions: interview@hardware-guru.com The following are some of the questions I was asked in my interviews. The questions of course, depend on the position you are being interviewed and also on your Resume. So if you find any questions not relevant to your Resume, you can safely ignore them. Also, these questions are limited to VLSI Design, Computer Architeture and some basic Programming. If you are looking for something in Analog, RF etc, this is NOT the place. Okay alright...that makes sense...now lets get going... VLSI Design: 1) Explain why & how a MOSFET works 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation 3) Explain the various MOSFET Capacitances & their significance 4) Draw a CMOS Inverter. Explain its transfer characteristics 5) Explain sizing of the inverter 6)How do you size NMOS and PMOS transistors to increase the threshold voltage? 7) What is Noise Margin? Explain the procedure to determine Noise Margin 8) Give the expression for CMOS switching power dissipation 9) What is Body Effect? 10) Describe the various effects of scaling 11) Give the expression for calculating Delay in CMOS circuit 12) What happens to delay if you increase load capacitance? 13) What happens to delay if we include a resistance at the output of a CMOS circuit? 14) What are the limitations in increasing the power supply to reduce delay? 15) How does Resistance of the metal lines vary with increasing thickness and increasing length? 16) You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other 17) What happens if we increase the number of contacts or via from one metal layer to the next? 18) Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times 19) Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 20) Draw the stick diagram of a NOR gate. Optimize it 21) For CMOS logic, give the various techniques you know to minimize power consumption 22) What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus 23) Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? 24) In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? 25) Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) 26) Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram 27) Why don’t we use just one NMOS or PMOS transistor as a transmission gate? 28) For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD 29) Draw a 6-T SRAM Cell and explain the Read and Write operations 30) Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation) 31) What happens if we use an Inverter instead of the Differential Sense Amplifier? 32) Draw the SRAM Write Circuitry 33) Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? 34) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance? 35) What’s the critical path in a SRAM? 36) Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? 37) Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers 38) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? 39) How can you model a SRAM at RTL Level? 40) What’s the difference between Testing & Verification? 41) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) 42) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? Digital Design: 1) Give two ways of converting a two input NAND gate to an inverter 2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt) 3) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? 4) Give a circuit to divide frequency of clock cycle by two 5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) 6) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors) 7) The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? 8) What are the different Adder circuits you studied? 9) Give the truth table for a Half Adder. Give a gate level implementation of the same. 10) Draw a Transmission Gate-based D-Latch. 11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output) 12) How do you detect if two 8-bit signals are same? 13) How do you detect a sequence of "1101" arriving serially from a signal line? 14) Design any FSM in VHDL or Verilog. Computer Architecture: 1) What is pipelining? 2) What are the five stages in a DLX pipeline? 3) For a pipeline with 'n' stages, what’s the ideal throughput? What prevents us from achieving this ideal throughput? 4) What are the different hazards? How do you avoid them? 5) Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages? 6) What are Branch Prediction and Branch Target Buffers? 7) How do you handle precise exceptions or interrupts? 8) What is a cache? 9) What's the difference between Write-Through and Write-Back Caches? Explain advantages and disadvantages of each. 10) Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32-bit physical address, give the division between Block Offset, Index and Tag. 11) What is Virtual Memory? 12) What is Cache Coherency? 13) What is MESI? 14) What is a Snooping cache? 15) What are the components in a Microprocessor? 16) What is ACBF(Hex) divided by 16? 17) Convert 65(Hex) to Binary 18) Convert a number to its two's compliment and back 19) The CPU is busy but you want to stop and do some other task. How do you do it? C/C++, Perl & Unix: 1) How would you decide weather to use C, C++ or Perl for a particular project? 2) What are pointers? Why do we use them? 3) What are the benefits of having Global & Local Variables? 4) What is ’malloc’? Why do we need to use it? 5) Write a C program to compare two arrays and write the common elements in another array 6) Write a function in C to accept two integers and return the bigger integer 7) What are the advantages of C over Perl and vice versa? 8) What does ’@’ and ’&’ mean in Perl? 9) What is a ’Package’ in Perl? 10) What are Perl Regular Expressions? 11) Perl Regular Expressions are greedy. What does that mean? 12) What are Associative arrays in Perl? 13) Suppose a Perl variable has your name stored in it. Now, how can you define an array by the name? (i.e., you have $a="Adarsh"; now you want @Adarsh=[.....]) 14) Write a Perl script to parse a particular txt file and output to another file in a desired format. (You can expect the file to have some data arranged rows & columns) 15) Suppose you have the outputs of a test program in some big test file. In Perl, how can you test if all the outputs match a particular string? 16) What are Data Abstraction and Data Encapsulation? 17) Explain Friend Functions and Polymorphism with examples 18) Commands for changing directory, making directory, going up one directory, knowing the file permissions and changing file permissions. 19) How do you search for a particular string in all the text files in current directory from command line? 20) How do you sort a file alphabetically from command line? Other Simple Questions: 1) What is j to the power j? 2) What is Normal Distribution? Where is the Mean and Median on the graph for Normal Distribution? 3) Draw a simple RC-Low pass circuit. Some General Questions: 1) Tell me something about yourself and your interests 2) Tell me something about some problems you faced in a project and how did you handle it? 3) Give one instance where you were criticised by your Professor 4) Where do you see yourself five years from now? 5) What salary are you expecting? 6) Any Questions for me regarding the position or the company? 7) Finally, does this position sound interesting? :-) Frequently Asked Interview Questions I gathered these quest ions f rom several emails, sent to me by students who at tended on- site interviews at varios dif f erent companies. I shall t ry to add more of them in near f uture. 1. What is t he dif f er ence bet ween a lat ch and a f lip f lop. For t he same input , how would t he out put look f or a lat ch and f or a f lip-f lop. 2. Finit e st at e machines: (2.1)Design a st at e-machine (or dr aw a st at e-diagr am) t o give an out put ’ 1’ when t he # of A’ s ar e even and # of B’ s ar e odd. The input is in t he f or m of a ser ial-st r eam (one-bit per clock cycle). The input s could be of t he t ype A, B or C. At any given clock cycle, t he out put is a ’ 1’ , pr ovided t he # of A’ s ar e even and # of B’ s ar e odd. At any given clock cycle, t he out put is a ’ 0’ , if t he above condit ion is not sat isf ied. (2.2). To det ect t he sequence "abca" when t he input s can be a b c d. 3. minimize a boolean expr ession. 4. Dr aw t r ansist or level nand gat e. 5. Dr aw t he cr oss-sect ion of a CMOS inver t er . 6. Der iving t he vect or s f or t he st uck at 0 and st uck at 1 f ault s. 7. Given a boolean expr ession he asked me t o implement j ust wit h muxes but not hing else. 8. Dr aw I d Vds cur ves f or mosf et s and explain dif f er ent r egions. 9. Given t he t r ansf er char act er ist ics of a black box dr aw t he cir cuit f or t he black box. 10. Given a cir cuit and it s input s dr aw t he out put s exact t o t he t iming. 11. Given an inver t er wit h a par t icular t iming der ive an inver t er using t he pr evious one but wit h t he r equir ed t iming ot her t han t he pr evious one. 12. Change t he r ise t ime and f all t ime of a given cir cuit by not changing t he t r ansist or sizes but by using cur r ent mir r or s. 13. Some pr oblems on clamping diodes. These are some of the quest ions asked by Microsof t . (I f eel that these type of quest ions are asked even in Elect rical Engineering interviews. Make sure you browse them. ) 1. Given a r ect angular (cuboidal f or t he pur it ans) cake wit h a r ect angular piece r emove