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DM9000A Application Notes Fiber Mode V2_0

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DM9000A Application Notes Fiber Mode V2_0DM9000A Application Notes Fiber Mode V2_0 DM9000A Application Notes DM9000A 16/ 8 Bit Three-In-One Fast Ethernet Controller Application Notes V2.00F Technical Reference Manual Davicom Semiconductor, Inc Date: May. 29, 2007 Preliminary Page 1 Version: ...

DM9000A Application Notes Fiber Mode V2_0
DM9000A Application Notes Fiber Mode V2_0 DM9000A Application Notes DM9000A 16/ 8 Bit Three-In-One Fast Ethernet Controller Application Notes V2.00F Technical Reference Manual Davicom Semiconductor, Inc Date: May. 29, 2007 Preliminary Page 1 Version: 2.00F May. 29, 2007 DM9000A Application Notes DM9000A Fiber Optics Mode Setting 1. Software PHY Register Setting: The TX Bit [10] of PHY DSCR REG. 16 is 100Base-TX/ FX mode control and is designed to let the system designers to select the fiber mode as well. If the value of the DSCR Bit [10] TX is "1", it means the DM9000A is set to 100Base-TX mode for 100Mbps Fast Ethernet. Besides, if the value is "0", the DM9000A is set to 100Base-FX mode for 100Mbps Fiber optics mode. The table 1.1 is shown setting the configuration of the DM9000A 100Base-TX/ FX mode, Davicom Specified Configuration Register (DSCR) – 16 Bit Bit Name Default Description 100Base-TX/ FX Mode Control 16.10 TX 1, RW 1 100Base-TX mode 0 100Base-FX mode Table 1.1 DM9000A 100Base-Tx/Fx Mode Configuration For example, to set the DM9000A in the fiber optics mode, static void dmfe_init_dm9000(struct net_device *dev)/* refer to Linux driver v1.26*/ { /* ... */ /* Set PHY 100M-FX Fiber on, and turn on (16.14) bypass scrambler function */ phy_write(db, 16, 0x4004); /* off (16.4) RPDCTR-EN reduce-power-down mode */ /* operating PHY media mode = DM9000_100M Full, with H/W Flow-control */ phy_write(db, 4, 0x400 | 0x1E1); /* TX capability all: phy_reg4 = 0x1E1 */ phy_write(db, 0, 0x2100); /* PHY 100M Full duplex mode fixed */ udelay(2000); /* wait > 2 ms (2~30 ms normal) for PHY power-on ready */ iow(db, 0x0A, 0x29);/* FCR REG.0AH TXPEN, BKPM (TX_Half), FLCE (RX) enable */ /* ... */ } Preliminary Page 2 Version: 2.00F May. 29, 2007 DM9000A Application Notes 2. Hardware Setting: Figure 2.1 Decoupling circuit. It is important to take care in the layout of the embedded circuit board to achieve optimum performance from the fiber transceivers. Figure 2.1 provides an example of a schematic for a power supply decoupling circuit that works well with these parts. It is further recommended that a contiguous ground plane be provided in the circuit board directly under the transceiver, to provide a low inductance ground for signal return current. The fiber transceiver can be supported by 5V or 3.3V. Please be careful that the values of the resistors are reference only and also contact with the embedded fiber transceiver vendor for further information. Preliminary Page 3 Version: 2.00F May. 29, 2007
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