智能IC卡外文文献翻译（英文+中文）

毕业 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 （论文）外文翻译外文 题 快递公司问题件快递公司问题件货款处理关于圆的周长面积重点题型关于解方程组的题及答案关于南海问题 目：AnewcontactlesssmartcardICusinganon-chipantennaandanasynchronousmicrocontroller译文题目：一种使用单片异步微控制器的新型非接触式智能IC卡文献出处：IEEEJournalofSolid-StateCircuits,2000,36(7):1101-1107外文作者：AndréAbrial,JackyBouvier,MarcRenaudin,PatriceSenn,PascalVivet字数统计：英文3010单词，16242字符；中文4546汉字外文文献：　AnewcontactlesssmartcardICusinganon-chipantennaandanasynchronousmicrocontrollerAbstractThispaperdescribesanewgenerationofContactlessSmartCardChipwhichintegratesanon-chipcoilconnectedtoapowerreceptionsystemandanemitter/receivermodulecompatiblewiththeIS014443standard,togetherwithanasynchronousquasi-delayinsensitive(QDI)8-bitmicrocontroller.BeyondtheContactlessSmartCardapplicationfield,thisnewchipdemonstratesthatsystem-on-chipintegratingpowerreceptionandmanagement,radio-frequencycommunication,andsignalprocessingisfeasible.Itassociatesanalog/digitalpartsaswellassynchronous/asynchronouslogicsandhasbeenfabricatedinaCMOSsixmetallayers0.25-mtechnologyfromSTMicroelectronics.IndexTermsAsynchronousprocessor,coil-on-chip,quasi-delayinsensitivecircuits,SmartCards,system-on-chip.I.INTRODUCTIONTheSmartCardmarketentersanewera,withaboomingnumberofapplicationsinvariousdomainsandnewcountrieswillingtousethistechnology.SmartCardsarebecomingmoreandmoreubiquitousandthetrendistointegrateacardreaderinallkindofequipment(PCs,PDAs,mobilephones,etc.).E-commerce,citizenadministration,andotherscouldbe,throughtheInternet,goodvehiclestoallowserviceproviderstodevelopnewservicesusingtheSmartCardasahigh-securitykeyelement.Inthiscontext,contactlessSmartCardsshouldplayanimportantpart.Theabsenceofcontactinduceslowermaintenancecost,improveseaseofuse,reliability,and,therefore,end-usersatisfaction.Theyaredeclinedinseveraltypesaccordingtothelocationoftheantenna.Itcanbeonthecard,onthemodule,orintegrateddirectlyonthechip.Thislatertechniquesignificantlydecreasescardfabricationcost.Moreover,astheuserstillinsertshiscardinareaderslot,transactionsremainassafeaswhenusingcardswithcontacts.Sincemostapplicationsrequirelow-costlow-powersystems,thegoalofthisworkistointegrateonasinglechipanantenna,anISO14443compliantradio-frequencyemitter/receiver,togetherwithanasynchronousmicrocontroller.Integratingthewholesystemonsiliconshouldpavethewaytonewreliablelow-costContactlessSmartCardchips.ThesemainkeytechnologiesusedtodesignthisnewSmartCardchiparepresentedinSectionII.TheSmartCardchipdesignisdetailedinSectionIII,andthedesignmethodologyisbrieflydescribedinSectionIV.ExperimentalresultsaregiveninSectionV.II.INNOVATIONTheinnovationofthischipliesintheassociationonthesamedieoftwokeytechnologies:anintegratedpowerreceptionsystemwithanon-chipcoil,andan8-bitCISCQDIasynchronousmicrocontroller.Thisassociationenablesustotakeadvantageoftheasynchronouslogicpropertiesinordertodecreasethedesignconstraintsoftheintegratedpowerreceptionsystemandalsotoincreasetheworkingdomainofthedigitalprocessingpart.Infact,theasynchronouslogichasthreeinterestingadvantagesvaluablefortheContactlessSmartCardapplicationconsideredhere.Insteadofbeingclockdriven,asynchronouscircuitsaredatadrivenwhichresultsinalowermean-powerconsumption.Insteadofimplementingacentralcontrolunit,asynchronouscircuitsimplementadistributedcontrolsystemwhichresultsinsmallercurrentpeaksandthenlowerelectromagneticemissionbecausetheelectricalactivityisspreadovertime.Finally,insteadofbeing“clocktimed”,asynchronouscircuitsareself-timedwhichenablesanautomaticregulationoftheperformance.Hence,QDIasynchronouscircuitsarenotsensitivetovoltagevariations,andrunsattheirmaximumspeedwithrespecttothepowerreceived.SincetheQDI8-bitmicrocontrollerissorobustwithrespecttothepowersupplyvariations(seeSectionIII),thedesignofthepowerreceptionsystemismadeeasier:loweraveragepowerdelivered,aswellasthepeakpower,andsimplifiedregulationofthesupplyvoltage.Thisnotonlymakesthedesigneasier,butalsodecreasesthearea(smallerVDDsmoothingcapacitance).Finally,becauseofitslowcurrentpeakstheQDIasynchronousmicrocontrollerdoesnotinterferewiththeloadmodulationusedintheISO14443standardforthecommunicationbetweenthecardandthereader.Thisenablesthemicrocontrollertorunwhilethechipistransferringdatatothereaderwhichdecreasesthecomplexityofthesoftwareandthenthememoryspacerequirements.III.SMARTCARDCHIPDESIGNTheSmartCardchipiscomposedoffourmainblocks(Fig.1).TheRFfront-endrecoverspowerfromtheintegratedantenna,whichformsatransformerwiththeexternalreadantenna.Therecoveredpoweristhenstabilizedandsuppliesthewholechip:theasynchronousmicrocontrollerandasynchronousdedicatedinterfacebetweentheRFblockandtheasynchronouscircuit.Thisinterfaceisdrivenbyareception-enablesignal(REN)controlledbythemicrocontroller.Inreceptionmode,theRFinterfacedemodulatesdatasentbythereader.Inemissionmode,dataaresenttothereaderusingaloadmodulation.ThesystemisISO14443-Bcompliant.WhentheSmartCardisinsertedinthereaderslot,assoonasthestabilizedsupplyreachesasufficientlevel,resetisactivatedbytheRFinterface.ThemicrocontrollerexecutesthebootprogramcontainedinROMandthenwaitsfordatacomingfromthereader.ThecommunicationbetweenthereaderandtheSmartCardisfunctionallyasynchronous.ThecombinationoftheRENsignalandthestartandstopbits(thecommunicationbetweenthereaderandthechipismadeonanasynchronousmode,withstartandstopbits),encapsulatingthetransmittedbyteimplementsahalf-duplexcommunication.A.AnalogBlockDesignSincetherearenocontacts,poweranddataarerecoveredfromRFsignalsemittedbythereader.Theanalogblockisinchargeof1)poweringthechip;2)demodulating/modulatingdatafrom/tothereader;3)recoveringtheclockusedinthesynchronous/asynchronousinterface.Comparedtoothercontactlesstechnologies,thecardisinsertedinaslotwhichensuresthatthedistancechipreaderiskeptconstantandsmall:thevariationsindistancearewithinmillimeters.Thisenablestheintegrationofthecoilon-chip.Then,thereisnoneedforthevoltagewhichisrecoveredfromtheRFpowertobeverywellregulated,asitisthecaseforcontactlesscardswhichoperateona“touchandgobasis.”Thedesignofthepowermanagementandanalogblockcircuitryisaccordinglysimplified.TheblockdiagramoftheRFfront-endisdescribedinFig.2.Itisbuiltofthefollowingparts.1)Thefullwaverectifier(FWR)isabridgecomposedofnMOSandpMOStransistors.Theelectro-motive-force(EMF)inducedintheon-chipantennaisappliedtotheFWRinputs.Thenegativeoutputisconnectedtothebulkandthepositiveoutputisconnectedtoa500Pfsmoothingcapacitor.ItdeliversthenonregulatedvoltageNRVtothechip.2)Theclockrecoveryblockextractsthe13.56-MHzclockfromtheRFcarriersignal.Forthispurpose,theinputofaSchmidttriggerisconnectedtooneofthetwoantennaterminals.3)Thepower-ondetector.Thisblockiscomposedofavoltagereference,adifferentialcomparatorandfilterstorejectmodulationparasitics.IttriggersaRESETwhentheNRVreachesagivenlevel.4)ThedatademodulatorisbasedonNRVamplitudetransitionsduetoNRZcodedtransmissionfromreadertochip.ThedatademodulatorextractsthedatamixedwithNRV,bydetectingnegativeandpositivetransitions.ThetwooutputsdrivetheinputsofanRSlatchwhichmakesthedataavailabletotheinterface.5)Theloadmodulatorisbuiltofaresistor(Rmod,seeFig.3)switchedbyannMOStransistorcontrolledbythedatatobesenttothereader.Itinducesanamplitudemodulationintheinductorantenna.Inemission,themodulatorhastomodulatethepowerabsorbedbythechipatan847-kHzBPSKrhythm.ThisismadebyamodulationofI(NRV),.ThisinducesanEMFinthereadersolenoid.6)Thecurrentgeneratorisassociatedwithazenerdiodetoachievepowerregulation.Aswewantinformationtobetransmittedtothereaderwhenthemicrocontrollerisrunning,andsincealoadmodulationisused,caremustbetakentothedynamiccurrentconsumptionofthemicrocontrollerwhichcaninduceNRVcurrentvariationsandthencorruptthecommunication.Topreventthisphenomenafromoccurring,aconstantcurrentsourceisusedtofeedthelogictogetherwitha2-Vshuntvoltagestabilizer.Theconstantcurrentgeneratorisdesignedtoprovidethemaximumcurrentneededbythelogicpart.ThismechanismensuresaconstantNRVcurrentandthereforeavoidsparasiticloadmodulationthatcouldbeinducedbysoftwarerunninginthemicrocontroller(Fig.4).Inthisprototype,thecurrentgeneratorisdesignedtodeliver15mAinordertosupplythemicrocontrolleraswellasanexternalnonvolatilememoryincludedinademonstratorunderdevelopment.B.Synchronous/AsynchronousInterfaceTheblockdiagramoftheinterfaceispresentedinFig.5.Itiscomposedofadivider,aBPSKmodulatorandablockwhichformatsthedatacomingfromtheexternalreaderandfromthemicrocontroller.TheRF13.56-MHzcarrierisrecoveredanddividedtoprovidea847-kHzsignalusedtoclocktheinterface.OntheRFinterfaceside,bytesareencapsulatedwithstartandstopbitswhicharethenreceivedoremittedsequentiallyatthe847-kHzbitrate.Onthemicrocontrollerside,anasynchronousfour-phasebundle-dataprotocolisused(8-bitdata,requestandacknowledgesignals)tocontroldataexchangeassertingP5ack.Thefour-phasehandshakeprotocolthencompleteswithtworeturn-to-zerophasesassoonastheonebytebufferisempty.Whenreceivingdatafromthereader,theRENsignalisdrivenhighandthemicrocontrollerisreadytoreceiveaninputbytebyassertingtheP4acksignal.TheinterfaceanswersrisingtheP4reqsignalassoonasabyteisavailablefromthereceiver.Thehandshakethencompleteswiththereturn-to-zerophase.Thehandshakeprotocolensuresthatboththemicrocontrollerandtheinterfaceareavailabletoacceptandtransmitabyteinemissionorreception.Thus,themicrocontrollerwillbeidledaslongastheinterfacedoesnotgrantitsrequest.Theprogramexecutionwillresumewhenthedatabyteisfinallysentorreceived.Aone-bytebufferallowsthemicrocontrollerandtheinterfacetorunconcurrently.Failuremayonlyoccurinreceptionifthemicrocontrollerdoesnotreadtheincomingbyteintime.Inthatcase,theinterfaceoverwritethenonreadbyte.Thistypeofcommunicationfailurescanbesolvedusingsoftwareerror-checking.C.QDIAsynchronous8-bitMicrocontrollerTheQDIasynchronous8-bitmicrocontrollerisaCISCmachine,basedonadedicated“luxurious”microarchitecture(Fig.6).Inordertofacilitatethedesignofa“C”compilerandalsotolimitmemoryaccesses,wedecidedtointegratetwodifferentregister-files:eight8-bitregistersaredevotedtodata,andeight16-bitregistersaredevotedtopointers(includingtheprogramcounterandthestackpointer).Specificarithmeticunitsareassociatedwitheachregisterfilesenablingconcurrentcomputationsofdataandaddresses.AdedicatedunitismanagingthestandardstatusbitsZ,N,V,andC.Aperipheralunitisalsoincluded,supportingsix8-bitparallelports(oneinput,fouroutputs,and1bidirectionalusedtocontrolexternalflashmemoriesandthesynchronous/asynchronousinterface)andfourseriallinks(usingatwo-phasedelayinsensitiveprotocolcompatiblewithourhigh-performanceRISCasynchronousAsproprocessor).Moreover,themicrocontrollerintegrates16kBRAMand2kBROM.TheROMincludesaBuilt-In-Self-Test(BIST)programwhichisexecutedatresetaccordingtothebootmodeselected(eightmodesareavailable).Itisa350assemblyinstructionroutinewhichperformsastuck-at-faulttestwhichcomputesasignaturewritten,onthefly,ononeoftheparallelporttoreportonself-testprogress.TheQDIasynchronouslogicusedisself-testablebecauseastuck-atfaultonanyinputofanygatewillcauseahandshaketostopforever(no“prematurefiring”).Asaresult,theBISTprogramwillneverproduceacompletesignature.•InstructionsetTheeight8-bitdataregistersarenamedr0tor7,andtheeight16-bitindexregistersi0toi7,wherei6andi7arethestack-pointerandtheprogram-counterrespectively.Thecontrollerimplementsthecommonarithmeticandlogicinstructions.Allinstructionsareencodedwithinoneword(16bits).Fourbasicaddressingmodesareavailable(immediate,register,indexedwithdisplacement,indexedpost-incrementedorpre-decremented)whichcanbeusedinconjunctionwithdataorindexregisteroperands.Lastly,thecontrollerimplementsamaskableinterruptmechanismanda“waitforinterrupt”instruction(Wfi).TableIsummarizestheinstructionset,notethe“copy”(Cp)andthe“Puch&Load”(Pl)instructions.Acompletesoftwaredevelopmentsuiteoftoolsiscurrentlyunderdevelopmentincludinga“C”compiler,anassembler,alinkerandasimulator.•ArchitecturedesignthearchitectureofMICAhasbeendesignedasadistributedsystem,eachpartprovidingspecificservices.Forexample,thetworegister-files,thestatusregisterandthememoryintegratelocalunitswhichmanagethememoryresources.Thesemodulesimplementfunctionssuchas“read,”“write,”“readthenwriteback,”orevenmorecomplexfunctionvlike:readabyte,increment/decrementthepointer/address,andreadthecorrespondingbyte(CpandPlinstructionsforexamplesusethesefeatures).AdoptingsuchanapproachsignificantlysimplifythedesignofthemainsequencerofaCISCmicroprocessorlikeMICA.Itthenminimizesthepowerconsumedbythemainsequencer,theconsumptionassociatedwitheachinstructionbeingthedirectimageofitscomplexity.Infact,complexinstructionimplementationdonotpenalizesimpleinstructionimplementationatthemainsequencerlevel.Moreover,suchadistributedap-proachminimizesthepowerconsumedbycommunicationssincetheminimumnumberoftransactionsoccurthroughbusses(memoryaccessesforexample).Becauseofthelow-powerconstraintandbecausecomputationalpowerwasnotapriorityforthetargetedapplications,aminimumnumberofpipelinestagewasintroduced.Thisdoesnotpreventparallelexecutionofinstructionsub-parts,butsimplymeansthatparallelexecutionofinstructionsisnotsupported.Insomecaseshowever,subsequentinstructionsmaypartiallyoverlap.Finally,atthesignallevel,communicationchannelsareusingalow-powerdataencoding.Insteadofusingdual-railcoding,wehaveimplementedn-railcoding(alsocalled“OneHot”),i.e.,oneoutoftheNwiresisactiveduringatransaction(insteadofoneoutoftwowithdual-rail).•MicrocontrollerperformanceBeforeintegratingthemicrocontrollerintheSmartCardchip,atestchiphasbeendesigned,fabricatedandtested.ThemicrocontrollerhasbeeneasilytestedthankstotheBIST,andwasfullyfunctionalatfirstsiliconbetween3Vdownto0.8V(2.5Visthenominalvoltageofthe0.25-mCMOStechnologyused).TableIIgivestheMIPS(meannumberofinstructionsexecutedpersecondwhenrunningtheBISTprogram),PowerandMIPS/Wattfiguresatdifferentvoltages(basedonthetotalcurrentconsumedbythecore,thememoryandthepads).Itisnoticeablethatthechiponlyconsumes800Wat1V,stilldeliveringacomputationalpowerof4.3MIPS.At0.8V,thechipconsumeslessthan400W.IV.DESIGNMETHODOLOGYTheSmartCardchiprepresentsacomplexsystemonchipwithseveraldifferentdesignstyles.Theanaloghasbeendesignedinfullcustom.Thesynchronous/asynchronousinterfacebetweentheanalogblockandthemicrocontrollerhasbeenmodeledusingVHDLasasynchronousfinitestatemachineandsynthesizedwithstandardCADtools.Asregardstotheasynchronouslogic,themicrocontrollerwasfirstdescribedinCHP,ahigh-levellanguagewellsuitedtomodelasynchronouscircuits.ModelvalidationwasperformedbyVHDLsimulation,thankstoaCHPtoVHDLtranslator.ThesynthesisoftheCHPmodelintoQDIlogicwasperformedbyhandandtheschematicmanuallycapturedinastandarddesignframework.Themicrocontrolleristhusbuiltof1)founderstandardcellsplussomespecificcells(Mullergates)andof2)foundersynchronouslow-powermemorieswithadditionalspecificinterfaces.Gate-levelandCHPco-simulationwasthenperformedinVHDLtovalidateeachblockaftersynthesis.Afterplace&route,thecompletesystem(excludedtheanalogblock)wasvalidatedbysimulatingaVHDLback-annotatedgatelevelnetlist.Finally,aswitchlevelsimulationwasperformedtoestimatethecorepowerconsumptionandthusdeterminetheSmartCardpowerreceptionsystemcharacteristics.Fig.7describesthecompletedesignflowwehavesetup.V.EXPERIMENTALRESULTSThechipwasfabricatedattheSTMicroelectronicsCrollesplantusinga6metal-layer0.25-mCMOSprocess.Padsareincludedinthisfirstprototypeinordertotestthechipandperformmeasurementsonboththedigitalandanalogparts.Thetotalchipareais16mmincludingthesepads.Theon-chip-coilissurroundingthechip(Fig.8).Thecoilismadeofsixturnsimplementedwiththeupperfivemetallayers.Itsareais1.5mm.TheCISCmicrocontrollerwithitsmemoryrepresentsonemilliontransistors.Fig.4showsthestabilizationoftheNRVcurrentwithrespecttotheVDDcurrentvariation.Forvalidatingthechipinasystemenvironment,areaderconnectedtoaPCviaanRS232portwasdesigned.ThereaderincludestheRFoscillator,the10%ASKmodulator,theBPSKdetector,andprovides1Wunder6-Vconditions.Thechipwasintegratedonaprototypecard.Wheninsertingthecardintothereadermagneticfield(11gauss,withload),aprogramisdownloadedintothemicrocontrolerRAManddataareexchangedbetweentheexternalPCandthecard.Thecircuithasbeensuccessfullyvalidatedusingseveralprogramdownloading,likedumpingthemicrocontrollerROMoridentifyingapinnumber.VI.CONCLUSIONThechippresentedinthispaperisthefirstprototypethatfullyintegratesaContactlessSmartCard(antenna,powerreception,RFcommunicationanddigitalprocessing).ItdemonstratesthatthedesignofsuchSystem-On-Chipisfeasibleusingthelatestindustrialtechnologies.Futureinvestigationswillfocusonthebenefitsoftheuseofanasynchronousmicrocontrollerwithrespecttoareagain(VDDsmoothingcapacitor),designcomplexityreductionandsoftwaresimplification.AnotherveryinterestingandpromisingperspectiveistoinvestigatetheabilityofasynchronouscircuitstoimproveSmartCardcircuitsresistanceagainstwellknownattackssuchasDPAanalysis,faultandglitchattacks.中文译文：一种使用单片异步微控制器的新型非接触式智能IC卡摘要本文介绍了一种新的非接触式智能卡芯片，它集成了一个片上线圈，连接到电源接收系统和发射器/接收器与ISO14443标准兼容的模块，连同一个异步准延迟不敏感（QDI）的8位微控制器。除了非接触式智能卡应用领域，这个新的芯片 表 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf 明，系统芯片上集成的电源接收和管理，射频通信，信号处理是可行的。它综合了模拟/数字以及同步/异步逻辑器件，并安装了一个意法半导体公司的0.25微米、CMOS六金属层的半导体。索引词异步处理器，片上线圈，异步准延迟不敏感，智能卡，系统芯片。I.介绍随着智能卡在不同领域应用的迅速发展，智能卡市场进入了一个新的时代，更多国家将应用这项技术。智能卡现在越来越普及，并且都趋向于在各种设备上集成读卡器，例如PC，PDA,移动电话，等等。使用智能卡，商家、城市行政部门和其它的服务商可以通过网络提供高安全性的新型服务。非接触式智能卡将要在这些应用中起重要作用。读写时不用进行接触不仅缩减了维修费用，而且提高了卡的易用性和可靠性，赢得了最终用户的满意。它通过本地的天线拒绝了几项服务。它可以应用在卡上，应用在模块上，或直接集成到芯片上。这项技术意味着卡的制造费用将减少。而且使用者一直将卡插在读卡器里，系统仍然是安全的。因为大多数应用系统成本低、低功耗。这项工程的总目标是整合射频线圈，符合ISO14443频率发射器/接收器与一个异步微控制器。将整个系统集成到半导体硅上降低制造成本和使非接触式智能卡更加可靠。用于设计新型非接触智能卡的主要技术将在第二部分有所陈述。智能卡设计细节在第三部分陈述，设计的方法论主要在第四部分讲述。实验结果在第五部分给出。II.创新本集成电路的创新归功于两项关键技术，集成在芯片上的电能接收线圈和一个8位CISCQDI异步处理器。这些联合是我们在异步逻辑上的宝贵财富。以便于降低综合功耗接收系统的限制并且工作范围扩展到数字信号处理领域。事实上，异步逻辑对于非接触式智能卡应用有三方面的意义。使用平均功耗较低的异步电路数字驱动代替了时钟驱动。使用小峰值电流的异步电路分布式控制系统代替中央控制执行单元，且减少了电磁辐射。最后使用自我调节的异步电路来控制时间代替了同步定时器。因此QDI异步电路对电压变化并不敏感，并且在所接到的信号的最大速度上运行。8位QDI微处理器电能供应系统的成熟（见第三部分），使得功耗接收系统的设计变得容易。较低的平均电力传输，相同的最大功耗，以及简化了的电压提供规则。这些不只是使设计变得容易也减少了面积（较少的VDD滤波电容）。最后因为它的低电压峰值，QDI异步微控制器不会干扰符合ISO14443标准的IC卡和读卡器之间的通信调制。这使得当芯片传输数据到读卡器时微控制器仍能运行，这减少了软件的复杂性和对存储器空间的需求。III．智能卡芯片设计智能卡芯片由四部分组成（如图1）。通过变压互感器来提供能量的射频天线以及接受芯片上的能量接收窗口，能够稳定为整个芯片提供能量；异步微控制器和一个RF模块与异步电路专用同步接口。这个接口由微处理器接收到的许可信号驱动。在接收模式中，RF接口解调数据通过读卡器发送。在发射模式中，数据使用负载调制送入读卡器。系统符合ISO14443-B标准。当智能卡插入读卡器插槽时，一旦电源供应达到稳定，RF接口被复位为活动状态。微控制器执行固化在ROM中的启动程序，然后等待从读卡器传来信号。在解读器和智能卡之间的信息传递是异步的。信号传递的开始与结束位（读卡器和集成电路之间的信息交流被设定为异步方式）半双工通信模式传递封包字节。A.模拟电路设计由于没有接触，能量和数字信号都通过脉冲频率被读卡器接收。模拟电路的功能：1）为集成电路提供电源2）从读卡器调制/解调数据3）恢复时钟用于同步或异步接口与其它的不接触工艺相比，卡片插入插槽保持的距离在毫米之内，这使电路集成在一块芯片上成为可能。由于使用RF射频提供能量而不需要电压，电源设计和模拟模块的电路图也相应的得到简化。RF模块如图2所示。它由以下几部分组成：1）全波整流器由nMOS和pMOS组成的晶体管桥接而成，天线集成电动势用于整流器输入，负载输出连接到大部分，正向输出连接到500PF滤波电容。2）时钟恢复模块提供13.56MHZ时钟频率从RF获得载波信号。为了实现这个效果输入连接到一个或两个天线终结点。3）电源监测器。这个模块由一个参考电压，一个微检测仪和过滤器组成。当NRV打到给定的电平时它触发一个复位信号。4）数字解调基于NRV振幅，由NRZ编码传递到读卡器芯片。数据解调器选录数据并且探测出是正向还是反向传递。两个输出驱动RS锁存输入，使得数据可以被接口访问。5）负载调节器由一个NMOS晶体管构成的电阻开关（如图3）控制数据发送到读卡器上。它导致感应天线的振幅调制。当发射时，芯片使调节器调节电源工作在847KHZBPSK。这在译读器中引起螺形电动势，电动势值由突变和夹带频率决定。电流发生器和齐纳二极管完成功耗调节。我们需要信息在微控制器运行时传递，因此，需要一个下载调制器，必须重视的是微控制器消耗原动电流，破坏信息。为了防止这种现象发生用一个不间断电流源提供一个稳定的2V电压。持续电流发生器被用于供应逻辑部分需要的最大电流，这个装置确保了一个不变的NRV电流。可以由软件执行消除负载调制产生的杂波。（如图4）在这个装置中，电流发生器被设计输出15MA电流以便满足控制器和外部非易失性存储器的需要。B.同步/异步接口接口模块简图如图5所示，它由一个分压器、一个解调器和一个处理来自外部读卡器和微控制器数据格式模块组成。这个13.56-MHZ的RF的频率读入器，被覆盖并分开提供一个847KHZ的接口时钟信号。在RF接口一侧，数据被以847KHZ的频率发射接受。在微控制器一侧，采用异步的四相位数据包协议（8位数据，请求和应答信号），用于控制QDI异步微控制器的数据传输。这个接口执行两种转变：协议转变和连续/并行或平行/连续之间的转变。它被设置成一个异步有限状态的机器，假定抽样异步控制信号是象P5rep和P4ack一样的。当有数据从卡读入时，微控制器禁止请求由P5rep信号控制的写入接口信号。当字节缓冲器无内容时，四相信号交换协议完成两个返0相位。当从读卡器接收数据时，REN信号被置为高电平，微控制器准备响应P4ack信号，接收一个输入字节。当接收器接收到一个有效的数据时，接口应答上升的P4req信号。归零的握手相位完成。握手协议确保微控制器和接口都能有效的传送和接收数据。因此，只要在接口没有授权微控制器的请求时，微控制器将保持空闲。当有数据再次传送或者接收时，程序将再次执行。1字节的数据缓冲器使微控制器和接口能正确运行。当微控制器没有及时读取输入数据时才会产生错误，在这种情况下接口将重写未读的比特。这种信息交流失败可以用软件校错改变。C.QDI8位异步微控制器QDI8位异步微控制器是一个采用CSIC指令集的微型处理器。（如图6）为了使C语言编译简单和限制记忆体访问，我们决定综合两个不同的寄存器文件，一个是8位寄存器用于存储数据，一个是16位寄存器用于指针（包括程序计数器和堆栈指针）。特殊算术单元联合每个寄存器单元，允许并发的数据计算和寻址。一个专门的单元用于管理Z,N,V状态位,外部单元也包括在内，支持六个8位的并行接口（一个输入，四个输出，一个双向控制可擦写存储器以及同步/异步接口），还支持四个串行连接（使用两个延迟协议协调高性能RISC异步处理器）。此外，微处理器集成了16KB的RAM和2KB的ROM。ROM包含一个自测试程序，当系统复位时依照启动模式执行（八种模式可以使用）。它是一个350汇编指令程序，用以完成故障测试，确定信号写入，在并行端口汇报运行结果。QDI异步逻辑模块使用自测试，因为任何门的输入故障将使得握手停止。（不是过早开通）。结果，BIST程序将从不产生完整的信号。•命令