UC3843

© Semiconductor Components Industries, LLC, 2005 November, 2005 − Rev. 8 1 Publication Order Number: UC3842A/D UC3842A, UC3843A, UC2842A, UC2843A High Performance Current Mode Controllers The UC3842A, UC3843A series of high performance fixed frequency current mode controllers are specifically designed for off−line and DC−to−DC converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in an 8−pin dual−in−line plastic package as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage. The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally suited for off−line converters. The UCX843A is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). Features • Trimmed Oscillator Discharge Current for Precise Duty Cycle Control • Current Mode Operation to 500 kHz • Automatic Feed Forward Compensation • Latching PWM for Cycle−By−Cycle Current Limiting • Internally Trimmed Reference with Undervoltage Lockout • High Current Totem Pole Output • Undervoltage Lockout with Hysteresis • Low Startup and Operating Current • Direct Interface with ON Semiconductor SENSEFET™ Products • Pb−Free Packages are Available 14 SOIC−14 D SUFFIX CASE 751A 1 See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ORDERING INFORMATION See general marking information in the device marking section on page 16 of this data sheet. DEVICE MARKING INFORMATION 1 8 PDIP−8 N SUFFIX CASE 626 PIN CONNECTIONS (Top View) Vref (Top View) Compensation Voltage Feedback Current Sense RT/CT Vref VCC Output GND 1 2 3 4 5 6 7 8 Compensation NC Voltage Feedback NC Current Sense NC RT/CT NC VCC VC Output GND Power Ground 1 2 3 4 5 6 7 9 8 10 11 12 13 14 1 8 SOIC−8 D1 SUFFIX CASE 751 http://onsemi.com UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 2 Figure 1. Simplified Block Diagram 5.0V Reference Latching PWM VCC Undervoltage Lockout Oscillator Error Amplifier 7(12) VC 7(11) Output 6(10) Power Ground 5(8) 3(5) Current Sense Input Vref 8(14) 4(7) 2(3) 1(1) GND 5(9) RTCT Voltage Feedback Input R R + − Vref Undervoltage Lockout Output Compensation Pin numbers in parenthesis are for the D suffix SOIC−14 package. VCC MAXIMUM RATINGS Rating Symbol Value Unit Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC 30 V Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink (Note 1) IO 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 �J Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V Error Amp Output Sink Current IO 10 mA Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air N Suffix, Plastic Package Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Air PD R�JA PD R�JA 862 145 1.25 100 mW °C/W W °C/W Operating Junction Temperature TJ + 150 °C Operating Ambient Temperature UC3842A, UC3843A UC2842A, UC2843A TA 0 to + 70 − 25 to + 85 °C Storage Temperature Range Tstg − 65 to + 150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum Package power dissipation limits must be observed. UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 3 ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3], unless otherwise noted.) Characteristics Symbol UC284XA UC384XA UnitMin Typ Max Min Typ Max REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV Temperature Stability TS − 0.2 − − 0.2 − mV/°C Total Output Variation over Line, Load, Temperature Vref 4.9 − 5.1 4.82 − 5.18 V Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − �V Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV Output Short Circuit Current ISC − 30 − 85 − 180 − 30 − 85 − 180 mA OSCILLATOR SECTION Frequency TJ = 25°C TA = Tlow to Thigh fosc 47 46 52 − 57 60 47 46 52 − 57 60 kHz Frequency Change with Voltage (VCC = 12 V to 25 V) �fosc/�V − 0.2 1.0 − 0.2 1.0 % Frequency Change with Temperature TA = Tlow to Thigh �fosc/�T − 5.0 − − 5.0 − % Oscillator Voltage Swing (Peak−to−Peak) Vosc − 1.6 − − 1.6 − V Discharge Current (Vosc = 2.0 V) TJ = 25°C TA = Tlow to Thigh Idischg 7.5 7.2 8.4 − 9.3 9.5 7.5 7.2 8.4 − 9.3 9.5 mA ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V Input Bias Current (VFB = 2.7 V) IIB − −0.1 −1.0 − −0.1 −2.0 �A Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB Output Current Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V) ISink ISource 2.0 −0.5 12 −1.0 − − 2.0 −0.5 12 −1.0 − − mA Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) VOH VOL 5.0 − 6.2 0.8 − 1.1 5.0 − 6.2 0.8 − 1.1 V 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842A, UC3843A Thigh = +70°C for UC3842A, UC3843A −25°C for UC2842A, UC2843A +85°C for UC2842A, UC2843A UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 4], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 5], unless otherwise noted.) UC284XA UC384XA Characteristics Symbol Min Typ Max Min Typ Max Unit CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 6 & 7) AV 2.85 3.0 3.15 2.85 3.0 3.15 V/V Maximum Current Sense Input Threshold (Note 6) Vth 0.9 1.0 1.1 0.9 1.0 1.1 V Power Supply Rejection Ratio VCC = 12 to 25 V (Note 6) PSRR − 70 − − 70 − dB Input Bias Current IIB − −2.0 −10 − −2.0 −10 �A Propagation Delay (Current Sense Input to Output) tPLH(in/out) − 150 300 − 150 300 ns OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) Low State (ISink = 200 mA) High State (ISink = 20 mA) High State (ISink = 200 mA) VOL VOH − − 13 12 0.1 1.6 13.5 13.4 0.4 2.2 − − − − 13 12 0.1 1.6 13.5 13.4 0.4 2.2 − − V Output Voltage with UVLO Activated VCC = 6.0 V, ISink = 1.0 mA VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns UNDERVOLTAGE LOCKOUT SECTION Startup Threshold UCX842A UCX843A Vth 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 V Minimum Operating Voltage After Turn−On UCX842A UCX843A VCC(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 V PWM SECTION Duty Cycle Maximum Minimum DCmax DCmin 94 − 96 − − 0 94 − 96 − − 0 % TOTAL DEVICE Power Supply Current (Note 4) Startup: (VCC = 6.5 V for UCX843A, (VCC = 14 V for UCX842A) Operating ICC − − 0.5 12 1.0 17 − − 0.5 12 1.0 17 mA Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V 4. Adjust VCC above the Startup threshold before setting to 15 V. 5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842A, UC3843A Thigh = +70°C for UC3842A, UC3843A −25°C for UC2842A, UC2843A +85°C for UC2842A, UC2843A 6. This parameter is measured at the latch trip point with VFB = 0 V. 7. Comparator gain is defined as: AV �V Output Compensation �V Current Sense Input UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 5 R T Ω , T IM IN G R E S IS T O R ( k ) Figure 2. Timing Resistor versus Oscillator Frequency Figure 3. Output Deadtime versus Oscillator Frequency Figure 4. Oscillator Discharge Current versus Temperature Figure 5. Maximum Output Duty Cycle versus Timing Resistor Figure 6. Error Amp Small Signal Transient Response Figure 7. Error Amp Large Signal Transient Response 0.5 �s/DIV 20 m V /D IV VCC = 15 V AV = −1.0 TA = 25°C 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M fOSC, OSCILLATOR FREQUENCY (Hz) VCC = 15 V TA = 25°C 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M fOSC, OSCILLATOR FREQUENCY (Hz) % D T, P E R C E N T O U T P U T D E A D T IM E VCC = 15 V TA = 25°C −55 −25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) , D IS C H A R G E C U R R E N T ( m A ) di sc hg I VCC = 15 V VOSC = 2.0 V RT, TIMING RESISTOR (�) 800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k , M A X IM U M O U T P U T D U T Y C Y C LE ( % ) m ax D VCC = 15 V CT = 3.3 nF TA = 25°C Idischg = 9.5 mA Idischg = 7.2 mA 2.55 V 2.5 V 2.45 V VCC = 15 V AV = −1.0 TA = 25°C 0.1 �s/DIV 20 0 m V /D IV 2.5 V 3.0 V 2.0 V 80 50 20 8.0 5.0 2.0 0.8 100 50 20 10 5.0 2.0 1.0 9.0 8.5 8.0 7.5 7.0 100 90 80 70 60 50 40 UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 6 Figure 8. Error Amp Open Loop Gain and Phase versus Frequency Figure 9. Current Sense Input Threshold versus Error Amp Output Voltage Figure 10. Reference Voltage Change versus Source Current Figure 11. Reference Short Circuit Current versus Temperature Figure 12. Reference Load Regulation Figure 13. Reference Line Regulation Δ , O U T P U T V O LT A G E C H A N G E ( 2. 0 m V /D IV ) O 2.0 ms/DIV V Δ , O U T P U T V O LT A G E C H A N G E ( 2. 0 m V /D IV ) O 2.0 ms/DIV V VCC = 12 V to 25 V TA = 25°C Δ , R E F E R E N C E V O LT A G E C H A N G E ( m V ) re f 0 20 40 60 80 100 120 Iref, REFERENCE SOURCE CURRENT (mA) V VCC = 15 V TA = 55°C TA = 125°C , R E F E R E N C E S H O R T C IR C U IT C U R R E N T ( m A ) S C −55 −25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) VCC = 15 V RL ≤ 0.1 � I VCC = 15 V IO = 1.0 mA to 20 mA TA = 25°C 0 −4.0 −8.0 −12 −16 −20 −24 110 90 70 50 TA = 25°C −�20 A V O L , O P E N L O O P V O LT A G E G A IN ( dB ) 10 M10 f, FREQUENCY (Hz) Gain Phase VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 K TA = 25°C 0 30 60 90 120 150 180 100 1.0 k 10 k 100 k 1.0 M 0 20 40 60 80 100 , E X C E S S P H A S E ( D E G R E E S ) φ 0 VO, ERROR AMP OUTPUT VOLTAGE (V) 0 , C U R R E N T S E N S E I N P U T T H R E S H O LD ( V V t h 0.2 0.4 0.6 0.8 1.0 1.2 2.0 4.0 6.0 8.0 VCC = 15 V TA = 25°C TA = −55°C TA = 125°C UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 7 Figure 14. Output Saturation Voltage versus Load Current Figure 15. Output Waveform Figure 16. Output Cross Conduction Figure 17. Supply Current versus Supply Voltage 50 ns/DIV VCC = 15 V CL = 1.0 nF TA = 25°C 100 ns/DIV VCC = 30 V CL = 15 pF TA = 25°C , S U P P LY C U R R E N T 10 0 m A /D IV 20 V /D IV I , O U T P U T V O LT A G E V C C O 8006004002000 IO, OUTPUT LOAD CURRENT (mA) , O U T P U T S A T U R A T IO N V O LT A G E ( V ) sa t V VCC TA = 25°C TA = −55°C GND TA = 25°C Source Saturation (Load to Ground) TA = −55°C VCC = 15 V 80 �s Pulsed Load 120 Hz Rate 0 10 20 30 40 , S U P P LY C U R R E N T ( m A ) C C VCC , SUPPLY VOLTAGE I RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 25°CU C X 84 3A U C X 84 2A 90% 10% 0 1.0 2.0 3.0 −2.0 −1.0 0 25 20 15 10 5 0 Sink Saturation (Load to VCC) UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 8 + − Sink Only Positive True Logic = RS + Internal Bias Reference Regulator Oscillator S R Q − Vref UVLO 3.6V 36V VCC 7(12) Q1 VinVCC VC 7(11) 6(10) 5(8) 3(5) + 1.0mA Error Amplifier 1(1) 2(3) 4(7) 8(14) 5(9)GND Output Compensation Voltage Feedback Input RT CT Vref − − PWM Latch Current Sense Comparator R R Power Ground Current Sense Input 2R R 1.0V Pin numbers in parenthesis are for the D suffix SOIC−14 package. QT + − + + − + − + VCC UVLO Output 2.5V Figure 18. Representative Block Diagram Output/ Compensation Current Sense Input Latch ‘‘Reset’’ Input Output Capacitor CT Latch ‘‘Set’’ Input Large RT/Small CT Small RT/Large CT Figure 19. Timing Diagram UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 9 OPERATING DESCRIPTION The UC3842A, UC3843A series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off−Line and DC−to−DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 18. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates and internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at TJ = 25°C. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 4 and 5. In many noise sensitive applications it may be desirable to frequency−lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 21. For reliable locking, the free−running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 22. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 8). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is −2.0 �A which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 31). The output voltage is offset by two diode drops (≈ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft−start interval (Figures 24, 25). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level: Rf(min) ≈ 3.0 (1.0 V) + 1.4 V 0.5 mA = 8800 � Current Sense Comparator and PWM Latch The UC3842A, UC3843A operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle−by−cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: Ipk = V(Pin 1) − 1.4 V 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 23. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 27. UC3842A, UC3843A, UC2842A, UC2843A http://onsemi.com 10 PIN FUNCTION DESCRIPTION Pin Function Description8−Pin 14−Pin 1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation. 2 3 Voltage Feedback This is the inverting input of the Error Amplifier. It is normally connected to the switching pow- er supply output through a resistor divider. 3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this infor- mation to terminate the output switch conduction. 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. 5 − GND This pin is the combined control circuitry and power ground (8−pin package only). 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. − 8 Power Ground This pin is a separate power ground return (14−pin package only) that is connected b