IPC-9252

IPC-9252A Requirements for Electrical Testing of Unpopulated Printed Boards November 2008 Supersedes IPC-9252 February 2001 A standard developed by IPC ® Association Connecting Electronics Industries The Principles of Standardization In May 1995 the IPC’s Technical Activities Executive Committee (TAEC) adopted Principles of Standardization as a guiding principle of IPC’s standardization efforts. Standards Should: • Show relationship to Design for Manufacturability (DFM) and Design for the Environment (DFE) • Minimize time to market • Contain simple (simplified) language • Just include spec information • Focus on end product performance • Include a feedback system on use and problems for future improvement Standards Should Not: • Inhibit innovation • Increase time-to-market • Keep people out • Increase cycle time • Tell you how to make something • Contain anything that cannot be defended with data Notice IPC Standards and Publications are designed to serve the public interest through eliminating mis- understandings between manufacturers and purchasers, facilitating interchangeability and improve- ment of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of IPC from manufacturing or selling products not conforming to such Standards and Publication, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than IPC members, whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by IPC without regard to whether their adop- tion may involve patents on articles, materials, or processes. By such action, IPC does not assume any liability to any patent owner, nor do they assume any obligation whatever to parties adopting the Recommended Standard or Publication. Users are also wholly responsible for protecting them- selves against all claims of liabilities for patent infringement. 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All rights reserved under both international and Pan-American copyright conventions. Any copying, scanning or other reproduction of these materials without the prior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copyright Law of the United States. IPC-9252A Requirements for Electrical Testing of Unpopulated Printed Boards Developed by the Electrical Continuity Testing Task Group (7-32c) of the Product Assurance Committee (7-30) of IPC Users of this publication are encouraged to participate in the development of future revisions. Contact: IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249 Tel 847 615.7100 Fax 847 615.7105 Supersedes: IPC-9252 - February 2001 IPC-ET-652A - October 1990 ® This Page Intentionally Left Blank Acknowledgment Any publication involving a complex technology draws material from a vast number of sources. While the principal mem- bers of the Electrical Continuity Testing Task Group (7-32c) of the Product Assurance Committee (7-30) are shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them, the members of the IPC extend their gratitude. Product Assurance Committee Electrical Continuity Testing Task Group Technical Liaisons of the IPC Board of Directors Chair Mel Parrish STI Electronics Vice-Chair Michael E. Hill Colonial Circuits Inc. Chair Michael E. Hill Colonial Circuits Inc. Peter Bigelow IMI Inc. Sammy Yi Flextronics International Electrical Continuity Testing Task Group Wendi Boger, DDi Corp. Thomas Bresnan, R & D Circuits Jeffrey Ciesla, Defense Supply Center Columbus Craig Coffman, Everett Charles Technologies-ECT David Corbett, Defense Supply Center Columbus C. Don Dupriest, Lockheed Martin Missiles and Fire Control Alan Exley, Raytheon Company Guy Ferraro, Beamind Michael Green, Lockheed Martin Space Systems Company Philip Henault, Raytheon Company Rick Kaim, USA Microcraft Christopher Katzko, Shanghai Meadville Electronics Co. Ltd Klaus Koziol, Mania Technologie (USA) Inc. Clifford Maddox, Boeing Company Kenneth Manning, Raytheon Company Matt McQueen, Naval Surface Warface Center Crane Roger Miedico, Raytheon Company Michael Paddack, Boeing Company Viktor Romanov, ATG Test Systems GmbH Lowell Sherman, Defense Supply Center Columbus Adelino Sousa, MicroCraft, Inc. Gordon Sullivan, Huntsman Advanced Technology Center David Wilkie, Everett Charles Technologies November 2008 IPC-9252A iii This Page Intentionally Left Blank IPC-9252A November 2008 iv Table of Contents 1 SCOPE......................................................................... 1 1.1 Purpose .................................................................... 1 1.2 Introduction.............................................................. 1 1.3 Selection of the Proper Test Level ......................... 1 2 APPLICABLE DOCUMENTS ...................................... 2 2.1 IPC .......................................................................... 2 2.2 International Organization for Standardization (ISO) ....................................................................... 2 2.3 American National Standards Institute (ANSI) .... 2 3 TERMS AND DEFINITIONS ........................................ 2 3.1 AABUS (As Agreed Between User and Supplier) ........................................................... 2 3.2 Adjacency Terms .................................................... 2 3.2.1 Adjacency ................................................................ 2 3.2.2 Adjacency Distance ................................................. 2 3.2.3 Horizontal Adjacency Distance............................... 3 3.2.4 Vertical Layer Adjacency ........................................ 3 3.3 Analyzer................................................................... 4 3.4 Computer Automated Design/Manufacturing (CAD/CAM) Net List ............................................. 4 3.5 Contamination.......................................................... 4 3.6 End Points/Midpoints .............................................. 4 3.7 Moving (Flying) Probe............................................ 4 3.8 Guide Plate Fixture ................................................. 5 3.9 Impedance Testing................................................... 5 3.10 Indirect Test by Signature Comparison .................. 5 3.11 Isolation Resistance ................................................. 5 3.12 Leakage.................................................................... 5 3.13 Plated Hole .............................................................. 5 3.14 Populated Board ...................................................... 5 3.15 Resistance Measuring Method ................................ 5 3.16 Time Domain Reflectometer (TDR) ....................... 5 4 TEST METHODOLOGIES .......................................... 5 4.1 Continuity Test ........................................................ 5 4.1.1 Resistive Continuity Testing ................................... 5 4.1.2 Indirect Continuity Testing by Signature Comparison.............................................................. 6 4.2 Isolation Testing ...................................................... 6 4.2.1 Resistive Isolation Testing ...................................... 6 4.2.2 Indirect Isolation Testing by Signature Comparison ............................................. 6 4.3 Test Parameter Matrix ............................................. 6 4.4 Tests Other than Continuity and Isolation.............. 6 4.5 Verification (Retesting)............................................ 6 5 TEST PROGRAM GENERATION .............................. 6 5.1 Source Data ............................................................ 7 5.1.1 CAM Data Test........................................................ 7 5.1.2 CAD Data Test ........................................................ 7 6 ELECTRICAL TEST CERTIFICATION AND TRACEABILITY .......................................................... 7 6.1 Certificate of Conformance (C of C)...................... 7 6.1.1 Example of a Test Certificate of Conformance (C of C) ............................................ 7 6.2 Marking and Traceability ........................................ 7 APPENDIX A Other Tests and Considerations .......... 8 Figures Figure 1-1 Automatic Test Equipment (ATE) Selection Criteria ............................................................... 1 Figure 3-1 Adjacency .......................................................... 2 Figure 3-2 Adjacency Distance Example ............................ 2 Figure 3-3 Horizontal Layer Adjacency ............................... 3 Figure 3-4 Line of Sight Adjacency ..................................... 3 Figure 3-5 Vertical Layer Adjacency ................................... 4 Figure 3-6 Test for Midpoint Classification.......................... 4 Figure 4-1 Resistive Continuity Test.................................... 5 Figure 4-2 Resistive Continuity Test.................................... 6 Tables Table 4-1 Requirements by Test Level................................. 5 November 2008 IPC-9252A v This Page Intentionally Left Blank IPC-9252A November 2008 vi Requirements for Electrical Testing of Unpopulated Printed Boards 1 SCOPE This document is intended to assist in selecting the test analyzer, test parameters, test data, and fixturing required to perform electrical test(s) on all unpopulated printed boards (PBs). The testing of PBs with embedded components (e.g., resis- tors, capacitors, etc.) is not addressed in this document revision. 1.1 Purpose Electrical testing verifies that the conduc- tive networks on the PBs are interconnected according to the design requirements. Electrical test does not ensure that the PB can be assembled or that the PB meets all of the customer’s requirements. Many physical characteristics of the conduc- tors (dimensional accuracy, solder mask, conductor geom- etry and nomenclature registration, presence of holes, etc.) can’t be determined by electrical test. Other checks should be employed to confirm these characteristics. 1.2 Introduction Electrical testing of PBs ensures that the PB conforms to the electrical design requirements. This document defines different levels of testing available in- order to achieve this purpose. In selecting the appropriate test level, technology, equipment, and associated fixturing, a suitable compromise between productivity, features, and costs can be found. The costs associated with electrical testing can vary dra- matically. Costs alone, however, should never be the only criteria for selecting the appropriate test level and equip- ment. As shown in Figure 1-1, many other important areas require consideration. For example, spacing and density of a PB design may be of paramount importance to one user, while another may be concerned with testing parameters and service reliability. A careful examination of all areas of concern and how they may affect each other, not just how they perform individually, is therefore significant. What- ever the selection criteria may be, qualifying ‘‘bench- marks’’ should be performed on known product. 1.3 Selection of the Proper Test Level All testing levels (see Table 4-1) defined in this document are intended to check electrical functionality of the design. However, the test level specified will affect test comprehensiveness. For example, when selecting test voltages and resistances for the PB, the user must take into account both the final appli- cation of the PB and the level of defect analysis needed to IPC-9252a-1-1 Figure 1-1 Automatic Test Equipment (ATE) Selection Criteria ATE PURCHASING CONTINGENCIES DIAGNOSTICS COST MAINTENANCE FAULT LOCALIZATION FUTURE APPLICATIONS DENSITY CAPABILITIES DOCUMENTATION SUPPORT SERVICES PRODUCT THROUGHPUT FIXTURING PROGRAMMING ELECTRICAL PARAMETERS November 2008 IPC-9252A 1 ensure acceptable product. Electrical testing parameters that allow high productivity could also allow higher defect escape rates. It is the responsibility of the user to select the test level desired. If nothing is specified, IPC Class 1, Class 2, and Class 3 will be tested to Level A, B, and C respectively. The user shall determine the test parameters to test for continuity (open), isolation (leakage/short), and other spe- cial characteristics (i.e., impedance, hi-pot, capacitance, current carrying capacity, etc.) that will satisfactorily evalu- ate the critical electrical characteristics of specific PBs. 2 APPLICABLE DOCUMENTS The following documents, of the issue currently in effect, are applicable to the extent specified herein. 2.1 IPC1 IPC-T-50 Terms and Definitions for Interconnecting and Packaging Electronic Circuits IPC-D-356 Bare Board Electrical Test Information in Digi- tal Form IPC-TM-650 Test Methods Manual2 2.5.5.7 Characteristic Impedance and Time Delay of Lines on Printed boards by TDR 2.5.7 Dielectric Withstanding Voltage, PWB IPC-2221 Generic Standard on Printed Board Design IPC-6011 Generic Performance Specification for Printed Boards 2.2 International Organization for Standardization (ISO)3 ISO 10012 Measurement Management Systems - Require- ments for Measurement Processes and Measuring Equip- ment 2.3 American National Standards Institute (ANSI)4 ANSI/NCSL Z540.3 Requirements for the Calibration of Measuring and Test Equipment 3 TERMS AND DEFINITIONS The definitions of terms used herein shall be in accordance with IPC-T-50 and in 3.1 through 3.16. 3.1 AABUS (As Agreed Between User and Supplier) Indicates additional or alternate requirements to be decided between the user and the supplier in the procurement docu- mentation. Examples include contractual requirements, modifications to purchase documentation and information on the drawing. Agreements can be used to define test methods, conditions, frequencies, categories or acceptance criteria within a test, if not already established. 3.2 Adjacency Terms 3.2.1 Adjacency An optional process to identify nets for isolation testing based on distance, which will reduce test time (see Figure 3-1). 3.2.2 Adjacency Distance The distance between two nets used to determine which nets are tested for isolation (see Figure 3-2). If vertical layer adjacency is required, it shall be defined and may be different than horizontal adja- cency distance. Adjacency distance is measured between features, edge to edge. 1. www.ipc.org 2. Current and revised IPC Test Methods are available on the IPC Web site (www.ipc.org/html/testmethods.htm) 3. www.iso.org 4. www.ansi.org IPC-9252a-3-1 Figure 3-1 Adjacency IPC-9252a-3-2 Figure 3-2 Adjacency Distance Example 1. 1.27 mm [0.050 in] 2. Where horizontal adjacency distance is shown as 1.27 mm [0.050 in], C is tested to B, D, and E, but not to A 1 1 A B C D E IPC-9252A November 2008 2 3.2.3 Horizontal Adjacency Distance The distance between two nets on any single layer used to determine which nets are tested for isolation (see Figure 3-3.) Also referred to as Planar 2D Adjacency (Adjacency applied to a two dimensional surface). 3.2.3.1 Line of Sight Adjacency A subset of all nets within the horizontal adjacency distance on any single layer that are identified for isolation testing. This method tests nets that lie within the line of sight of each other. That is, there are no other nets lying between them. The nets must also lie within the horizontal adjacency distance of each other. In Figure 3-4, adjacency is being shown for the black line’s net (C). The Crosshatch traces (B and D) are found to be adjacent because they lie completely or par- tially within the line of sight of the black line (C). The solid gray-shaded traces (A & E) are not found to be adja- cent because another net blocks the line of sight. 3.2.4 Vertical Layer Adjacency Identified nets from the layers above and below the specified net to be included in the isolation test. Each net from one layer above and one layer below is considered as if it was on the same layer as the specified net and is included in the vertical layer adja- cency list if it lies within the vertical layer adjacency dis- tance. This distance can be different than the horizontal layer adjacency distance (see Figure 3-5 which illustrates the vertical layer adjacency rule). Also referred to as Layer to Layer, Z-axis, or 3-D Adjacency. IPC-9252a-3-3 Figure 3-3 Horizontal Layer Adjacency 1. Segmented Ground/Layer 2 2. Adjacency Limit is from Edge of D-L3 Conductor 3. Adjacency Rules: D-L3 is tested to C-L3, E-L3, and F-L3 D-L3 is not tested to G-L3, A-L2, B-L2, or to segmented ground/L2 B-L2 is tested against A-L2, G-L3, and to segmented ground/L2 B-L2 is not tested against C-L3, D-L3, E-L3, or F-L3 1 2 A-L2 B-L2 C-L3 E-L3 F-L3 G-L3 D-L3 IPC-9252a-3-4 Figure 3-4 Line of Sight Adjacency 1. 1.27 mm [0.050 in] 2. Where line of sight adjacency distance is shown as 1.27 mm [0.050 in], C is tested to B and D, but not to A or E. 3. A short from C to E should also be reported as a C to D and a D to E short. 1 1 A B C D E November 2008 IPC-9252A 3 3.3 Analyzer An instrument designed to examine the functions of circuits, components, or test points and their relationships with each other. 3.4 Computer Automated Design/Manufacturing (CAD/ CAM) Net List A net list derived from the design layout system and traceable to the schematic. 3.5 Contamination Foreign metallic and nonmetallic materials between circuits, traces, and lands, which may cause shorts/leakage between the conductors. Alternatively, it may be resistive foreign material on conductors that could cause an electrical test to fail because of high resis- tance. 3.6 End Points/Mid