HEF4011UB与非门

DATA SHEET Product specification File under Integrated Circuits, IC04 January 1995 INTEGRATED CIRCUITS HEF4011UB gates Quadruple 2-input NAND gate For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 查询HEF4011UB供应商 January 1995 2 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates DESCRIPTION The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. Fig.1 Functional diagram. HEF4011UBP(N): 14-lead DIL; plastic (SOT27-1) HEF4011UBD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4011UBT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages Fig.3 Schematic diagram (one gate). The splitting-up of the n-transistors provide identical inputs. January 1995 3 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays In → On 5 60 120 ns 25 ns + (0,70 ns/pF) CL HIGH to LOW 10 tPHL 25 50 ns 12 ns + (0,27 ns/pF) CL 15 20 40 ns 10 ns + (0,20 ns/pF) CL 5 35 70 ns 8 ns + (0,55 ns/pF) CL LOW to HIGH 10 tPLH 20 40 ns 9 ns + (0,23 ns/pF) CL 15 17 35 ns 9 ns + (0,16 ns/pF) CL Output transition 5 75 150 ns 15 ns + (1,20 ns/pF) CL times 10 tTHL 30 60 ns 6 ns + (0,48 ns/pF) CL HIGH to LOW 15 20 40 ns 4 ns + (0,32 ns/pF) CL 5 60 110 ns 10 ns + (1,00 ns/pF) CL LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL Input capacitance CIN 10 pF VDD V TYPICAL FORMULA FOR P (µW) Dynamic power 5 500 fi + ∑ (foCL) × VDD2 where dissipation per 10 5 000 fi + ∑ (foCL) × VDD2 fi = input freq. (MHz) package (P) 15 25 000 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates Fig.4 Typical transfer characteristics; one input, the other input connected to VDD;  VO; − − − ID (drain current); IO = 0; VDD = 5 V. Fig.5 Typical transfer characteristics; one input, the other input connected to VDD;  VO; − − − ID (drain current); IO = 0; VDD = 10 V. Fig.6 Typical transfer characteristics; one input, the other input connected to VDD;  VO; − − − ID (drain current); IO = 0; VDD = 15 V. January 1995 5 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates Fig.7 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.8). Fig.8 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C. A : average, B : average + 2 s, C : average − 2 s, where ‘s’ is the observed standard deviation. January 1995 6 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates APPLICATION INFORMATION Some examples of applications for the HEF4011UB are shown below. Because of the fact that this circuit is unbuffered, it is suitable for use in (partly) analogue circuits. Fig.9 (a) Astable relaxation oscillator using two HEF4011UB gates; the diodes may be BAW62; C2 is a parasitic capacitance. (b) Waveforms at the points marked A, B, C and D in the circuit diagram. INH O L H H OSC In Fig.9 the oscillation frequency is mainly determined by R1C1, provided R1 << R2 and R2C2 << R1C1. The function of R2 is to minimize the influence of the forward voltage across the protection diodes on the frequency; C2 is a stray (parasitic) capacitance. The period Tp is given by Tp = T1 + T2, in which VST is the signal threshold level of the gate. The period is fairly independent of VDD, VST and temperature. The duty factor, however, is influenced by VST. T1 R1C1 In VDD VST+ VST ---------------------------and T2 R1C1 In 2VDD VST– VDD VST– ------------------------------- where= = January 1995 7 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates Fig.10 Example of a crystal oscillator using one HEF4011UB gate. INH O L H H OSC Fig.11 Output voltage as a function of supply voltage. NOTES If a gate is just used as an amplifying inverter, there are two possibilities: • Connecting the inputs together gives simpler wiring, but makes the device output not completely symmetrical. • Connecting one input to VDD will give the device a symmetrical output. Fig.12 Test set-up for measuring graph of Fig.11. Condition: all other inputs connected to ground. January 1995 8 Philips Semiconductors Product specification Quadruple 2-input NAND gate HEF4011UBgates Fig.13 Voltage gain (VO/VI) as a function of supply voltage. Fig.14 Supply current as a function of supply voltage. Fig.15 Test set-up for measuring graphs of Figs 13 and 14. Condition: all other inputs connected to ground. Fig.16 Example of an analogue amplifier with inhibit using one HEF4011UB gate.