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一维纳米半导体材料及其电子与光子器件研究

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一维纳米半导体材料及其电子与光子器件研究一维纳米半导体材料及其电子与光子器件研究 论文中英文摘要 作者姓名:马仁敏 论文题目:一维纳米半导体材料及其电子与光子器件研究 作者简介:马仁敏,男,1982年12月出生。2004年7月毕业于北京科技大学,获得学士学位。2009年7月毕业于北京大学,获博士学位。指导教师:戴伦教授。 中 文 摘 要 CdS是一种非常重要的半导体材料,其纳米结构在纳电子器件和光子器件等领域有着广泛的应用。本论文以CdS为代表,通过实验考察与理论分析,深入地研究了一维纳米材料的可控生长和掺杂、高性能纳电子器件的设计与性能提高...

一维纳米半导体材料及其电子与光子器件研究
一维纳米半导体材料及其电子与光子器件研究 论文中英文摘要 作者姓名:马仁敏 论文题目:一维纳米半导体材料及其电子与光子器件研究 作者简介:马仁敏,男,1982年12月出生。2004年7月毕业于北京科技大学,获得学士学位。2009年7月毕业于北京大学,获博士学位。指导教师:戴伦教授。 中 文 摘 要 CdS是一种非常重要的半导体材料,其纳米结构在纳电子器件和光子器件等领域有着广泛的应用。本论文以CdS为代 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf ,通过实验考察与理论分析,深入地研究了一维纳米材料的可控生长和掺杂、高性能纳电子器件的设计与性能提高、纳米线/硅异质结高效率电致发光和纳米线耦合微腔的光学特性等。主要创新成果如下: 1. 利用气相金属铟对CdS纳米线(带)进行原位掺杂并对其结构、光学和电学性质进行了表征。结果显示生长的CdS纳米线(带)具有单晶结构和优异的光学性质,其荧光谱只有半高宽仅为11纳米的带边峰,没有缺陷发光峰;电学表征结果显示In作为浅施主已成功掺入到 4CdS纳米线(带)中,其电阻率可由未掺杂的10 Ω•cm降低到约3.72 Ω•cm,而且通过控制In 源的含量,可以进一步调控CdS 纳米线(带)中的电子浓度。掺杂样品载流子迁移率约为~100-350 22cm/V•s,非常接近体单晶CdS材料的电子迁移率340 cm/V•s。 2. 采用Si (111)衬底生长出平行于衬底的CdS纳米线网络。提出了异质外延和同质外延两步法的生长机制。在理解该生长机制的基础上,使用解理的正三角形Si (111) 衬底,生长出的CdS纳米线六个对称的生长方向与正三角形的Si (111)衬底的三条边对应垂直, 从而实现了宏观取向可预定的纳米线网络的生长。光学表征显示该纳米线网络具有非常高的晶体以及光学质量。利用安装在扫描电镜中的纳米探针对纳米网络的电学性质进行了研究。实验发现纳米线交叉处的节点提供了很好的电学接触,显示出纳米线网络在集成光电子器件中潜在的应用价值。 16-33. 通过控制CdS纳米带中的电子浓度到约5×10 cm, 并选择合适的金属电极,在同一根 CdS纳米带上同时实现了良好的欧姆接触和肖特基接触,在此基础上研制成功高性能 8Au/CdS纳米带肖特基二极管。该二极管具有接近于1的理想因子(~1.14)、极高的整流比(>10)、 –5-2,极小的反向漏电流密度(<3.010 A,cm, ,10V偏压下)和很高的反向击穿电压(>,40 V)。这些二极管重要指标在已报道的各种一维纳米材料二极管中处于国际最高水平。 4. 首次报道了CdS纳米带金属-半导体场效应晶体管(MESFET)。相对于纳米线(带) 金属-绝缘体-半导体场效应晶体管(MOSFET)而言,纳米线(带)MESFET不需要栅极绝缘介质,从 而使其制备工艺简化、成本降低,更为重要的是其栅极与沟道之间有更好的电容耦合,使该器件可以有更大的电压和功率增益。所制备的CdS纳米带MESFET的开关比、阈值电压、跨导、亚阈值摆幅等晶体管重要指标在已报道的纳米场效应晶体管中处于国际最高水平。 5. 增强型晶体管具有高速低功耗的特点,在现在的微电子工艺中被广泛采用。但纳米线(带)基的增强型晶体管在制备上却很困难。本文作者首次实现了低功耗增强型纳米线MESFET,并将该方法推广到其它纳米材料上。 6. 首次提出带有附加肖特基接触的纳米线(带)MOSFET新结构器件,并从实验上证明利用附加的肖特基势垒产生的沟道窄化效应可以使CdS纳米线(带)MOSFET阈值电压大幅减小,跨导大幅增加。随后又与本组其他同学合作将这一方法推广到其它纳米材料上,实现了背栅n沟道ZnO纳米线和p沟道ZnP纳米线增强型MOSFET。这些低阈值电压、高跨导的32 纳米线(带)晶体管有助于实现低电压、高增益纳米线逻辑电路。 7. 首次在单根纳米线上构建了基于MESFET的n沟道金属-半导体(NMES)反相器。首先 7在单根纳米线上构建两个高性能的MESFET,此种纳米线晶体管具有高开关比(~10), 小阈值电压(~ ,0.4V),达到了理论极限的亚阈值摆幅(60 mV/dec)。然后利用这两个晶体管构建了高性能的NMES反相器,与构建在纳米线MOSFET上的反相器相比,这种类型的反相器具有更高的电压增益,且不需要绝缘层,制备工艺简单。制备的反相器具有高达83的电压增益,为报道时一维纳米材料反相器最高的增益值。在此基础上还构建了纳米线“与非”门,“或非”门逻辑电路。 8. 制备成功纳米线互补型金属-半导体(CMES)反相器。利用电场排布的方法在单根n型CdS纳米线旁边排列单根p型ZnP纳米线,制备成功了CMES纳米线反相器。在供给电压32 为0.5 V时,该反相器操作电压约为1.5 V、电压增益为10、静态功耗低至0.025 nW。还利用带有附加肖特基接触的新型纳米线MOSFET制备了互补型金属-绝缘体-半导体(CMOS)反相器。由于顶肖特基接触大幅降低了n沟道和p沟道纳米线MOSFETs的阈值电压,使其操作电压从原先大于10 V,降低到3 V左右。在供给电压为1 V时,该反相器操作电压约为2.5 V、电压增益为13、静态功耗低至0.015 nW。 9. 研究了CdS纳米带/Si异质结电致发光。当加一定的正向偏压时,其电致发光肉眼可见。观测到的电致发光谱与单根CdS纳米带的光致发光谱相似:只有半高宽仅11纳米的CdS带边峰,没有杂质峰。说明电致发光来源于电子、空穴(来自硅)在CdS纳米带中的辐射复合。随后,又与本组其他同学合作,与Harvard大学研究小组同时首次报道了单根ZnO纳米线/Si异质结电致发光。我们的电致发光谱中,ZnO紫外带边峰占主导地位。而他们的电致发光谱中,ZnO缺陷峰占主导地位。 10. 首次制备并研究了CdS纳米线微环腔。在此基础上,利用一根解理的直纳米线与微环腔耦合制备成功纳米线微环,法-布腔。实验发现直纳米线不但可以作为波导将环形微腔的光引出,而且可以调制环型微腔中的共振模式。 关键词:纳米,掺杂, 电子输运,场效应晶体管管,逻辑电路,异质结,光致发光,电致发光,微腔 Study of One-Dimensional Semiconductor Materials and Nano- Electronic & Photonic Devices Ma Ren-Min ABSTRACT CdS, with a direct band-gap of 2.4 eV at room temperature, is one of the most important group II-VI semiconductors and has been widely used in making optoelectronic and electronic devices. This thesis systemically investigates the synthesis and doping of one-dimensional semiconductor CdS materials and the fabrication of nano-electronic & photonic devices based on them. The main achievements are as follows: 1. Implemented an in-situ vapor doping method to obtain high conductivity and mobility CdS nanowires and nanobelts for the first time. The synthesized CdS nanowires and nanobelts are with single crystal structure. The photoluminescence spectra of them are dominated by an intense sharp band-edge emission with full width at half maximum of only about 11 nm, and free from deep-level defect emissions. The resistivity of the doped CdS nanowires and nanobelts is about 3.72 Ω•cm, 4much lower than 10 Ω•cm of the unintentionally doped CdS NBs , indicating that In atoms have been effectively doped into the CdS NBs as shallow donors. The electron mobility of CdS nanobelts 22is about ~100-350 cm/V,s, quite close to that of bulk CdS single crystal material (~340 cm/V,s). 2. Discovered that CdS nanowires can grow along the directions and form a network in a plane parallel to the Si (111) substrate. The growth mechanism of the nanowire network was suggested. In addition, the cleaved regular triangle Si (111) wafers were used as the substrates to synthesize the CdS nanowire networks with predictable directions. The observed free-exciton and bound-exciton emission peaks at 77 K show that the synthesized nanowires are with very high crystalline and optical quality. Electrical measurement results indicate that the nanowires in the networks have high electrical quality, and the current can flow through different NWs via the cross-junctions. 3. Realization of ideal ohmic and Schottky contacts with CdS nanowires and nanobelts. Based on this, I have fabricated high performance Au/CdS nanobelts Schottky diode. An on/off current 8–5-2,ratio is obtained to be greater than 10. The reverse current density is only about 3.010 A,cm even when the reverse bias approaches –10 V. The breakdown voltages of the CdS NB Schottky diodes are about –40 V. All of the above parameters are the best values reported for nanowire or nanobelts Schottky diodes so far. 4. Fabricated and studied and nano-MESFETs based on single CdS NBs for the first time. The single CdS nanobelt MESFETs exhibit n-channel normally-on mode and excellent performances, such as low threshold voltage (~–1.56 V), high transconductance (~3.5 μS), low subthreshold swing 8(~45 mV/dec), and the highest on/off current ratio (~210) for nano-field-effect-transistors when , reported. 5. Design and fabrication of enhancement-mode metal-semiconductor field-effect-transistors based on nanowire for the first time. Enhancement-mode field-effect-transistors, which do not have a conductive channel at zero gate voltage, have more advantage than depletion-mode FETs in high speed and low power consumption operation devices. However, they are usually more difficult to be implemented. I adopted a top surrounding Schottky gate, which has larger contact area with the CdS nanowire, to increase the gate depletion effect and pinch-off the channel at zero gate voltage to realize enhancement-mode nanowire metal-semiconductor field-effect-transistors. My method to realize enhancement-mode metal-semiconductor field-effect-transistors can be extended to other materials. Using this method, we have fabricated enhancement-mode metal-semiconductor field-effect-transistors based on other semiconductor nanowires. 6. Discovered that the Schottky barrier could be used to reduce the operating voltages and increase the transconductances of single CdS nanobelt MOSFETs. The mechanism is discussed. I have shown that the absolute value of threshold voltage for a metal-insulator-semiconductor field-effect-transistor made on a single CdS NB can be reduced from ~12.5 V to ~0.4 V, and its transconductance can be increased from ~0.2 μS to ~3.2 μS by adding an extra Au Schottky contact on the CdS NB. This method even could be used to realize enhancement-mode field-effect transistors and extended to other semiconductor materials. Using this method, my colleagues and I have fabricated enhancement-mode n-ZnO and p-ZnP nanowire metal-insulator-semiconductor 32 field-effect-transistors. 7. Demonstrated nanowire logic circuits based on MESFETs for the first time. High performance NMES inverter was constructed by combining two identical n-channel MESFETs made on single CdS nanowires. The inverter has a voltage gain as high as 83, which is the highest one for inverters made on one-dimensional nano-materials when reported. By assembling three identical NW MESFETs, NOR and NAND gates have been demonstrated. 8. Demonstrated the construction of CMES inverters with single n- and p-type nanowires on the same chip for the first time. A single p-type nanowire was assembled by the side of an n-type nanowire via the electric field assembly method. N- and p-channel MESFETs were fabricated with the n- and p-type nanowires, respectively. Based on this, the first high performance nanowire CMES inverter was built. I also fabricated and studied CMOS inverters based on Schottky barrier enhanced nanowire MOSFETs. 9. Fabricated the first silicon based nanowire light-emitting diodes in China. +Electroluminescence spectra of the n-CdS nanobelt/p-Si heterojunction are dominated by an intense sharp band-edge emission with full width at half maximum of only about 11 nm and free +from deep-level defect emissions. A few month later, single n-ZnO nanowire/p-Si heterojunction electroluminescence devices have also been fabricated by my colleagues and me. A sharp 382 nm ultraviolet electroluminescence from single ZnO nanowire is obtained. The EL intensity for both heterojunctions increases with the forward bias. Our results were reported simultaneously with that +of group in Harvard University. Compared to their results, the EL spectrum from ZnO nanowire/ p Si heterojunction is dominated by a UV peak. 10. Fabricated and studied CdS NW ring cavities for the first time. The rings with radii from 2.1 to 5.9 µm were fabricated by a nanoprobe system installed in a SEM. Radius dependent ring resonant modes were observed and confirmed. Further, a coupled R-F-P cavity was constructed by placing a straight NW by the side of a NW ring. The experiment results indicated that the straight NW not only served as a waveguide to couple the light out but also as a modulator to modulate resonant modes of the ring cavity. Such a coupled cavity is useful for the applications of nano photonic integrated circuits. Key words: Nanowires, Doping, Transport, Field-effect-transistor, Logic circuit, Heterojunction, Photoluminescence, Electroluminescence, Microcavity
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