ACPL-C79X

ACPL-C79B, ACPL-C79A, ACPL-C790 Precision Miniature Isolation Amplifiers Data Sheet CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Description The ACPL-C79B/C79A/C790 isolation amplifiers were designed for current and voltage sensing in electronic power converters in applications including motor drives and renewable energy systems. In a typical motor drive implementation, current flows through an external resistor and the resulting analog voltage drop is sensed by the isolation amplifier. A differential output voltage that is proportional to the current is created on the other side of the optical isolation barrier. For general applications, the ACPL-C79A (±1% gain tolerance) and the ACPL-C790 (±3% gain tolerance) are recommended. For high precision applications, the ACPL-C79B (±0.5% gain tolerance) can be used. The product operates from a single 5 V supply and provides excellent linearity and dynamic performance of 60 dB SNR. With 200 kHz bandwidth, 1.6 �s fast response time, the product captures transients in short circuit and overload conditions. The high common-mode transient immunity (15 kV/�s) of the ACPL-C79B/C79A/C790 provides the precision and stability needed to accurately monitor motor current in high noise motor control environments, providing for smoother control (less “torque ripple”) in various types of motor control applications. Combined with superior optical coupling technology, the ACPL-C79B/C79A/C790 implements sigma-delta (���) analog-to-digital converter, chopper stabilized ampli- fiers, and a fully differential circuit topology to provide unequaled isolation-mode noise rejection, low offset, high gain accuracy and stability. This performance is delivered in a compact, auto-insertable Stretched SO-8 (SSO-8) package that meets worldwide regulatory safety standards. Functional Diagram Features � ±0.5% High Gain Accuracy (ACPL-C79B) � –50 ppm/°C Low Gain Drift � 0.6 mV Input Offset Voltage � 0.05% Excellent Linearity � 60 dB SNR � 200 kHz Wide Bandwidth � 3 V to 5.5 V Wide Supply Range for Output Side � –40°C to +105°C Operating Temperature Range � Advanced Sigma-Delta (���) A/D Converter Technology � Fully Differential Isolation Amplifier � 15 kV/�s Common-Mode Transient Immunity � Compact, Auto-Insertable Stretched SO-8 Package � Safety and Regulatory Approvals (pending): – IEC/EN/DIN EN 60747-5-5: 1140 Vpeak working insulation voltage – UL 1577: 5000 Vrms/1min double protection rating – CSA: Component Acceptance Notice #5 Applications � Current/Voltage Sensing in AC and Servo Motor Drives � Solar Inverters, Wind Turbine Inverters � Industrial Process Control � Data acquisition systems � Switching Power Supply Signal Isolation � General Purpose Analog Signal Isolation � Traditional Current Transducer Replacements NOTE: A 0.1 �F bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. Figure 1. 1 2 3 4 8 7 6 5 IDD1 VDD1 VIN+ VIN- GND1 IDD2 VDD2 VOUT+ VOUT- GND2 + - + - SHIELD 2 Table 1. Pin Description Pin No. Symbol Description 1 VDD1 Supply voltage for input side (4.5 V to 5.5 V), relative to GND1 2 VIN+ Positive input (± 200 mV recommended) 3 VIN– Negative input (normally connected to GND1) 4 GND1 Input side ground 5 GND2 Output side ground 6 VOUT– Negative output 7 VOUT+ Positive output 8 VDD2 Supply voltage for output side (3 V to 5.5 V), relative to GND2 Table 2. Ordering Information ACPL-C79B/C79A/C790 is UL recognized with 5000 Vrms/1 minute rating per UL 1577 (pending). Part number Option (RoHS Compliant) Package Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-5 Quantity ACPL-C79B ACPL-C79A ACPL-C790 -000E Stretched SO-8 X X 80 per tube -500E X X X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example: ACPL-C79B-500E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliance. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 3 Package Outline Drawings Stretched SO-8 Package (SSO-8) 5.850 ± 0.50 (0.230 ± 0.010) 5678 4321 Dimensions in millimeters and (inches). Lead coplanarity = 0.1 mm (0.004 inches). 6.807 ± 0.127 (0.268 ± 0.005) RECOMMENDED LAND PATTERN 12.650 (0.5) 1.905 (0.1) 3.180 ± 0.127 (0.125 ± 0.005) 0.381 ± 0.130 (0.015 ± 0.005) 1.270 (0.050) BSG 7° (0.453 ± 0.010) (0.008 ± 0.004)(0.0295 ± 0.010) 0.200 ± 0.1000.750 ± 0.250 11.50 ± 0.250 (0.063 ± 0.005) 1.590 ± 0.127 (0.018) 0.450 45° RoHS-COMPLIANCE INDICATOR PART NUMBER DATE CODE C79B YYWW Figure 2. SSO-8 package. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-C79B/C79A/C790 is pending for approvals by the following organizations: IEC/EN/DIN EN 60747-5-5 Approved with Maximum Working Insulation Voltage VIORM = 1140 Vpeak. UL Approval under UL 1577, component recognition program up to VISO = 5000 Vrms/1min. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 4 Table 3. Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (External Clearance) L(101) 8.0 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (External Creepage) L(102) 8.0 mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Plastic Gap (Internal Clearance) 0.5 mm Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 4. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics [1] Description Symbol Value Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 V rms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I-IV I-IV I-III I-III I-II Climatic Classification 55/105/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 1140 Vpeak Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VPR 2137 Vpeak Input to Output Test Voltage, Method a VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC VPR 1824 Vpeak Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values (Maximum values allowed in the event of a failure) Case Temperature Input Current [2] Output Power [2] TS IS,INPUT PS,OUTPUT 175 230 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS ≥ 109 � Notes: 1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. 2. Safety-limiting parameters are dependent on ambient temperature. The Input Current, IS,INPUT, derates linearly above 25°C free-air temperature at a rate of 2.53 mA/°C; the Output Power, PS,OUTPUT, derates linearly above 25°C free-air temperature at a rate of 4 mW/°C. 5 Table 5. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 +125 °C Ambient Operating Temperature TA –40 +105 °C Supply Voltages VDD1, VDD2 –0.5 6.0 V Steady-State Input Voltage [1, 3] VIN+, VIN– –2 VDD1 + 0.5 V Two-Second Transient Input Voltage [2] VIN+, VIN– –6 VDD1 + 0.5 V Output Voltages VOUT+, VOUT– –0.5 VDD2 + 0.5 V Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Notes: 1. DC voltage of up to –2 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. 2. Transient voltage of 2 seconds up to –6 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. 3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs. Table 6. Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA –40 +105 °C VDD1 Supply Voltage VDD1 4.5 5.5 V VDD2 Supply Voltage VDD2 3 5.5 V Input Voltage Range [1] VIN+, VIN– –200 +200 mV Notes: 1. ±200 mV is the nominal input range. Full scale input range (FSR) is ±300 mV. Functional input range is ±2 V. 6 Table 7. Electrical Specifications Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = –200 mV to +200 mV, and VIN– = 0 V (single-ended connection). Parameter Symbol Min. Typ.[1] Max. Unit Test Conditions/Notes Fig. DC CHARACTERISTICS Input Offset Voltage VOS –1 0.6 2 mV TA = 25°C 3, 4 Magnitude of Input Offset Change vs. Temperature |dVOS/dTA| 3 10 �V/°C TA = –40°C to +105°C; absolute value 5 Gain (ACPL-C79B, ±0.5%) G0 8.16 8.2 8.24 V/V TA = 25°C; Note 2 6, 7 Gain (ACPL-C79A, ±1%) G1 8.12 8.2 8.28 V/V TA = 25°C; Note 2 6, 7 Gain (ACPL-C790, ±3%) G3 7.95 8.2 8.44 V/V TA = 25°C; Note 2 6, 7 Magnitude of Gain Change vs. Temperature dG/dTA –0.00041 V/V/°C TA = –40°C to +105°C; Note 3 8 Nonlinearity over ±200 mV Input Voltage NL200 0.05 0.13 % VIN+ = –200 mV to +200 mV, TA = 25°C; Note 2 9, 10 Magnitude of NL200 Change vs. Temperature dNL200/dTA 0.0003 %/°C TA = –40°C to +85°C 11 0.004 %/°C TA = +85°C to +105°C 11 Nonlinearity over ±100 mV Input Voltage NL100 0.02 0.06 % VIN+ = –100 mV to +100 mV, TA = 25°C; Note 2 9, 10, 11 INPUTS AND OUTPUTS Full-Scale Differential Voltage Input Range FSR ±300 mV VIN = VIN+ – VIN–; Note 4 12 Input Bias Current IIN+ –1 –0.1 �A VIN+ = 0 V, VIN– = 0 V; Note 5 13 Magnitude of IIN+ Change vs. Temperature dIIN+/dTA –0.05 nA/°C Equivalent Input Impedance RIN 22 k� VIN+ or VIN–, single-ended 14 Output Common-Mode Voltage VOCM 1.23 V VOUT+ or VOUT–; Note 6 Output Voltage Range OVR 0 to 2.5 V VOUT+ or VOUT–; Note 4 12 Output Short-Circuit Current |IOSC| 11 mA VOUT+ or VOUT–, shorted to GND2 or VDD2 Output Resistance ROUT 21 � VOUT+ or VOUT– Input DC Common-Mode Rejection Ratio CMRRIN 76 dB Note 2 AC CHARACTERISTICS Signal-to-Noise Ratio SNR 60 dB VIN+ = 300 mVpp 10 kHz sine wave; Note 7 15, 16 Signal-to-(Noise + Distortion) Ratio SNDR 56 dB VIN+ = 300 mVpp 10 kHz sine wave; Note 8 15, 16 Small-Signal Bandwidth (-3 dB) f–3 dB 140 200 kHz 17, 18 Input to Output Propagation Delay 10%-10% tPD10 1.6 2.3 �s 200 mV/�s step input 19 50%-50% tPD50 2 2.6 �s 200 mV/�s step input 19 90%-90% tPD90 2.6 3.3 �s 200 mV/�s step input 19 Output Rise/Fall Time (10%-90%) tR/F 1.7 �s Step input 19 Common Mode Transient Immunity CMTI 10 15 kV/�s VCM = 1 kV, TA = 25°C; Note 2 Power Supply Rejection PSR –78 dB 1 Vpp 1 kHz sine wave ripple on VDD1, differential output; Note 9 POWER SUPPLIES Input Side Supply Current IDD1 13 18.5 mA VIN+ = 400 mV; see Note 10 20 Output Side Supply Current IDD2 7 12 mA 5 V supply 20 6.8 11 mA 3.3 V supply 20 7 Notes: 1. All Typical values are under Typical Operating Conditions at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V. 2. See Definitions section. 3. Gain temperature drift can be normalized and expressed as Temperature Coefficient of Gain (TCG) of –50 ppm/°C. 4. When FSR is exceeded, outputs saturate. 5. Because of the switched-capacitor nature of the input sigma-delta converter, time-averaged values are shown. 6. Under Typical Operating Conditions, part-to-part variation ±0.04 V. 7. Under Typical Operating Conditions, part-to-part variation ±1 dB. 8. Under Typical Operating Conditions, part-to-part variation ±1 dB. 9. Ripple voltage applied to VDD1 with a 0.1 �F bypass capacitor connected; differential amplitude of the ripple outputs measured. See Definitions section. 10. The input supply current decreases as the differential input voltage (VIN+ – VIN–) decreases. Table 8. Package Characteristics Parameter Symbol Min. Typ. Max. Unit Test Condition Note Input-Output Momentary Withstand Voltage VISO 5000 Vrms RH < 50%, t = 1 min., TA = 25°C 1, 2 Resistance (Input-Output) RI-O >1012 � VI-O = 500 VDC 3 Capacitance (Input-Output) CI-O 0.5 pF f = 1 MHz 3 Notes: 1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 �A). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747- 5-5 Insulation Characteristic Table. 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 insulation characteristics table and your equipment level safety specification. 3. This is a two-terminal measurement: pins 1–4 are shorted together and pins 5–8 are shorted together. 8 Figure 4. Input offset vs. supply VDD2.Figure 3. Input offset vs. supply VDD1. Figure 6. Gain vs. supply VDD1.Figure 5. Input offset vs. temperature. Figure 8. Gain vs. temperature.Figure 7. Gain vs. supply VDD2. Typical Performance Plots Unless otherwise noted, TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V. 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 4.5 4.75 5 5.25 5.5 VDD1 - SUPPLY VOLTAGE - V OF FS ET - m V VDD2 = 3.3V VDD2 = 5V 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 3 3.5 4 4.5 5 5.5 VDD2 - SUPPLY VOLTAGE - V OF FS ET - m V VDD1 = 5V 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - °C OF FS ET - m V 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 4.5 4.75 5 5.25 5.5 VDD1 - SUPPLY VOLTAGE - V GA IN - V/ V 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 3 3.5 4 4.5 5 5.5 VDD2 - SUPPLY VOLTAGE - V GA IN - V/ V 8.12 8.14 8.16 8.18 8.20 8.22 8.24 8.26 8.28 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - °C G - G AI N - V /V VDD2 = 3.3V VDD2 = 5V VDD1 = 5V 9 Figure 10. Nonlinearity vs. supply VDD2.Figure 9. Nonlinearity vs. supply VDD1. Figure 12. Output voltage vs. input voltage.Figure 11. Nonlinearity vs. temperature. Figure 14. Input impedance vs. temperature.Figure 13. Input current vs. input voltage. 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 4.5 4.75 5 5.25 5.5 VDD1 - SUPPLY VOLTAGE - V NL - NO NL IN EA RI TY - % 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 3 3.5 4 4.5 5 5.5 VDD2 - SUPPLY VOLTAGE - V NL - NO NL IN EA RI TY - % 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - °C NL - LI NE AR IT Y - % -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 VIN+ - INPUT VOLTAGE - V V OU T - O UT PU T V OL TA GE - V -30 -25 -20 -15 -10 -5 0 5 10 15 20 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 VIN+ - INPUT VOLTAGE - V I IN + - IN PU T C UR RE NT - �A 21 22 23 24 25 -40 -20 0 20 40 60 80 100 120 TA - TEMPERATURE - °C R I N - IN PU T I M PE DA NC E - k oh m NL200, VDD2 = 5V NL200, VDD2 = 3.3V NL100, VDD2 = 5V NL100, VDD2 = 3.3V NL100 NL200 VDD1 = 5V NL100 NL200 VOUT+VOUT– VIN+ = 0 to 300mV 10 Figure 16. SNR, SNDR vs. input voltage.Figure 15. SNR, SNDR vs. temperature. Figure 18. Phase frequency response.Figure 17. Gain frequency response. Figure 20. Supply current vs. input voltage.Figure 19. Propagation delay, output rise/fall time vs. temperature. VIN+ - INPUT VOLTAGE - m Vpp 40 43 46 49 52 55 58 61 64 -40 -20 0 20 40 60 80 100 120 SN R, SN DR - dB SNR SNDR 40 43 46 49 52 55 58 61 64 100 150 200 250 300 350 400 SN R, SN DR - dB SNR SNDR -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 100 1,000 10,000 100,000 1,000,000 FREQUENCY - Hz 100 1,000 10,000 100,000 1,000,000 FREQUENCY - Hz NO RM AL IZ ED G AI N - d B -180 -150 -120 -90 -60 -30 0 30 60 90 120 150 180 PH AS E - D EG RE ES 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -40 -20 0 20 40 60 80 100 120 PR OP AG AT IO N DE LA Y - � s tPD90 tPD50 tR/F tPD10 5 6 7 8 9 10 11 12 13 14 15 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 I D D - SU PP LY CU RR EN T - m A TA - TEMPERATURE - °C TA - TEMPERATURE - °C VIN+ - INPUT VOLTAGE - V VIN+ = 300mVpp 10 kHz sine wave tPD10, tPD50, tPD90: 200mV/�s step input; tR/F: step input IDD1 (VDD1 = 5V) IDD2 (VDD2 = 5V) IDD2 (VDD2 = 3.3V) 11 Definitions Gain Gain is defined as the slope of the best-fit line of differen- tial output voltage (VOUT+ – VOUT–) vs. differential input voltage (VIN+ – VIN–) over the nominal input range, with offset error adjusted out. Nonlinearity Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a per- centage of the full-scale differential output voltage. Input DC Common Mode Rejection Ratio, CMRRIN CMRRIN is defined as the ratio of the differential signal gain (signal applied differentially between pins VOUT+ and VOUT–) to the input side common-mode gain (input pins tied together and the signal applied to both inputs with respect to pin GND1), expressed in dB. Common Mode Transient Immunity, CMTI, also known as Com- mon Mode Rejection CMTI is tested by applying an exponentially rising/falling voltage step on pin 4 (GND1) with respect to pin 5 (GND2). The rise time of the test waveform is set to approximately 50 ns. The amplitude of the step is adjusted until the dif- ferential output (VOUT+ – VOUT–) exhibits more than a 200 mV deviation from the average output voltage for more than 1�s. The ACPL-C79B/C79A/C790 will continue to function if more than 10 kV/μs common mode slopes are applied, as long as the breakdown voltage limitations are observed. Power Supply Rejection, PSR PSR is the ratio of differential amplitude of the ripple outputs over power supply ripple voltage, referred to the input, expressed in dB. 0.1 �F VDD2 (+5 V) VDD1 VOUT 8 7 6 1 3 U2 5 2 4 R1 2.00 K +15 V C8 0.1 �F 0.1 �F -15 V – + TL032A R3 10.0 K ACPL-C79B/ ACPL-C79A/ ACPL-C790 C4 R4 10.0 K C6 47 pF U3 U1 78L05 IN OUT C1 C2 47 nF R5 10 GATE DRIVE CIRCUIT POSITIVE FLOATING SUPPLY HV+ * * * HV- –+ RSENSE MOTOR C5 47 pF 0.1 �F 0.1 ��F C3 C7 R2 2.00 K * * * * * * GND1 GND2 GND2 GND2 GND2 Figure 21. Typical application circuit for motor phase current sensing. 12 Figure 22. Example printed circuit board layout. PC Board Layout The design of the printed circuit board (PCB) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. In addition, the layout of the PCB can also affect the isolation transient immunity (CMTI) of the ACPL-C79B/C79A/C790, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMTI performance, the layout of the PC board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the PC board does not pass directly below or extend much wider than the body of the ACPL-C79B/C79A/C790. Figure 22 shows an example PCB layout. TO GND1 TO VDD1 R5 C3 C4