538 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998
Design Considerations and Performance Evaluations
of Synchronous Rectification in Flyback Converters
Michael T. Zhang, Member, IEEE, Milan M. Jovanovic´, Senior Member, IEEE, and Fred C. Y. Lee, Fellow, IEEE
Abstract—Design tradeoffs and performance comparisons of
various implementations of the flyback converter with a
synchronous rectifier (SR) are presented. Specifically, the merits
and limitations of the constant-frequency (CF) continuous-
conduction mode (CCM), CF discontinuous-conduction mode
(DCM), variable-frequency (VF) DCM, and zero-voltage-
switched (ZVS) DCM flyback converters with SR’s are
discussed. The theoretical efficiency improvements of the
discussed synchronous rectification approaches relative to
Schottky diode implementations are derived. Finally, theoretical
results are verified on an experimental universal-input off-line
15-V/36-W flyback prototype.
Index Terms—Efficiency, flyback converter, synchronous rec-
tification.
I. INTRODUCTION
GENERALLY, in low-output-voltage power supplies, theconduction loss of the diode rectifier (DR) due to its
forward voltage drop is the dominant loss component. In power
supplies with the output voltage not too many times higher
than the rectifier forward voltage drop, the DR loss accounts
for more than 50% of the total power loss. The rectification
loss can be reduced by replacing the DR with a synchronous
rectifier (SR), i.e., with a low-on-resistance MOSFET [1], [2].
Synchronous rectification is most often applied to the buck and
buck-derived isolated topologies, which are suitable for step-
down low-output-voltage applications [2]. Generally, in the
isolated buck-derived topologies, such as the forward, bridge-
type, and push–pull converters, synchronous rectification can
be implemented by a direct replacement of the DR’s with
low-voltage MOSFET’s [3], [4]. Namely, in these self-driven
SR implementations, the secondary voltage of the transformer
is used to directly drive the SR’s, thus reducing the circuit
complexity and cost without sacrificing the efficiency.
A number of applications of the SR in the flyback converter
have also been reported [5]–[7]. However, in all of these
applications, the main purpose of the SR was to provide the
postregulation of the output voltage and not to maximize the
conversion efficiency. Specifically, in [5]–[7], the SR is used
Manuscript received January 7, 1997; revised July 28, 1997. This work
was supported by Delta Electronics, Inc., Taiwan. Recommended by Associate
Editor, R. Steigerwald.
M. T. Zhang is with the Platform Architecture Laboratory, Intel Corpora-
tion, Hillsboro, OR 97124-5916 USA.
M. M. Jovanovic´ is with the Delta Power Electronics Laboratory, Inc.,
Blacksburg, VA 24060 USA.
F. C. Y. Lee is with the Virginia Power Electronics Center, Bradley
Department of Electrical Engineering, Virginia Polytechnic Institute and State
University, Blacksburg, VA 24061-0111 USA.
Publisher Item Identifier S 0885-8993(98)03343-2.
Fig. 1. Flyback converter with SR.
as a voltage-controlled resistor in a control loop which adjusts
the SR’s resistance so that the output voltage is maintained
within the regulation range. Generally, the regulation range
of these postregulation approaches is limited to the forward
voltage drop of the SR body diode, i.e., 0.7 V. Moreover,
since the voltage drop across the SR is not minimized because
of the resistance modulation, the conversion efficiency of these
postregulators is reduced, compared to that of the converter
with the “true” SR.
The objective of this paper is to evaluate the theoretical
and practical limits of the efficiency improvements for various
implementations of the flyback converter with the SR with
respect to the corresponding converter with the DR. Specifi-
cally, the design considerations and performance evaluations
of the constant-frequency (CF) continuous-conduction mode
(CCM), CF discontinuous-conduction mode (DCM), variable-
frequency (VF) DCM, and zero-voltage-switched (ZVS) DCM
flyback converters with the SR are discussed.
II. SYNCHRONOUS RECTIFIER IMPLEMENTATIONS
A flyback converter with the SR is shown in Fig. 1. For
proper operation of the converter, conduction periods of pri-
mary switch SW and secondary-side switch SR must not
overlap. To avoid the simultaneous conduction of the SW
and the SR, a delay between the turn-off instant of switch
SW and the turn-on instant of the SR as well as between
the turn-on instant of the SW and turn-off instant of the
SR must be introduced in the gate-drive waveforms of the
switches. With properly designed gate drives, the operation
of the circuit shown in Fig. 1 is identical to that with a
conventional DR. Namely, during the time switch SW is turned
on, energy is stored in the transformer magnetizing inductance
and transferred to the output after SW is turned off.
0885–8993/98$10.00 1998 IEEE
ZHANG et al.: DESIGN CONSIDERATIONS AND EVALUATIONS OF FLYBACK CONVERTERS 539
Generally, the circuit sown in Fig. 1 can work in CCM or
DCM either with a constant or variable switching frequency
pulse-width-modulation (PWM) control. Design considera-
tions and SR loss estimates for various modes of operation
and different control approaches are given next.
A. Constant-Frequency CCM
The key waveforms of the flyback converter with the SR
operating in CCM are given in Fig. 2. As can be seen from
Fig. 2, during delay times and , secondary current
flows through the body diode of the SR (shaded
region in Fig. 2). The conduction of body diode not only
increases the conduction loss, but also introduces a reverse
recovery loss when primary switch SW is turned on. The
total conduction loss of the SR is given by the sum of the
channel-resistance loss (unshaded region in Fig. 2) and
body-diode loss (shaded region in Fig. 2). Assuming that
the conduction time through the channel of the SR is much
longer than the conduction time through the body diode of the
SR, i.e., assuming that the SR conducts through the channel for
the entire off period, the rms value of the trapezoidal secondary
current which flows through the channel can be derived as
(1)
where is the SR on resistance, is the
duty ratio of the primary switch, is the output current,
is the secondary peak-
to-peak ripple current, is the primary-side magnetizing
inductance of the transformer, is the switching period, and
is the turns ratio of the transformer, respectively. Using (1),
the total conduction loss of the SR can be calculated as
(2)
where the second term represents the loss incurred by the
conduction of the body diode of the SR. In (2), is the
forward voltage drop of the SR’s body diode and and
are the SR’s body diode currents during dead times
and , respectively. Because dead times and
are short compared with off-time , currents and
can be considered constant during the SR’s body diode
conduction. Since in the CCM
and , the total conduction loss
of the SR can be expressed as
(3)
The total reverse recovery loss of the body diode of the SR
is [8]
(4)
Fig. 2. Key waveforms of CF CCM flyback converter with SR. Body diode
of SR conducts in shaded area ( ).
where is the recovered charge of the SR body diode and
is the steady-state reverse voltage across the SR.
In addition to and losses, the CF CCM converter
in Fig. 1 exhibits a loss each time the SR is turned off (i.e.,
each time the SW is turned on) because of a parasitic resonance
between and the leakage inductance of the transformer
(see Fig. 9). Since the parasitic resonance must be damped by
a snubber to limit the maximum voltage across the SR, the
resonance dies out completely before SR is turned on again.
As a result, the power loss due to this parasitic resonance can
be calculated from
(5)
Finally, for proper operation of the circuit, the SR must
be turned off before primary switch SW is turned on (delay
time in Fig. 2). Therefore, the flyback converter with the
SR cannot be self-driven from the secondary winding of the
transformer. In fact, the circuit shown in Fig. 1 requires an
external control circuit to turn off the SR.
B. Constant-Frequency DCM
The key waveforms of the CF flyback converter with the
SR operating in DCM are shown in Fig. 3. In DCM, the
energy stored in the magnetizing inductance of the transformer
during the on time of switch SW is completely discharged
during the subsequent off time. As can be seen from Fig. 3,
secondary current reaches zero before primary switch SW
is turned on. To prevent the discharging of the output filter
capacitor through a conducting SR, the SR channel conduction
(transistor ) must be terminated at the moment reaches
zero, or a short while after. Therefore, the DCM flyback
converter with the SR requires a zero-current crossing detector
in the control circuit.
After the SR is turned off, the magnetizing inductance of
the transformer and capacitance
starts resonating, as shown in Fig. 3. For a converter with a
regulated output, the duration of resonant interval in
540 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998
Fig. 3. Key waveforms of CF DCM flyback converter with SR. Body diode
of SR conducts in shaded area ( ).
Fig. 3 changes significantly with the input voltage and less
dramatically with the output current. As a result, the voltage
across the primary switch at the moment of its turn on can
range anywhere between and , producing
the capacitive turn-on loss of
(6)
where . Since
is maximum at the peaks of the oscillation and
minimum at its valleys, the efficiency of the converter shows
strong fluctuations with the input voltage. In addition, because
typical SR’s have a much larger output capacitance than
the Schottky rectifiers, the characteristic impedance
of the resonant tank consisting of and
is much lower for the converter with an SR compared to that
with a Schottky diode. As a result, the resonant-tank current
of the converter with an SR is much higher than that of
the converter with a Schottky, causing a larger conduction
loss. For certain line and load conditions, this power loss can
completely offset the power-loss savings obtained by the SR,
making the efficiency of the converter with the SR lower than
that of the converter with the DR.
Finally, it should be noted that in the DCM flyback converter
reverse-rectifier loss is eliminated because the rectifier
current becomes zero before primary switch SW is turned on.
C. Variable-Frequency DCM
Capacitive switching loss can be minimized, and
parasitic oscillation caused by the interaction of and
can be eliminated if the primary switch SW is turned on at the
moment reaches its minimum voltage the
first time after the SR is turned off, as shown in Fig. 4. This
can be accomplished by sensing the zero-current crossing of
and turning on SW after a constant delay , which is
equal to one half of the parasitic-resonance period, i.e.,
(7)
With this VF control, the efficiency fluctuations with the
input voltage are eliminated. It should be noted that with the
VF control, the switching frequency is minimum at low line
Fig. 4. Key waveforms of VF DCM flyback converter with SR. Body diode
of SR conducts in shaded area ( ).
and full load, and it increases as the line increases and/or load
decreases.
The conversion efficiency at low line of the VF DCM
converter can be always made higher than the efficiency
of the corresponding CF counterpart. In addition, the high-
line efficiency of the VF DCM converter can also be higher
than that of the CF DCM implementation if the power-loss
savings due to elimination of the parasitic oscillations and
the minimization of the turn-on voltage are lower than
the increased switching losses and magnetic losses due to the
increased switching frequency.
D. Variable-Frequency ZVS DCM
As can be seen from Fig. 4, if the amplitude of the os-
cillation after the turn off of the SR is larger than the input
voltage, i.e., if
(8)
primary-switch voltage will fall to zero before the
switch is turned on at the moment . Therefore,
for , the VF flyback converter can achieve ZVS,
i.e., the capacitive turn-on loss of the primary switch can be
eliminated. While the ZVS condition in (8) may be met for
certain designs at low input-voltages, generally it is not met at
higher input voltages. As a result, at higher input voltages, the
VF flyback converter with gate-drive timing given in Fig. 4
operates with partial ZVS.
However, the complete ZVS of the primary switch in the
VF flyback converter with the SR can be achieved in the
entire input-voltage range if the turn-off instant of the SR
after the secondary current zero crossing is delayed enough to
allow a negative secondary current to build up, as shown in
Fig. 5. To achieve ZVS in the entire input-voltage range, the
energy stored in magnetizing inductance by the negative
secondary current must be large enough to discharge
primary switch capacitance from voltage down
to zero, i.e.,
(9)
ZHANG et al.: DESIGN CONSIDERATIONS AND EVALUATIONS OF FLYBACK CONVERTERS 541
TABLE I
POWER LOSS COMPARISONS OF FLYBACK CONVERTERS WITH DR AND SR
Fig. 5. Key waveforms of VF ZVS DCM operation.
Therefore, to build up the necessary , the turn off of the
SR should be delayed after the zero crossing of for
(10)
as shown in Fig. 5.
Finally, it should be noted that in the VF ZVS DCM flyback
converter with the SR, the capacitive turn-on switching loss
of the primary switch is traded off for the conduction loss.
Namely, according to Fig. 5, due to the negative secondary
current, the rms value of the secondary current is slightly
increased. Therefore, the VF ZVS converter in Fig. 5 might
not necessarily achieve higher efficiency compared to the VF
converter with partial ZVS (Fig. 4).
III. SR EFFICIENCY IMPROVEMENT ESTIMATES
Generally, in a flyback converter, the substitution of the DR
with an SR affects the conduction and switching losses of the
rectifier. In addition, the employment of an SR allows for the
implementation of VF flyback converter with complete ZVS,
i.e., without any primary-switch capacitive turn-on switching
loss . Table I summarizes theoretical rectifier con-
duction loss , rectifier switching losses,
, and the primary switching loss of the flyback
converter with the DR and the SR.
The efficiency of a converter with the DR can be expressed
as
(11)
where is the output power and is the loss other
than the conduction and switching losses of the rectifier
and the capacitive turn-on switching loss of the primary
switch. Specifically, includes the transformer, input
[electromagnetic interference (EMI)] filter, output filter, and
control circuit losses, i.e., the losses which are virtually the
same for both the SR and rectifier diode implementations of
the converter.
Similarly, the efficiency of the flyback converter with the
SR can be written as
(12)
By eliminating from (11) and (12), the efficiency
difference between the SR and the DR implementations can
542 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 13, NO. 3, MAY 1998
Fig. 6. Theoretical efficiency estimates.
be calculated as
(13)
where
(14)
Using the power loss expressions from Table I and knowing
the device characteristics and the circuit parameters, the effi-
ciency improvement of the flyback converter with the SR can
be calculated. As an example, Fig. 6 presents the calculated
efficiencies for the discussed four implementations of the
converter with the SR as functions of the load current. In
Fig. 6, it is assumed that the DR versions of the converter
have conversion efficiencies of 89%, which correspond to the
efficiencies of the experimental circuit discussed in the next
section.
As can be seen from Fig. 6, the efficiency of the ZVS
DCM implementation (solid line) is highest at low-power
levels (i.e., for – A) because the switching turn-on
loss of the primary switch contributes significantly to the total
loss in the other implementations. For the same range of the
output power, the CF CCM implementation exhibits the lowest
efficiency due to the dominant effect of the turn-on switching
loss of the primary switch and the turn-off switching loss of
the SR. For example, at A (which corresponds to the
full-load current of the experimental converter presented in the
next section), the efficiency of the ZVS DCM implementation
with the SR is approximately 3% higher than the efficiency of
the corresponding circuit with the Schottky rectifier. However,
at A, the efficiency of the CCM implementation with
the SR at A is 1% lower than the efficiency of the
same circuit with the Schottky rectifier.
At higher power levels, the conduction losses of the primary
switch and the SR start dominating the total loss. As a result,
the CF CCM implementation exhibits the highest efficiency
at A due to its smallest primary and secondary rms
currents. On the other hand, the efficiency of the CF DCM
implementation monolithically decreases as the load current
(output power) increases. In fact, as can be seen from Fig. 6,
for A the efficiency of the CF DCM implementation
is lower than that of the Schottky implementation. Also, as
the load current, and therefore the conduction losses, become
larger, the efficiencies of the VF DCM and ZVS DCM
implementations converge because the power savings brought
about by soft switching in ZVS DCM implementation are less
significant.
Finally, as the output current continues to increase, so that
the voltage drop across the SR approaches that
of the Schottky rectifier , the efficiencies of the CF CCM,
VF DCM, and ZVS DCM implementations approach that of
the Schottky-rectifier implementation. As can be seen from
Fig. 6, at A, the efficiencies of the VF DCM and
ZVS DCM implementations fall to the level of the Schottky
implementation efficiency. The CF CCM implementation ef-
ficiency drops to that of the Schottky-rectifier implementation
at A due to lower . The only way to achieve
efficiency improvements at higher load currents, i.e., when
, is to resort to paralleling of SR’s in order
to reduce the effective .
IV. EVALUATION RESULTS
The discussed SR implementations were experimentally
evaluated on a 15-V/2.4-A flyback converter designed to oper-
ate in the 100–370-Vdc input-voltage range. The diode-version
power stages were implemented with Motorola MTP6N60
( V, C, and
pF V) MOSFET’s for the primary
switches and two IR 10CQT150 ( V,
V A , C, and pF
V) Schottky diodes in parallel for the secondary rectifiers. In
implementations of the power stages with SR’s, the Schottky
diodes were replaced with IXYS IXFK100N10 (
V, m C, pF
V, and V) MOSFET’s. The turns ratio of the
transformer for the CCM implementation was
( H), and the converter was operated in CCM
at full load over the entire input line range with switching
frequency kHz [9]. The transformer used for all
other implementations (CF DCM, VF DCM, and ZVS DCM)
had a turns ratio of ( H).
Fig. 7 shows the control and drive circuit for the variable
frequency DCM flyback converter implementations with the
SR. As can be seen from Fig. 7, the converter has a detector
which senses zero crossings of secondary current . The
delay time between the zero crossing of secondary current
and the turn off of the SR is set by the R-C time constant
of the circuit which is connected to the output of the
zero-crossing detector comparator. Resistors and are
used to set the hysteresis of the zero-crossing detector. The
VF control of the converter is achieved by employing the UC
3852 IC controller. Also, an R-C delay circuit is used on the
primary side to set a proper delay between the turn off of
the SR and the turn on of the primary switch. The UC3852
functional description, operation, and implementation in VF
ZCS applications are thoroughly explained in [10].
ZHANG et al.: DESIGN CONSIDERATIONS AND EVALUATIONS OF FLYBACK CONVERTERS 543
Fig. 7. Control and drive circuit for VF DCM flyback converter with SR.
The thick lines
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