CRM PFC计算

Application Note UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Preregulator Application Note SLUU138A − December 2002 − Revised June 2004 2 UCC38050 100-W Critical Conduction UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Preregulator Michael O’Loughlin Power Supply Control Products ABSTRACT Power factor corrected (PFC) preregulators are generally used in higher power ac-to-dc offline power converters or to meet line harmonic requirements such as EN61000−3−2. The designs are typically done using a boost topology with the average current mode control offered by PFC controllers such as TI/Unitrode’s UC3854 and UCC3817. These 16-pin controllers are pulse width modulators (PWM) that require many external components to achieve near unity power factor (PF). However, in some applications, it may not be necessary to acheive the levels of PF and the current total harmonic distorion (THD) that the average current mode control can provide. The PFC preregulator can be designed using a critical conduction mode control (also referred to as transition mode control). The 8-pin UCC38050 PFC controller is designed for such an application. The UCC38050 operates with pulsed frequency modulation (PFM) in a critical conduction mode. Contents 1 Introduction 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power Stage Design 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Inductor Selection 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Boost Switch Selection (D1) And Boost Diode Selection (Q1) 7. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Heat Sinks 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Output Holdup Capacitor Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Input Holdup Capacitor Selection 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Current Resistor Selection 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Multiplier Setup 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Voltage Loop Compensation 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Input Filter Design 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Design Performance 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Summary 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 References 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLUU138A − December 2002 − Revised June 2004 3 UCC38050 100-W Critical Conduction 1 Introduction This application note reviews the design process for a 100-W offline power factor corrected preregulator using the UCC38050 Transition Mode PFC Controller. • The application note was generated using typical parameters rather than worst-case values. • Please refer to the Table 1 and Figure 1 for design specifications and component placement. • Please refer to Table 2, the variable definition table for all variable definitions. Table 1. Design Specifications PARAMETER TEST CONDITION MIN TYP MAX UNIT VIN 85 265 VRMS Input frequency 60 Hz VOUT dc VIN = 85 VRMS 370 400 425 V VOUT dc VIN = 265 VRMS 370 390 410 V POUT 0 100 W Output voltage ripple VIN = 85 VRMS, PO = 100 W 3% Efficiency VIN = 265 VRMS, PO = 100 W 90% Total harmonic distortion (THD) VIN = 265 VRMS, PO = 100 W 5% Total harmonic distortion (THD) 15% Hold-up time 16.7 ms The following table lists and defines all of the variables that are going to be used in this application note. Table 2. Variable Definitions VARIABLE DEFINITION IRMS_C3 RMS current in the boost capacitor CDIODE Boost diode capacitance COMP Dynamic range of the comp pin of the multiplier COSS FET drain to source capacitance fLINE Input line frequency fS Minimum switching frequency GC(s) Control transfer function GCO(s) Control to output transfer function gM Transconductance amplifier gain GVEA Gain of the voltage amplifier HS Voltage divider gain SLUU138A − December 2002 − Revised June 2004 4 UCC38050 100-W Critical Conduction VARIABLE DEFINITION IPEAK Peak inductor current, peak diode current, peak switch current IRMS_DIODE Boost diode current IRMS_FET RMS current in the FET IRMS_L RMS inductor current PSEMI Power dissipated by a semiconductor device PCON_FET Conduction losses in the FET PCOND_DIODE Diode conduction losses PCOSS Power dissipated by the FET’s drain to source capacitance PDIODE Total loss in the boost diode PDIODE_CAP Loss due to boost diode capacitance PFET_TR FET transition losses PGATE Power dissipated by gate of the FET POUT Maximum output power PQ1 Total FET losses QGATE FET gate charge RDS(on) On resistance of the FET RΘcs Thermal impedance case to sink RΘjc Thermal impedance junction to case RΘsa Thermal impedance sink to air TAMB Ambient tempature tF FET fall time tHOLDUP Boost capacitor hold up time TJ(max) Maximum semiconductor temperature tON Boost inductor energizing on time tR FET rise time TS(f) Voltage loop gain VCSENSE Maximum current sense voltage VDROP Amount of voltage the boost capacitor has to hold up VEA(max) Maxim voltage amplifier output. VEA(min) Minimum voltage amplifier output. VGATE Gate drive voltage VIN(max) Maximum RMS input voltage VIN(min) Minimum RMS input voltage VOUT Boost output voltage VPP Output peak-to-peak ripple voltage VR3 Average multiplier input voltage at low line input voltage VREF UCC38050 Internal Reference η Efficiency %THD Percentage of allowable current total harmonic distortion. SLUU138A − December 2002 − Revised June 2004 5 UCC38050 100-W Critical Conduction + + + Figure 1. UCC38050 Schematic SLUU138A − December 2002 − Revised June 2004 6 UCC38050 100-W Critical Conduction 2 Power Stage Design 2.1 Inductor Selection The boost inductor is selected based on the maximum ripple current at the peak of minimum line voltage and the minimum switching frequency. The minimum switching frequency (fS) needs to be set at a frequency above the audible range. for this design fS was selected to be 25 kHz. The following equation can be used to calculate the required inductor for the power stage for a critical conduction design. The calculated inductance for this design was roughly 1 mH. To make the design process easier the inductor was designed by Cooper Electronics part number CTX16−15954. L1 � �VOUT� 2� VIN(min)� � �� VIN(min) 2 2� fS� VOUT� POUT In this design an auxiliary winding was taken off the boost inductor to power the UCC38050 PFM controller. The turns ratio (N) was calculated with the following equation. N � VOUT� VIN(max)� 2� 2 V 2.2 Boost Switch Selection (D1) and Boost Diode Selection (Q1) To properly select D1 and Q1 a power budget is generally set for these devices to maintain the desired efficiency goal. The following equations can be used to estimate power loss in your switching devices. To meet the power budget for this design an IRF840 HEX FET and HFA08TB60STRR fast recovery diode from International Rectifier were chosen for this design to meet the power constraints. Equations used to calculate the loss In Q1: IRMS_FET � POUT� 2� 2 � �� VIN(min) � 16� 4� 2� � VIN(min) 9� �� VOUT � IRMS_L � POUT �� VOUT(min)� 6� PGATE � QGATE� VGATE� fS, PCOSS � 1 2 COSSVOUT(min) 2 � fS, PCOND_FET � RDS(on)� IRMS_FET 2 IPEAK � POUT� 2� 2 � � 1.3 �� VIN(min) (1) (2) (3) (4) (5) (6) (7) (8) SLUU138A − December 2002 − Revised June 2004 7 UCC38050 100-W Critical Conduction Equations used to estimate the loss in D1: PDIODE � PCOND_DIODE� PDIODE_CAP IRMS_DIODE � POUT� 2� 2 � �� VIN(min) � 4� 2� � VIN(min) 9� �� VOUT � PCOND_DIODE � Vf� IAVG PDIODE_CAP � CDIODE 2 � VOUT(min) 2 � fS NOTE: The diode RMS current is used as an estimate of average current to approximate conduction losses in the diode. 2.3 Heat Sinks The following equation can be used to calculate the minimum required thermal impedance of the heat sinks (Rθsa) required for this design for Q1 and D1. The heat sink was designed to ensure that the junction tempature would not go above 75% of their rated maximum with convection cooling with a maximum ambient temperature of 60°C. The heat sink required for Q1 was an Avvid heat sink part number 593002 B 0 00 00. Because of the zero current switching technique (ZCS) used in this topology a heat sink was not required for D1.[6] R�sa � TJ(max)� TAMB� PSEMI� �R�CS� R�JC� PSEMI 2.4 Output Holdup Capacitor Selection The following equations were used to estimate the minimum holdup capacitor size (C3) and the maximum allowable RMS current through the boost capacitor (IRMS_C3). The holdup capacitor was designed for 16.7 ms of holdup time (tholdup) allowing the output 85 V of drop (VDROP). C3 � 2� POUT� tHOLDUP VOUT(min)2� VOUT(min)� VDROP 2 IRMS_C3 � POUT VOUT(min) � 16� VOUT(min) 3� �� VIN(min)� 2� � 1� (9) (10) (11) (12) (13) (14) (15) SLUU138A − December 2002 − Revised June 2004 8 UCC38050 100-W Critical Conduction 2.5 Input Holdup Capacitor Selection Due to the high ripple current of this PFC preregulator topology, holdup capacitance is required. However, if too much capacitance is added, it can cause an unwanted current phase shift. The capacitor is selected to provide half of the input current at low line maximum load when the boost inductor L1 is energizing for time tON. tON � 2� L1� POUT �� VIN(min) 2 C5 �� POUT�tON ��2 �VOUT(min)� 2� � 2 � VOUT(min)� 2� � VDROP 2 2.6 Current Resistor Selection The following equation can be used to size the current-sense resistor R7. The current-sense resistor should be selected to trip the peak current limit comparitor at 130% of the maximum output power. VCSENSE is the peak current limit comparitor’s threshold of 1.7 V. R7 � VCSENSE POUT�2� 2 � ��VIN(min) � 1.3 2.7 Multiplier Setup The multiplier is used to shape the input current waveform and must be set up correctly to get proper PFC. The multiplier was designed for a maximum input voltage range of 3:1. The multiplier’s input is sensed from the rectified line voltage. Resistors R8, R5, R3 and C2 form a voltage divider and form a low pass filter. R8 and R5 were selected first and the following equations were used to properly size R3 for a 3 to 1 input range. A 1-nF capacitor (C2) was put in parallel with R3 to filter out high frequency noise. VR3 � VC_SENSE� (0.9) K� �VEA(max)� 2.5 V� � 0.075 V R3 � (R8� R5)VR3 VIN(min)� VR3 (16) (17) (18) (19) (20) SLUU138A − December 2002 − Revised June 2004 9 UCC38050 100-W Critical Conduction 2.8 Voltage Loop Compensation Figure 2 shows the small signal control block diagram for this application. The following equations describe each small signal gain block; as well as the voltage loop frequency response TS. Gc(s) Gco(s)VREF H(s) � + − Vc VIN VOUT Figure 2. Small Signal Control HS � R1 R1� R2� R9 GC(s) � gM� (s(f)� R13� C9� 1) s(f)� (C9� C11)��s(f)�C9�C11C9�C11 � 1� GCO(s) � �VOUT �VC � k� VIN 2 s� C3� VOUT� R7� 2 � R3R5� R8� R3 TS(f) �� H(s)�GC(s)�GCO(s) To reduce third harmonic distortion typically the voltage loop crosses over at roughly 10 Hz to 12 Hz. This design uses the voltage loop crossover (fC) to be roughly 10 Hz at the maximum input voltage (VIN(max)). The following equations were used to select the components to compensate the voltage loop TS(f) to crossover at the desired fC with 45 degrees of phase margin. R13 � 4� VOUT 2 � �� fC� C3� R7� (R3� R8� R5) �VREF� VIN(max)2� R3� gm� C9 � 12� �� R13� FC C11 is selected to attenuate the 120-Hz output voltage ripple (VPP) to 1.5% (%THD) of the dynamic range of the comp pin to the multiplier. VPP � POUT � 2� �� 120 Hz� C12� VIN(min) GVEA � %THD� COMP VPP� 100 C11 � H(s)� gm� 1 2� �� �2� fLINE� �GVEA (21) (22) (23) (24) (25) (26) (27) (28) (29) SLUU138A − December 2002 − Revised June 2004 10 UCC38050 100-W Critical Conduction When evaluating the control to output transfer function (GCO(f)) it can be observed that the transfer function will change with line voltage (VIN) which result in a change in TS. After the components are selected it is a good idea to double check that the voltage feedback loop (TS) is stable with changes in input voltage. After the design was complete the frequency response was measured with a network analyzer and the results are shown in Figure 4. From these results, it can be observed that at high line the phase margin was roughly 45 degrees with a cross over frequency of 8 Hz. These results were close to the design goal. at low line the phase margin was roughly 36 degrees with a crossover frequency of roughly 35 degrees. For this design having a phase margin greater than 35 degrees with changes in line voltage is acceptable. −50 −30 −20 0 20 40 50 30 10 −10 −40 −180 −108 −72 0 72 144 180 108 36 −36 −144 100101 VOLTAGE LOOP FREQUENCY RESPONSE TS AT HIGH LINE G ai n Ph as e − de gr ee s fOSC − Frequency − Hz Phase GCO(s)_min GCO(s)_max Figure 3. SLUU138A − December 2002 − Revised June 2004 11 UCC38050 100-W Critical Conduction 3 Input Filter Design The input of a critical conduction PFC preregulator is pictured in waveform A of Figure 4 to meet the less than 10% current THD design goal the input current waveform has to resemble clean sinusoid resembling waveform B of Figure 4. To achieve the current THD design goal an input filter had to be designed. The differential input filter required consists of electrical components C4, C3, L3, and L2. Waveform A Waveform B 2 x IPK 0 A −2 x IPK IPK 0 A −IPK INPUT OF CRITICAL CONDUCTION PFC PREREGULATOR Figure 4. The following equations can be used to properly design the input filter. The filter inductors (L2 and L3) are designed to ensure a smooth continues input current despite the changes in voltage of the input holdup capacitor C5. The differential mode input filter is bi-directional and the double pole frequency (fP) can be set to attenuate high frequency noise. L2 � L3 � �VIN(min)� 2� � VDROP� � tON POUT� 2 � ��VIN(min) C4 � C8 � 1 �2� �� fP� 2 L1 (30) (31) SLUU138A − December 2002 − Revised June 2004 12 UCC38050 100-W Critical Conduction 4 Design Performance The following graphs show the measured performance of this application note. Figure 5 0 50 75 100 0 10 20 30 40 265 V 175 V 85 V TOTAL HARMONIC DISTORION vs OUTPUT POWER TH D − To ta l H ar m on ic D is to rio n − % POUT − Output Power − W Figure 6 25 50 75 100 85 90 95 100 265 V 175 V 85 V EFFICIENCY vs OUTPUT POWER Ef fic ie nc y − % POUT − Output Power − W Figure 7 25 50 75 100 0.900 0.950 1.000 265 V 175 V 85 V POUT − Output Power − W POWER FACTOR vs OUTPUT POWER PF − P ow er F ac to r SLUU138A − December 2002 − Revised June 2004 13 UCC38050 100-W Critical Conduction Figure 8 t − Time − 4 ms/div Rectified Line Voltage CH 4 100 V/div 2 A/div VIN = 85 V, POUT = 100 W Input Curent CH 3 Figure 9 t − Time − 4 ms/div CH 3 CH 4 100 V/div 400 mA/div VIN = 265 V, POUT = 100 W Rectified Line Voltage Input Curent Figure 10 t − Time − 4 ms/div CH 3 CH 4 100 V/div 600 mA/div VIN = 85 V POUT = 25 W Input Curent Rectified Line Voltage Figure 11 t − Time − 4 ms/div CH 3 CH 4 100 V/div 50 mA/div VIN = 265 V, POUT = 25 W Input Curent Rectified Line Voltage 5 Summary With the UCC38050 Critical Conduction PFC Control device and a carefully designed input filter we were able to reach the design goal of less that 10% THD at full load for a universal input range. This design would meet the input current requirements of EN61000−3−2 while using fewer components than a solution using average current mode control topology. SLUU138A − December 2002 − Revised June 2004 14 UCC38050 100-W Critical Conduction 6 References 1. Lloyd Dixon, High Power Factor Switching Preregulator Design Optimization, Unitrode Power Supply Design Seminar Sem−700, Topic 7, 1990 2. Practical Considerations In Current Mode Power Supplies, TI Literature Number SLUA110, Power Supply Control Products (PS) 2000 Data Book, P. 3−559 3. Power Conversion, September 1992 Proceedings, P. 67 4. 100-W Universal Line Input PFC Boost Converter Using The UCC38050, TI Literature Number SLUU134, PP 1−9 5. UCC3817 Data Sheet, TI Literature Number SLUS395F 6. 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