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Practical Applications of Semiconductor Reliability ModelingLori E. Bechtold, Boeing Commercial Airplanes Florian Molière, PhD, Airbus Group Innovations David A. Sunderland, PhD, Boeing Space & Intelligence Systems Bahig Tawfellos, Honeywell Aerospace Key Words: Physics-of-Failure, Predictions, Semiconductor Reliability SUMMARY & CO CLUSIO S A practical methodology for modeling the reliability of deep submicron (<90  nm) semiconductor microcircuits provides timely and needed information for the integration of commercial off the shelf (COTS) electronics in airborne and  high reliability applications. （1）Designing and assuring customer confidence in airborne high reliability applications becomes more challenging as electronics technologies develop rapidly and  commercial application demands drive the increasing use of faster, more integrated, higher density commercial off the shelf (COTS) electronics. （2）Use of COTS electronics provides advantages of greater computational power, with higher manufacturing volumes driving better quality control. COTS also introduce the new problem of life-limited semiconductors [1]. Outdated adequately support reliable aerospace system design [2]. The Semiconductor Reliability project, that launched in April 2013 by the Aerospace Vehicle Systems Institute (AVSI) under the Authority for Expenditure (AFE) 83, （3）developed a practical approach to modeling the random and wearout failure mechanisms of deep sub-micron (<90nm) microcircuits. Unlike prior physics of failure approaches, the methodology was kept simple and was implemented in a spreadsheet. （4）This spreadsheet is provided free of charge to R&M practitioners to help promote understanding and common usage of the methodology. （5）Recipients of the spreadsheet are expected to provide feedback to the AVSI team in return.  The project also encourages microcircuit device suppliers to provide reliability information in some form, （6）either by using the spreadsheet or directly providing the cumulative defect fraction (CDF) of their product in theapplication environments. When microcircuit device suppliers provide test data results for their products, the spreadsheet is used to scale the results from test to usage environments.（7） The methodology developed by AVSI differs from traditional Arrhenius methods in that scaling is not only based on temperature but also on voltage, current and frequency. （8）Models of time dependent dielectric breakdown (TDDB), hot carrier injection (HCI), negative bias temperature instability (NBTI) and electromigration (EM) are used to gain an accurate reliability assessment for technologies sensitive to these mechanisms. （9）This paper describes the AVSI reliability research project,the semiconductor  microcircuit reliability models, andcommercial and provides examples of the application of these models to support reliable avionics systems design. I TRODUCTIO （10）COTS microcircuit wearout has become a major concern for both military/aerospace (mil/aero) integrators and avionics equipment manufacturer companies (OEMs) . （11）By contrast with packaging reliability issues, microcircuit wearoutelectronics degradations cannot be easily addressed and revealed by means  of the typical qualification tests performed on equipment. （12）This is because equipment qualification tests mainly accelerate environmental tresses (thermal cycle vibration,  moisture) without the necessary functional constraints required to bring to light the  life limited semiconductor issues. In this sense, wearout concerns have to be addressed in an early design phase at the sub-assembly level (Figure 1) through component selection methodologies like the one proposed in this paper. （13）Designing for high reliability applications is a challenge that requires  multi-level collaboration to assure vertical integration of the requirements and  information flow necessary for design. （14）Figure 2 illustrates the flow of information between members of the supply chain, showing generally the downward flow of requirements and upward flow of analysis and test data needed to design systems to meet the requirements. （15）Mil/aero integrators design aircraft and other platforms for commercial and military applications. （16）All companies in this market segment face the common need to use the best available COTS electronics in high reliability applications. （17）Airborne  high reliability mil/aero applications generally experience greater environmental stresses than ground based commercial applications. （18）They drive reliability requirements in the context of thermal profiles, thermal cycling and vibration environments down to their suppliers, the avionics OEMs.（19）Avionics OEMs must find architecture solutions and trade multiple and often conflicting requirements. The avionics OEMs procure electronics devices from the microcircuit device suppliers and must understand how the device will operate in the required environments. （20）Mitigation measures at the avionics OEM level include adequately derating the device in the context of thermal profiles, thermal cycling, vibration,  voltage and frequency, and assuring adequate architecture redundancy to guarantee reliability and safety requirements are met throughout the unit life. The microcircuit device suppliers must provide avionics OEMs with enough information and substantiating data so the OEM can make good design decisions while using their devices in electronics modules.  The avionics OEM must provide the mil/aero integrators with enough information and substantiating data for them to use the modules in an airborne platform that meets their customer requirements for high functionality, safety and reliability over the operational lifetimes of the equipment. （21）The AFE 83 project aims to break down communication barriers between these market segments to improve practical semiconductor reliability assessments. （22）AFE 83 is working in collaboration with 与...合作microcircuit device suppliers to develop a practicable methodology for predicting the reliability of integrated circuit semiconductors for high reliability applications. It is developing a simple reliability prediction methodology for random failure rate and the time to intrinsic.（23）The random failure rate portion of the model is similar to MIL-HDBK-217 models [3], because it is scaled with device complexity复杂性 and use conditions. （24）The physics of failure semiconductor wearout models developed in prior AVSI projects [4] are used as a starting point and will be modified based on the inputs from semiconductor suppliers. 2 AVSI AVSI is a research cooperative that addresses issues impacting the aerospace community through international collaborative research conducted by industry, government and academia.（25） （ 翻译 阿房宫赋翻译下载德汉翻译pdf阿房宫赋翻译下载阿房宫赋翻译下载翻译理论.doc ）Members combine their resources and talents to organize and conduct research projects directly benefiting the member organizations and often benefiting the aerospace industry as a whole.（26）AVSI provides a voice for their membership to jointly influence standards, processes and technologies related to aerospace industry. AVSI has invested over a decade of research into electronics reliability, including deep sub-micron (<130nm) semiconductor wearout mechanisms, atmospheric radiation effects and the integration of physics of failure methods into reliability predictions.  In 2010, AVSI reliability roadmap project, AFE 74, engaged a broad community of reliability subject matter experts to develop a consensus based Reliability Prediction Technology Roadmap. The Roadmap identified many gaps in reliability prediction capability to support the application needs identified by the stakeholders.（27）The stakeholders require a methodology that results in timely,accurate and necessary information to support design engineering processes that build customer confidence in product reliability. Semiconductor reliability modeling was identified as a high priority by the roadmap project[5]. 3 APPLICATIO S Aerospace applications often require a 20-30 year service life, while COTS electronics usually are designed for shorter market cycles. while COTS electronics usually are designed for high  performance and low cost, consequently long termreliability is less of a concern. This leaves less incentive for COTS suppliers to address the need for extended life by applying mitigation measures for these  failure  mechanisms.  If “design  for reliability” measures have been applied within the microcircuit, these may be proprietary or not fully understood by the user, so  will not figure in the user’s reliability modeling.  By focusing at the part level, the AFE 83 spreadsheet allows these mitigation measures to be included by the supplier Avionics systems are designed to rigorous high standards of safety and reliability, with growing processing demands of advanced navigation, guidance and communication systems. High functional density and high speed processing to support the growing avionics systems requirements is enabled through the use of COTS electronics with deep sub-micron (<90 nm) integrated circuit (IC) technologies. Airborne environments are generally harsher than ground based applications. Each flight cycle induces vibration combined with a thermal cycle in many electronics, especially those in partially protected areas such as the electronics bay. （28）Flight environments are harsh on electronics and electronic packaging, due to extremes of temperature, frequent thermal cycling, moisture, vibration, pressure, and atmospheric radiation. （29）In aviation applications, reliability needs can be higher as application conditions become worse. The effect of temperature on reliability may be seen in Fig.3. （30）This chart, provided by Xilinx, is an example of one type of result that could come out of the spreadsheet. Here Xilinx has used an internal tool, described in [6], to compute time to an acceptable percent failure for each of three distinct intrinsic wearout failure mechanisms, as well as the net lifetime value considering all three. They then plotted the result versus use temperature.（31）（翻译）.The AFE 83 spreadsheet similarly can provide the user with calculations of reliability at multiple temperatures, which can be convolved with the application’s temperature vs. time profile (e.g., Fig. 4 for commercial avionics) to enable mission analysis or decisions on whether to provide a more protected environment for the electronics. [7] （32）The results of such reliability calculations are intended to provide reasonable inputs to estimates of system-level reliability. （33）Aggregated, part-level reliability parametric data can be used to compute a reliability estimate at the circuit board, line replaceable unit, or subsystem level. This is based on the system designer’s understanding of  the intended operation of the system and the environment in which it is intended to operate. While the proposed methodology is more involved than traditional reliability  estimation methods, it may not be necessary to analyze every device in a given unit.  （34）For many,conservative estimates will be adequate to meet random failure rate targets, and combination of older technology and limited stress will suggest that wearout life is adequate. The practical understanding of the inner relationship between the effects of the wearout failure mechanisms within a part may be controversial. The source of controversy is whether such effects can be treated as competing effects or if it is more accurate to model them as enhancing each other. （35）Asimplifying assumption  in the spreadsheet is that the mechanisms are independent, and that the cumulative failure fractions may be combined numerically without correcting for an interaction between them. Figure 5 shows a sample flow diagram of the decision process an equipment manufacturer may use to determine the application of these analyses or equivalent.  （36）It is important to note that if a component is expected to experience early wearout it must have the dominant wearout mechanisms accounted for in a prediction or the results will be misleading. （37）Figure 6 shows another approach to system level analysis where the traditional random failure reliability prediction (Mean Time Between Failures) is normalized to a Mean Life,so that it can be compared with the Geometric Mean Life the wearout of each small geometry part over the usage profile.[8] The Avionics OEM can then understand whether the small geometry part will be a key driver in their ability to meet the MTBF requirement. EM, TDDB, HCI and NBTI have been identified as dominant failure mechanisms for complementary metal-oxide semiconductors (CMOS) [9]. Models for these mechanisms were developed by various researchers and studied during the AVSI projects AFE 17, 71 and 71s1 and validated [10]. They have also been presented in detail in a previous RAMS paper [11], and are summarized here. The AFE 83 spreadsheet offers models for all four mechanisms, based on equations (1)-(4). T2 is the test temperature in K. These equations differ in some ways from traditional forms [12] to make the independent variables those directly controllable by the IC user, (e.g. for EM we use voltage as a proxy for current density.)  （38）In addition, alternate forms of voltage acceleration models are provided in the spreadsheet,for different technologies.The failure mechanism AF models for TDDB, EM, HCI and NBTI provide an assessment at the feature level within the logic circuitry of an IC.  The effects of these mechanisms become more pronounced as feature sizes shrink and functional density increases. （39）A recent study of field failures of communications technology semiconductors found that failures due to these effects are increasing, in a way similar to Moore’s Law [13] [14]. （40）Models have been developed for NBTI; however as semiconductor feature sizes continue to reduce Positive Bias Temperature Instability (PBTI) may become an issue and models will need to be developed. A traditional approach is to use the Arrhenius model to scale test data to usage environments using empirically derived activation energy factors. （41）It does not consider the relying on a generalized temperaturewere developed by various researchers and studied during the related failure rate model. [15] The models provided in the spreadsheet offer a more detailed failure characterization, the ability to consider multiple failure mechanisms and to directly model voltage and frequency effects as well as thermal effects. 5 RELIABILITY PREDICTIO  OF SEMICO DUCTORS In any practical reliability analysis the best data available is used, and this is also true for use of the AFE 83 spreadsheet.Due to budget and time constraints and possibly the limited availability of COTS vendor data, analyses are sometimes performed with less than ideal data precision. The ideal strategy is to seek the best data first then fall back on other sources. The following is the prioritized order for finding data and analyzing semiconductor microcircuits: 1. Ideal–Supplier provides all the necessary reliability in the usage environments and considering operational stresses 2. Second best – Supplier provides some test information, and the user adjusts it to usage conditions using AFE 83 spreadsheet 3. Third best – If no test data is available, the user runsIn (1)-(4), their own set of tests and uses AFE 83 spreadsheet to are the acceleration perform prediction 4. Fourth option – When no information is available, a factors for TDDB, EM, HCI and NBTI, respectively, prediction can be performed using AFE 83 spreadsheet defaults . The AFE 83 spreadsheet PoF models are used to start the conversation with semiconductor supplier companies about what is needed for the analysis.  A potential approach is to have semiconductor manufacturers take the spreadsheet develop it to accurately model their particular product line, and provide it on a webpage for use by reliability engineers applying their product in an electronic system.