A Modified Three-Phase Four-Wire UPQC Topology

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 9, SEPTEMBER 2013 3555 A Modified Three-Phase Four-Wire UPQC Topology With Reduced DC-Link Voltage Rating Srinivas Bhaskar Karanki, Nagesh Geddada, Student Member, IEEE, Mahesh K. Mishra, Senior Member, IEEE, and B. Kalyan Kumar, Member, IEEE Abstract—The unified power quality conditioner (UPQC) is a custom power device, which mitigates voltage and current-related PQ issues in the power distribution systems. In this paper, a UPQC topology for applications with non-stiff source is proposed. The proposed topology enables UPQC to have a reduced dc-link voltage without compromising its compensation capability. This proposed topology also helps to match the dc-link voltage re- quirement of the shunt and series active filters of the UPQC. The topology uses a capacitor in series with the interfacing inductor of the shunt active filter, and the system neutral is connected to the negative terminal of the dc-link voltage to avoid the requirement of the fourth leg in the voltage source inverter (VSI) of the shunt active filter. The average switching frequency of the switches in the VSI also reduces, consequently the switching losses in the inverters reduce. Detailed design aspects of the series capacitor and VSI parameters have been discussed in the paper. A simulation study of the proposed topology has been carried out using PSCAD simulator, and the results are presented. Experimental studies are carried out on three-phase UPQC prototype to verify the proposed topology. Index Terms—Average switching frequency, dc-link voltage, hybrid topology, non-stiff source, unified power quality condi- tioner (UPQC). I. INTRODUCTION W ITH THE advancement of power electronics and digitalcontrol technology, the renewable energy sources are increasingly being connected to the distribution systems. On the other hand, with the proliferation of the power electronics devices, nonlinear loads and unbalanced loads have degraded the power quality (PQ) in the power distribution network [1]. Custom power devices have been proposed for enhancing the quality and reliability of electrical power. Unified PQ con- ditioner (UPQC) is a versatile custom power device which consists of two inverters connected back-to-back and deals with both load current and supply voltage imperfections. UPQC can simultaneously act as shunt and series active power filters. The series part of the UPQC is known as dynamic voltage restorer (DVR). It is used to maintain balanced, distortion free nominal voltage at the load. The shunt part of the UPQC is known as distribution static compensator (DSTATCOM), and it is used Manuscript received September 19, 2011; revised January 31, 2012, February 9, 2012, and March 30, 2012; accepted May 29, 2012. Date of publication July 6, 2012; date of current version May 2, 2013. This work was supported by the Department of Science and Technology, India, under the project Grant SR/S3/EECE/048/2008. The authors are with the Department of Electrical Engineering, In- dian Institute of Technology Madras, Chennai 600 036, India (e-mail: balu.karanki@gmail.com; nagesh.mselectrical@gmail.com; mahesh@ee.iitm. ac.in; bkalyan@ee.iitm.ac.in). Digital Object Identifier 10.1109/TIE.2012.2206333 to compensate load reactive power, harmonics and balance the load currents thereby making the source current balanced and distortion free with unity power factor. Voltage rating of dc-link capacitor largely influences the compensation performance of an active filter [2]. In general, the dc-link voltage for the shunt active filter has much higher value than the peak value of the line-to-neutral voltage. This is done in order to ensure a proper compensation at the peak of the source voltage. In [3], the authors mentioned about the current distortion limit and loss of control limit, which states that the dc-link voltage should be greater than or equal to √ 6 times the phase voltage of the system for distortion- free compensation. When the dc-link voltage is less than this limit, there is insufficient resultant voltage to drive the currents through the inductances so as to track the reference currents. The primary condition for reactive power compensation is that the magnitude of reference dc-bus capacitor voltage should be higher than the peak voltage at the point of common coupling (PCC) [4]. Due to the aforementioned criteria, many researchers have used a higher value of dc capacitor voltage based on applications [5]–[13]. Similarly, for series active filter, the dc-link voltage is maintained at a value equal to the peak of the line-to-line voltage of the system for proper compensation [14]–[18]. In case of the UPQC, the dc-link voltage requirement for the shunt and series active filters is not the same. Thus, it is a challenging task to have a common dc-link of appropriate rating in order to achieve satisfactory shunt and series compensation. The shunt active filter requires higher dc-link voltage when compared to the series active filter for proper compensation. In order to have a proper compensation for both series and shunt active filter, the researchers are left with no choice rather than to select common dc-link voltage based on shunt active filter requirement. This will result in over rating of the series active filter as it requires less dc-link voltage compared to shunt active filter. Due to this criterion, in literature, a higher dc- link voltage based on the UPQC topology has been suggested [19]–[22]. With the high value of dc-link capacitor, the voltage source inverters (VSIs) become bulky, and the switches used in the VSI also need to be rated for higher value of voltage and current. This in turn increases the entire cost and size of the VSI. To reduce the dc-link voltage storage capacity, few attempts were made in literature. In [23], [24], a hybrid filter has been discussed for motor drive applications. The filter is connected in parallel with diode rectifier and tuned at seventh harmonic frequency. Although an elegant work, the design is specific to the motor drive application, and the reactive power 0278-0046/$31.00 © 2012 IEEE 3556 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 9, SEPTEMBER 2013 Fig. 1. Equivalent circuit of neutral-clamped VSI topology-based UPQC. compensation is not considered, which is an important aspect in UPQC applications. In case of the three-phase four-wire system, neutral-clamped topology is used for UPQC [25], [26]. This topology enables the independent control of each leg of both the shunt and series in- verters, but it requires capacitor voltage balancing [27]. In [21], four-leg VSI topology for shunt active filter has been proposed for three-phase four-wire system. This topology avoids the voltage balancing of the capacitor, but the independent control of the inverter legs is not possible. To overcome the problems associated with the four-leg topology, in [28], [29], the authors proposed a T-connected transformer and three-phase VSC- based DSTATCOM. However, this topology increases the cost and bulkiness of the UPQC because of the presence of extra transformer. In this paper, a UPQC topology with reduced dc-link voltage is proposed. The topology consists of capacitor in series with the interfacing inductor of the shunt active filter. The series capacitor enables reduction in dc-link voltage requirement of the shunt active filter and simultaneously compensating the re- active power required by the load, so as to maintain unity power factor, without compromising its performance. This allows us to match the dc-link voltage requirements of the series and shunt active filters with a common dc-link capacitor. Further, in this topology, the system neutral is connected to the negative terminal of the dc bus. This will avoid the requirement of the fourth leg in VSI of the shunt active filter and enables independent control of each leg of the shunt VSI with single dc capacitor. The simulation studies are carried out using PSCAD simulator, and detailed results are presented in the paper. A prototype of three-phase UPQC is developed in the laboratory to verify the proposed concept, and the detailed results are presented in this paper. II. CONVENTIONAL AND PROPOSED TOPOLOGIES OF UPQC In this section, the conventional and proposed topology of the UPQC are discussed in detail. Fig. 1 shows the power circuit of the neutral-clamped VSI topology-based UPQC which is considered as the conventional topology in this study. Even though this topology requires two dc storage devices, each leg of the VSI can be controlled independently, and tracking is smooth with less number of switches when compared to other VSI topologies [27]. In this figure, vsa, vsb, and vsc are source voltages of phases a, b, and c, respectively. Similarly, vta, vtb, and vtc are terminal voltages. The voltages vdvra, vdvrb, and vdvrc are injected by the series active filter. The three- phase source currents are represented by isa, isb, and isc, load currents are represented by ila, ilb, and ilc. The shunt active filter currents are denoted by ifa, ifb, ifc, and iln represents the current in the neutral leg. Ls and Rs represent the feeder inductance and resistance, respectively. The interfacing induc- tance and resistance of the shunt active filter are represented by Lf and Rf , respectively, and the interfacing inductance and filter capacitor of the series active filter are represented by Lse and Cse, respectively. The load constituted of both linear and nonlinear loads as shown in this figure. The dc-link capacitors and voltages across them are represented by Cdc1 = Cdc2 = Cdc and Vdc1 = Vdc2 = Vdc, respectively, and the total dc-link voltage is represented by Vdbus(Vdc1 + Vdc2 = 2Vdc). In this conventional topology, the voltage across each common dc-link capacitor is chosen as 1.6 times the peak value of the source voltages as given in [27]. Fig. 2 represents the equivalent circuit of the proposed VSI topology for UPQC compensated system. In this topology, the system neutral has been connected to the negative terminal of the dc bus along with the capacitor Cf in series with the interfacing inductance of the shunt active filter. This topology is referred to as modified topology. The passive capacitor Cf has the capability to supply a part of the reactive power required by the load, and the active filter will compensate the balance reactive power and the harmonics present in the load. The ad- dition of capacitor in series with the interfacing inductor of the shunt active filter will significantly reduce the dc-link voltage requirement and consequently reduces the average switching frequency of the switches. This concept will be illustrated with analytic description in the following section. The reduction in KARANKI et al.: MODIFIED THREE-PHASE FOUR-WIRE UPQC TOPOLOGY WITH REDUCED DC-LINK VOLTAGE RATING 3557 Fig. 2. Equivalent circuit of proposed VSI topology for UPQC compensated system (modified topology). the dc-link voltage requirement of the shunt active filter enables us to the match the dc-link voltage requirement with the series active filter. This topology avoids the over rating of the series active filter of the UPQC compensation system. The design of the series capacitor Cf and the other VSI parameters have significant effect on the performance of the compensator. These are given in the next section. This topology uses a single dc ca- pacitor unlike the neutral-clamped topology and consequently avoids the need of balancing the dc-link voltages. Each leg of the inverter can be controlled independently in shunt active filter. Unlike the topologies mentioned in the literature [21], [25], [26], [30], this topology does not require the fourth leg in the shunt active filter for three-phase four-wire system. The performance of this topology will be explained in detailed in the following section. III. DESIGN OF VSI PARAMETERS The parameters of the VSI need to be designed carefully for better tracking performance. The important parameters that need to be taken into consideration while designing conven- tional VSI are Vdc, Cdc, Lf , Lse, Cse, and switching frequency (fsw). The design details of the VSI parameters for the shunt and series active filter are given in [31], [32]. Based on the following equations, the parameters of the VSIs are chosen for study. A. Design of Shunt Active Filter VSI Parameters Consider the active filter is connected to an X kVA system and deals with 0.5X kVA and 2X kVA handling capability under transient conditions for n cycles. During transient, with an increase in system kVA load, the voltage across each dc-link capacitor (Vdc) decreases and vice versa. Allowing a maximum of 25% variation in Vdc during transient, the differential energy (ΔEc) across Cdc is given by ΔEc = Cdc [ (1.125Vdc) 2 − (0.875Vdc)2 ] 2 . (1) The change in system energy (ΔEs) for a load change from 2X kVA to 0.5X kVA is ΔEs = (2X −X/2)nT. (2) Equating (1) and (2), the dc-link capacitor value is given by Cdc = 2(2X −X/2)nT (1.125Vdc)2 − (0.875Vdc)2 . (3) where, Vm is the peak value of the source voltage, X is the kVA rating of the system, n is number of cycles, and T time period of each cycle. An empirical study has been carried out for various values of interfacing inductance values with the variation of the dc-link voltage in [31], with Vdc = mVm, and it is found that m = 1.6 gives fairly good switching performance of the VSI. The approximate relationship between m and minimum (fswmin), maximum switching frequency (fswmax) is obtained by analysis of the VSI in [31], and this is given below. For switching frequency variation approximately from 6 kHz to 10 kHz, the value of m is 1.58, which is taken as 1.6 in the study m = 1√ 1− fswmin/fswmax . (4) Based on this, the shunt interfacing inductance has been derived taking into consideration of the maximum switching frequency and is given below [31] Lf = mVm 4h1fswmax (5) where h1 = √ k1 k2 (2m2 − 1) 4m2 fswmax (6) where, h1 is the hysteresis band limit, k1 and k2 are proportion- ality constants. 3558 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 9, SEPTEMBER 2013 B. Design of Series Active Filter VSI Parameters In order to make the series active filter system a first-order system, a resistor is added in series with the filter capacitor, referred as switching band resistor (Rsw) [32]. The rms value of the capacitor current can be expressed as Ise = √ I2inv − I2l . Iinv is the series inverter current rating and Il is the load current. The capacitor branch current is divided into two components—a fundamental current Ise1, correspond- ing to the fundamental reference voltage (Vref1) and a switching frequency current Isw, corresponding to the band voltage (Vsw). The DVR voltage and the current of the capacitor are given by Vdvr = √ V 2ref1 + V 2 sw Ise = √ I2se1 + I 2 sw Vsw = IswRsw = h2√ 3 Vref1 = Ise1Xse1 = Ise1 2πf1Cse (7) where h2 is the hysteresis band voltage. The resistance (Rsw) and the capacitance (Cse) values are expressed in terms of band voltage vsw and rated references voltage (Vref1), respectively, and are given by Rsw = h2 Isw √ 3 Cse = Ise1 Vref12πf1 . (8) The interfacing inductor Lse has been designed based on the switching frequency of the series active filter and is given by Lse = (Vbus)Rsw 4fswmaxh2 (9) where Vbus is the total dc-link voltage across both the dc-link capacitors. A design example is illustrated for a rated voltage of 230 V line to neutral and the dc-link voltage reference (Vdcref) of the conventional VSI topology has been taken as 1.6 Vm for each capacitor [27], [31]. The hysteresis band (h1) is taken as 0.5 A. From (5), the interfacing inductance (Lf ) is computed to be 26 mH. The base kVA rating of the system is taken as 5 kVA. Using (3), Cdc is computed and found to be 2200 μF. The rated series VSI voltage is chosen as 50% of the rated voltage, i.e., the maximun injection capacity of the series active filter is 115 V. The hysteresis band (h2) for series active filter is taken as 3% of the rated voltage, i.e., 6.9 V. The maximun switching frequency of the IGBT-based inverter is taken as 10 kHz. The series active filter current rating is choosen as 8 A and the rated load current as 7 A. Using the (7)–(9), the filter capaciotr Cse, the band resistor Rsw and interfacing inductance Lse are calculated to be 80 μF, 1.5 Ω, and 5 mH, respectively. The system parameters are given in Table I for the conventional VSI topology. TABLE I SYSTEM PARAMETERS C. Design of Cf for the Proposed VSI Topology The design of the Cf depends upon the value to which the dc-link voltage is reduced. In general, loads with only nonlinear components of currents are very rare, and most of the electrical loads are combination of the linear inductive and nonlinear loads. Under these conditions, the proposed topology will work efficiently. The design of the value of Cf is carried out at the maximum load current, i.e., with the minimum load impedance to ensure that the designed Cf will perform satisfactorily at all other loading conditions. If Smax is the maximum kVA rating of a system and Vbase is the base voltage of the system, then the minimum impedance in the system is given as Zmin = V 2base Smax = |Rl + jXl| (say). (10) In order to achieve the unity power factor, the shunt active filter current needs to supply the required reactive component of the load current, i.e., the fundamental imaginary part of the filter current should be equal to the imaginary part of the load current. The filter current and load current in a particular phase are given below Ifilter = Vinv1 − Vl1 Rf + j(Xlf −Xcf ) (11) I load = Vl1 Rl + jXl (12) where, Xlf = 2πfLf , Xl = 2πfLl, Xcf = 1/2πfCf , and f is the supply frequency of fundamental voltage. Neglecting the interfacing resistance and equating the imag- inary parts of the the above equations gives (13) Vl1Xl R2l +X 2 l = Vinv1 − Vl1 (Xlf −Xcf )2 (Xlf −Xcf ) (13) where, Vinv1 and Vl1 are the line to neutral rms voltage of the inverter and the PCC voltage at the fundamental frequency, respectively. The fundamental component of inverter voltage in terms of dc-link voltage is described in [33], as given below Vinv1 = 0.612Vdc 2 √ 3 . (14) KARANKI et al.: MODIFIED THREE-PHASE FOUR-WIRE UPQC TOPOLOGY WITH REDUCED DC-LINK VOLTAGE RATING 3559 In general, if the filter current (If ) flows from the inverter terminal to the PCC, the voltage at the inverter terminal should be at a higher potential. Due to this reason, in conventional VSI topologies, the dc-link voltage is maintained higher than the voltage at the PCC. Equations (15) and (16) give the KVL along the filter branch for conventional topology and the proposed modified topology, respectively uVdc − vl =Lf dif dt +Rf if (15)( uVdc − 1 Cf ∫ ifdt ) − vl =Lf dif dt +Rf if (uVdc − vcf )− vl =Lf dif dt +Rf if (16) where, u attains values of 1 or −1 depending on the switching of the inverter. In (16), the fundamental voltage across the capacitor (vcf1) adds to the inverter terminal voltage (uVdc) when the load is inductive in nature. This is because, when the load is inductive in nature, the fundamental of the filter current leads the voltage at the PCC by 90◦ for reactive power compensation, and thus the fundamental voltage across the capacitor again lags the fundamental filter current by 90◦. Therefore, the fundamental voltage across the capacitor will be in phase opposition to the voltage at the PCC. Thus, the fundamental voltage across the capacitor adds to the inverter terminal voltage. This allows us to rate the dc-link voltage at lower value than conventional design. The designer has a choice to choose the value of dc-link voltage to be reduced, such that the LC filter in the active filter leg of each phase offers minimum impedance to the fundamental fre