ADC0804

������ ����� ���� � ADC0803/0804 CMOS 8-bit A/D converters Product data Supersedes data of 2001 Aug 03 2002 Oct 17 INTEGRATED CIRCUITS Philips Semiconductors Product data ADC0803/0804CMOS 8-bit A/D converters 22002 Oct 17 DESCRIPTION The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus. The differential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. Additionally, the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution. FEATURES • Compatible with most microprocessors • Differential inputs • 3-State outputs • Logic levels TTL and MOS compatible • Can be used with internal or external clock • Analog input range 0 V to VCC • Single 5 V supply • Guaranteed specification with 1 MHz clock PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 15 D, N PACKAGES CS RD WR INTR CLK IN VIN(+) VIN(–) A GND VREF/2 D GND VCC CLK R D0 D1 D2 D3 D4 D5 D6 D7 TOP VIEW SL00016 Figure 1. Pin configuration APPLICATIONS • Transducer-to-microprocessor interface • Digital thermometer • Digitally-controlled thermostat • Microprocessor-based monitoring and control systems ORDERING INFORMATION DESCRIPTION TEMPERATURERANGE ORDER CODE TOPSIDE MARKING DWG # 20-pin plastic small outline (SO) package 0 to 70 °C ADC0803CD, ADC0804CD ADC0803-1CD, ADC0804-1CD SOT163-1 20-pin plastic small outline (SO) package –40 to 85 °C ADC0803LCD, ADC0804LCD ADC0803-1LCD, ADC0804-1LCD SOT163-1 20-pin plastic dual in-line package (DIP) 0 to 70 °C ADC0803CN, ADC0804CN ADC0803-1CN, ADC0804-1CN SOT146-1 20-pin plastic dual in-line package (DIP) –40 to +85 °C ADC0803LCN, ADC0804LCN ADC0803-1LCN, ADC0804-1LCN SOT146-1 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER CONDITIONS RATING UNIT VCC Supply voltage 6.5 V Logic control input voltages –0.3 to +16 V All other input voltages –0.3 to (VCC +0.3) V Tamb Operating temperature range ADC0803LCD/ADC0804LCD –40 to +85 °C ADC0803LCN/ADC0804LCN –40 to +85 °C ADC0803CD/ADC0804CD 0 to +70 °C ADC0803CN/ADC0804CN 0 to +70 °C Tstg Storage temperature –65 to +150 °C Tsld Lead soldering temperature (10 seconds) 230 °C PD Maximum power dissipation1 Tamb = 25 °C (still air) N package 1690 mW D package 1390 mW NOTE: 1. Derate above 25 °C, at the following rates: N package at 13.5 mW/°C; D package at 11.1 mW/°C. Philips Semiconductors Product data ADC0803/0804CMOS 8-bit A/D converters 2002 Oct 17 3 BLOCK DIAGRAM M VIN (+) VIN (–) 76 + – LADDER AND DECODER + – AUTO ZERO COMPARATOR VREF/2 A GND 9 8 VCC 20 10 D GND WR CS RD 3 1 2 SAR 8–BIT SHIFT REGISTER INTR FF CLOCK OUTPUT LATCHES LE OE D7 (MSB) (11) D6 (12) D5 (13) D4 (14) D3 (15) D2 (16) D1 (17) D0 (LSB) (18) INTR CLK IN CLK R S R Q 5 4 19 SL00017 Figure 2. Block diagram Philips Semiconductors Product data ADC0803/0804CMOS 8-bit A/D converters 2002 Oct 17 4 DC ELECTRICAL CHARACTERISTICS VCC = 5.0 V, fCLK = 1 MHz, Tmin ≤ Tamb ≤ Tmax, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT ADC0803 relative accuracy error (adjusted) Full-Scale adjusted 0.50 LSB ADC0804 relative accuracy error (unadjusted) VREF/2 = 2.500 VDC 1 LSB RIN VREF/2 input resistance3 VCC = 0 V2 400 680 Ω Analog input voltage range3 –0.05 VCC+0.05 V DC common-mode error Over analog input voltage range 1/16 1/8 LSB Power supply sensitivity VCC = 5V ±10%1 1/16 LSB Control inputs VIH Logical “1” input voltage VCC = 5.25 VDC 2.0 15 VDC VIL Logical “0” input voltage VCC = 4.75 VDC 0.8 VDC IIH Logical “1” input current VIN = 5 VDC 0.005 1 µADC IIL Logical “0” input current VIN = 0 VDC –1 –0.005 µADC Clock in and clock R VT+ Clock in positive-going threshold voltage 2.7 3.1 3.5 VDC VT– Clock in negative-going threshold voltage 1.5 1.8 2.1 VDC VH Clock in hysteresis (VT+)–(VT–) 0.6 1.3 2.0 VDC VOL Logical “0” clock R output voltage IOL = 360 µA, VCC = 4.75 VDC 0.4 VDC VOH Logical “1” clock R output voltage IOH = –360 µA, VCC = 4.75 VDC 2.4 VDC Data output and INTR VOL Logical “0” output voltage Data outputs IOL = 1.6 mA, VCC = 4.75 VDC 0.4 VDC INTR outputs IOL = 1.0 mA, VCC = 4.75 VDC 0.4 VDC VO Logical “1” output voltage IOH = –360 µA, VCC = 4.75 VDC 2.4 V CVOH Logical “1” output voltage IOH = –10 µA, VCC = 4.75 VDC 4.5 VDC IOZL 3-State output leakage VOUT = 0 VDC, CS = logical “1” –3 µADC IOZH 3-State output leakage VOUT = 5 VDC, CS = logical “1” 3 µADC ISC +Output short-circuit current VOUT = 0 V, Tamb = 25 °C 4.5 12 mADC ISC –Output short-circuit current VOUT = VCC, Tamb = 25 °C 9.0 30 mADC ICC Power supply current fCLK = 1 MHz, VREF/2 = OPEN, CS = Logical “1”, Tamb = 25 °C 3.0 3.5 mA NOTES: 1. Analog inputs must remain within the range: –0.05 ≤ VIN ≤ VCC + 0.05 V. 2. See typical performance characteristics for input resistance at VCC = 5 V. 3. VREF/2 and VIN must be applied after the VCC has been turned on to prevent the possibility of latching. Philips Semiconductors Product data ADC0803/0804CMOS 8-bit A/D converters 2002 Oct 17 5 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TO FROM TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TO FROM TEST CONDITIONS Min Typ Max UNIT Conversion time fCLK = 1 MHz1 66 73 µs fCLK Clock frequency1 0.1 1.0 3.0 MHz Clock duty cycle1 40 60 % CR Free-running conversion rate CS = 0, fCLK = 1 MHzINTR tied to WR 13690 conv/s tW(WR)L Start pulse width CS = 0 30 ns tACC Access time Output RD CS = 0, CL = 100 pF 75 100 ns t1H, t0H 3-State control Output RD CL = 10 pF, RL = 10 kΩ See 3-State test circuit 70 100 ns tW1, tR1 INTR delay INTR WD or RD 100 150 ns CIN Logic input=capacitance 5 7.5 pF COUT 3-State output capacitance 5 7.5 pF NOTE: 1. Accuracy is guaranteed at fCLK = 1 MHz. Accuracy may degrade at higher clock frequencies. FUNCTIONAL DESCRIPTION These devices operate on the Successive Approximation principle. Analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator [ VIN(+)–VIN(–) ] matches the voltage from the decoder. After all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. Conversion begins with the arrival of a pulse at the WR input if the CS input is low. On the High-to-Low transition of the signal at the WR or the CS input, the SAR is initialized, the shift register is reset, and the INTR output is set high. The A/D will remain in the reset state as long as the CS and WR inputs remain low. Conversion will start from one to eight clock periods after one or both of these inputs makes a Low-to-High transition. After the conversion is complete, the INTR pin will make a High-to-Low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion result. A read (RD) operation (with CS low) will clear the INTR line and enable the output latches. The device may be run in the free-running mode as described later. A conversion in progress can be interrupted by issuing another start command. Digital Control Inputs The digital control inputs (CS, WR, RD) are compatible with standard TTL logic voltage levels. The required signals at these inputs correspond to Chip Select, START Conversion, and Output Enable control signals, respectively. They are active-Low for easy interface to microprocessor and microcontroller control buses. For applications not using microprocessors, the CS input (Pin 1) can be grounded and the A/D START function is achieved by a negative-going pulse to the WR input (Pin 3). The Output Enable function is achieved by a logic low signal at the RD input (Pin 2), which may be grounded to constantly have the latest conversion present at the output. ANALOG OPERATION Analog Input Current The analog comparisons are performed by a capacitive charge summing circuit. The input capacitor is switched between VIN(+)4 and VIN(–), while reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the most recent total value set by the successive approximation register. The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance is switched through the analog differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN(–) input. These transient currents occur at the leading edge of the internal clock pulses. They decay rapidly so do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period. Input Bypass Capacitors and Source Resistance Bypass capacitors at the input will average the charges mentioned above, causing a DC and an AC current to flow through the output resistance of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input at full scale. This current can be a few microamps, so bypass capacitors should NOT be used at the analog inputs of the VREF/2 input for high resistance sources (> 1 kΩ). If input bypass capacitors are desired for noise filtering and a high source resistance is desired to minimize capacitor size, detrimental effects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place. This is possible because the magnitude of the input current is a precise linear function of the differential voltage. Philips Semiconductors Product data ADC0803/0804CMOS 8-bit A/D converters 2002 Oct 17 6 Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (< 1 kΩ) for a passive RC section or add an op amp active filter (low pass). For applications with source resistances at or below 1 kΩ, a 0.1 µF bypass capacitor at the inputs will prevent pickup due to series lead inductance or a long wire. A 100 Ω series resistor can be used to isolate this capacitor (both the resistor and capacitor should be placed out of the feedback loop) from the output of the op amp, if used. Analog Differential Voltage Inputs and Common-Mode Rejection These A/D converters have additional flexibility due to the analog differential voltage input. The VIN(–) input (Pin 7) can be used to subtract a fixed voltage from the input reading (tare correction). This is also useful in a 4/20 mA current loop conversion. Common-mode noise can also be reduced by the use of the differential input. The time interval between sampling VIN(+) and VIN(–) is 4.5 clock periods. The maximum error due to this time difference is given by: V(max) = (VP) (2fCM) (4.5/fCLK), where: V = error voltage due to sampling delay VP = peak value of common-mode voltage fCM = common mode frequency For example, with a 60 Hz common-mode frequency, fcm, and a 1 MHz A/D clock, fCLK, keeping this error to 1/4 LSB (about 5 mV) would allow a common-mode voltage, VP, which is given by: VP � [V(max) (fCLK) (2fCM)(4.5) or VP � (5 x 10�3) (104) (6.28) (60) (4.5) � 2.95V The allowed range of analog input voltages usually places more severe restrictions on input common-mode voltage levels than this, however. An analog input span less than the full 5 V capability of the device, together with a relatively large zero offset, can be easily handled by use of the differential input. (See Reference Voltage Span Adjust). Noise and Stray Pickup The leads of the analog inputs (Pins 6 and 7) should be kept as short as possible to minimize input noise coupling and stray signal pick-up. Both EMI and undesired digital signal coupling to these inputs can cause system errors. The source resistance for these inputs should generally be below 5 kΩ to help avoid undesired noise pickup. Input bypass capacitors at the analog inputs can create errors as described previously. Full scale adjustment with any input bypass capacitors in place will eliminate these errors. Reference Voltage For application flexibility, these A/D converters have been designed to accommodate fixed reference voltages of 5V to Pin 20 or 2.5 V to Pin 9, or an adjusted reference voltage at Pin 9. The reference can be set by forcing it at VREF/2 input, or can be determined by the supply voltage (Pin 20). Figure 6 indicates how this is accomplished. Reference Voltage Span Adjust Note that the Pin 9 (VREF/2) voltage is either 1/2 the voltage applied to the VCC supply pin, or is equal to the voltage which is externally forced at the VREF/2 pin. In addition to allowing for flexible references and full span voltages, this also allows for a ratiometric voltage reference. The internal gain of the VREF/2 input is 2, making the full-scale differential input voltage twice the voltage at Pin 9. For example, a dynamic voltage range of the analog input voltage that extends from 0 to 4 V gives a span of 4 V (4–0), so the VREF/2 voltage can be made equal to 2 V (half of the 4 V span) and full scale output would correspond to 4 V at the input. On the other hand, if the dynamic input voltage had a range of 0.5 to 3.5 V, the span or dynamic input range is 3 V (3.5–0.5). To encode this 3 V span with 0.5 V yielding a code of zero, the minimum expected input (0.5 V, in this case) is applied to the VIN(–) pin to account for the offset, and the VREF/2 pin is set to 1/2 the 3 V span, or 1.5 V. The A/D converter will now encode the VIN(+) signal between 0.5 and 3.5 V with 0.5 V at the input corresponding to a code of zero and 3.5 V at the input producing a full scale output code. The full 8 bits of resolution are thus applied over this reduced input voltage range. The required connections are shown in Figure 7. Operating Mode These converters can be operated in two modes: 1) absolute mode 2) ratiometric mode In absolute mode applications, both the initial accuracy and the temperature stability of the reference voltage are important factors in the accuracy of the conversion. For VREF/2 voltages of 2.5 V, initial errors of ±10 mV will cause conversion errors of ±1 LSB due to the gain of 2 at the VREF/2 input. In reduced span applications, the initial value and stability of the VREF/2 input voltage become even more important as the same error is a larger percentage of the VREF/2 nominal value. See Figure 8. In ratiometric converter applications, the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A/D converter, and, therefore, cancels out in the final digital code. See Figure 9. Generally, the reference voltage will require an initial adjustment. Errors due to an improper reference voltage value appear as full-scale errors in the A/D transfer function. ERRORS AND INPUT SPAN ADJUSTMENTS There are many sources of error in any data converter, some of which can be adjusted out. Inherent errors, such as relative accuracy, cannot be eliminated, but such errors as full-scale and zero scale offset errors can be eliminated quite easily. See Figure 7. Zero Scale Error Zero scale error of an A/D is the difference of potential between the ideal 1/2 LSB value (9.8 mV for VREF/2=2.500 V) and that input voltage which just causes an output transition from code 0000 0000 to a code of 0000 0001. If the minimum input value is not ground potential, a zero offset can be made. The converter can be made to output a digital code of 0000 0000 for the minimum expected input voltage by biasing the VIN(–) input to that minimum value expected at the VIN(–) input to that minimum value expected at the VIN(+) input. This uses the differential mode of the converter. Any offset adjustment should be done prior to full scale adjustment. Philips Semiconductors Product data ADC0803/0804CMOS 8-bit A/D converters 2002 Oct 17 7 Full Scale Adjustment Full scale gain is adjusted by applying any desired offset voltage to VIN(–), then applying the VIN(+) a voltage that is 1-1/2 LSB less than the desired analog full-scale voltage range and then adjusting the magnitude of VREF/2 input voltage (or the VCC supply if there is no VREF/2 input connection) for a digital output code which just changes from 1111 1110 to 1111 1111. The ideal VIN(+) voltage for this full-scale adjustment is given by: VIN(�) � VIN(�)� 1.5 x VMAX� VMIN 255 where: VMAX = high end of analog input range (ground referenced) VMIN = low end (zero offset) of analog input (ground referenced) CLOCKING OPTION The clock signal for these A/Ds can be derived from external sources, such as a system clock, or self-clocking can be accomplished by adding an external resistor and capacitor, as shown in Figure 11. Heavy capacitive or DC loading of the CLK R pin should be avoided as this will disturb normal converter operation. Loads less than 50pF are allowed. This permits driving up to seven A/D converter CLK IN pins of this family from a single CLK R pin of one converter. For larger loading of the clock line, a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the CLK R pin. Restart During a Conversion A conversion in process can be halted and a new conversion began by bringing the CS and WR inputs low and allowing at least one of them to go high again. The output data latch is not updated if the conversion in progress is not completed; the data from the previously completed conversion will remain in the output data latches until a subsequent conversion is completed. Continuous Conversion To provide continuous conversion of input data, the CS and RD inputs are grounded and INTR output is tied to the WR input. This INTR/WR connection should be momentarily forced to a logic low upon power-up to insure circuit operation. See Figure 10 for one way to accomplish this. DRIVING THE DATA BUS This CMOS A/D converter, like MOS microprocessors and memories, will require a bus driver when the total capacitance of the data bus gets large. Other circuitry tied to the data bus will add to the total capacitive loading, even in the high impedance mode. There are alternatives in handling this problem. The capacitive loading of the data bus slows down the response time, although DC specifications are still met. For systems with a relatively low CPU clock frequency, more time is available in which to establish proper logic levels on the bus, allowing higher capacitive loads to be driven (see Typical Performance Characteristics). At higher CPU clock frequencies, time can be extended for I/O reads (and/or writes) by inserting wait states (8880) or using clock-extending circuits (6800, 8035). Finally, if time is critical and capacitive loading is high, external bus drivers must be used. These can be 3-State buffers (low power Schottky is recommended, such as the N74LS240 series) or special higher current drive products designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended as the PNP input offers low loading of the A/D output, allowing better response time. POWER SUPPLIES Noise spikes on the VCC line can cause conversion errors as the internal comparator will respond to them. A low inductance filter capacitor should be used close to the converter VCC pin and values of 1 µF or greater are recommended. A separate 5 V regulator for the converter (and other 5 V linear circuitry) will greatly reduce digital noise on the VCC supply and the attendant pro