DC Design Compiler 综合脚本命令及参考模板

DC Design Compiler 综合脚本命令及参考模板DC Design Compiler 综合脚本命令及参考模板 Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的 Constraints 和 Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。 Invoking Design Compiler Unix% design_vision # Interactive GUI, WLM mode Unix% design_vi...

DC Design Compiler 综合脚本命令及参考模板 Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的 Constraints 和 Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。 Invoking Design Compiler Unix% design_vision # Interactive GUI, WLM mode Unix% design_vision –topographical # Interactive GUI, Topographical mode Unix% dc_shell-t # Interactive shell, WLM mode Unix% dc_shell-t –topographical # Interactive shell, Topographical mode Unix% dc_shell-t –f RUN.tcl | tee –i my.log # Batch mode .synopsys_dc.setup set search_path “$search_path libs cons unmapped rtl” set synthetic_library dw_foundation.sldb set target_library 65nm.db set link_library “* $target_library $synthetic_library IP.db” set symbol_library 65nm.sdb define_design_lib WORK –path ./work set_svf set_vsdc history keep 200 set sh_enable_page_mode false set cache_write . set cache_read $cache_write suppress_message {LINT-28 LINT-32 LINT-33 UID-401} set alib_library_analysis_path [get_unix_variable HOME] alias h history alias rc “report_constraint -all_violators” TCL Commands and Constructs set PER 2.0 # Define a variable and its value echo $PER # Variable substitution , 2.0 set MARG 0.95 expr $PER * $MARG # expr: *, /, +, -, >, <, =, <=, >= set pci_ports [get_ports A] # Imbedded command set pci_ports [get_ports “Y??M Z*”] # Wildcards echo “Effctv P = \ # Soft quotes , 1.9 [expr $PERIOD * $MARGIN]” echo {Effctv P = \ # Hard quotes [expr $PERIOD * $MARGIN]} # , Effctv P = [expr $PER * $MARG] # Comment line set COMMENT in_line; # In-line comment set MY_DESIGNS {B1.v ... B26.v} # foreach loop foreach DESIGN $MY_DESIGNS { read_verilog $DESIGN } for {set i 1} {$i < 27} {incr i} { # for loop read_verilog BLOCK_$i.v } Helpful UNIX-like DC-shell commands pwd cd ls history !! !7 !report sh printenv get_unix_variable ARCH Constraints reset_design set_max_area 0 create_clock -period 2 –name Main_Clk [get_ports Clk1] create_clock –period 2.5 –waveform {2 3.5} [get_ports Clk2] create_clock –period 3.5 –name V_Clk; # VIRTUAL clock set_clock_uncertainty –setup 0.14 [get_clocks *] set_clock_uncertainty –setup 0.21 –from [get_clocks Main_Clk] –to [get_clocks Clk2] set_clock_latency –max 0.6 [get_clocks Main_Clk] set_clock_latency –source –max 0.3 [get_clocks Main_Clk] set_clock_transition 0.08 [get_clocks Main_Clk] set_input_delay -max 0.6 -clock Main_Clk [all_inputs] set_input_delay –max 0.3 –clock Clk2 –clock_fall –add_delay [get_ports “B E”] set_input_delay -max 0.5 -clock –network_latency_included V_Clk [get_ports “A C F”] set_output_delay -max 0.8 -clock –source_latency_included Main_Clk [all_outputs] set_output_delay -max 1.1 -clock V_Clk [get_ports “OUT2 OUT7] set_max_capacitance 1.2 [all_inputs] set_load 0.080 [all_outputs] set_load [expr [load_of slow_proc/NAND2_3/A] * 4] [get_ports OUT3] set_load 0.12 [all_inputs] set_input_transition 0.12 [remove_from_collection [all_inputs][get_ports B]] set_driving_cell –lib_cell FD1 –pin Q [get_ports B] set_operating_conditions –max WCCOM set auto_wire_load_selection false set_wire_load_model –name 1.6MGates set_wire_load_mode enclosed set_wire_load_model –name 200KGates [get_designs “SUB1 SUB2”] set_wire_load_model –name 3.2MGates [get_ports IN_A] set_port_fanout_number 8 [get_ports IN_A] set_false_path -from [get_clocks Asynch_CLKA] -to [get_clocks Asynch_CLKB] set_multicycle_path –setup 4 –from –from A_reg -through U_Mult/Out –to B_reg set_multicycle_path –hold 3 –from –from A_reg -through U_Mult/Out –to B_reg set_isolate_ports –type inverter [all_outputs] set_ideal_network [get_ports reset* select*] set_ideal_network [get_pins FF_SET_reg/Q] set_ideal_network –no_propagate [get_nets CTRL] set_ideal_latency 1.4 [get_ports reset* select*] set_ideal_transition 0.5 [get_pins FF_SET_reg/Q] set_scan_configuration -style Checking and Removing Constraints and Directives report_clock; report_clock -skew report_design report_port –verbose report_wire_load report_path_groups report_timing_requirements (–ignored) report_auto_ungroup report_isolate_ports write_script –output check_timing reset_path –from FF1_reg remove_clock remove_clock_transition remove_clock_uncertainty remove_input_delay remove_output_delay remove_driving_cell remove_wire_load_model Syntax Checking Unix% dcprocheck constr_file.con Physical Constraints – Topographical Mode set_aspect_ratio set_utilization set_placement_area set_rectilinear_outline set_port_side set_port_location set_cell_location create_placement_keepout Misc. Reports # Generate A library report file read_db library_file.db list_libs redirect –file reports/lib.rpt {report_lib } report_hierarchy [-noleaf] # Arithmetic implementation and # resource-sharing info report_resources # List area for all cells in the design report_cell [get_cells –hier *] Run Script read_verilog {A.v B.v TOP.v} or read_vhdl {A.vhd B.vhd TOP.vhd} or read_ddc MY_TOP.ddc or acs_read_hdl MY_TOP or analyze –format verilog {A.v B.v TOP.v} elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16” current_design MY_TOP link if {[check_design] ==0} { echo “Check Design Error” exit # Exits DC if a check-design error is encountered } # Continue if NO problems encountered write –f ddc –hier –out unmappedd/TOP.ddc redirect –tee –file reports/precompile.rpt {source –echo -verbose TOP.con} redirect –append –tee –file reports/precompile.rpt {check_timing} source or # Source tcl constraints, if available, or extract_physical_constraints # Extract and apply from an existing # DEF floorplan file group_path -name CLK1 -critical_range <10% of CLK1 Period> –weight 5 group_path -name CLK2 -critical_range <10% of CLK2 Period> –weight 2 group_path –name INPUTS –from [all_inputs] group_path –name OUTPUTS –to [all_outputs] group_path –name COMBO –from [all_inputs] –to [all_outputs] set_fix_multiple_port_nets –all –buffer_constants ********************************************************* * * * Insert Expert, Ultra or ACS compile flow here * * * ********************************************************* check_design report_constraint –all_violators report_timing –delay –to –from –through –input_pins –max_paths \ –nworst –nets –cap –sig –group report_area report_qor set verilogout_no_tri true change_names –rule verilog –hier write –f verilog –hier –out mapped/TOP.v write –f ddc –hier –out mapped/TOP.ddc write_sdc TOP.sdc write_scan_def –out TOP_scan.def write_physical_constraints –output TOP_PhysConstr.tcl exit Object Retrieval and Manipulation (Collection Commands) get_ports, get_pins, get_designs get_cells, get_nets, get_clocks get_nets –of_objects [get_pins FF1_reg/Q] get_libs get_lib_cells get_lib_pins all_inputs, all_outputs, all_clocks, all_registers all_connected all_fanin, all_fanout all_ideal_nets set pci_ports [get_ports pci_*] echo $pci_ports # , _sel184 query_objects $pci_ports # , {pci_1 pci_2 ...} get_object_name $pci_ports # , pci_1 pci_2 ... sizeof_collection $pci_ports # , 37 set pci_ports [add_to_collection $pci_ports \ [get_ports CTRL*]] set all_inputs_except_clk [remove_from_collection \ [all_inputs] [get_ports CLK]] compare_collections index_collection sort_collection foreach_in_collection my_cells [get_cells -hier * \ -filter “is_hierarchical == true”] { echo “Instance [get_object_name $cell] is hierarchical” } # Filtering operators: ==, !=, >, <, >=, <=, =~, !~ filter_collection [get_cells *] “ref_name =~ AN*” get_cells * -filter “dont_touch == true” get_clocks * -filter “period < 10” # List all cell attributes and redirect output to a file redirect –file cell_attr \ {list_attributes –application –class cell} # Grep the file for cell attributes starting with dont_ UNIX% grep dont_ cell_attr | more # List the value of the attribute dont_touch get_attribute dont_touch Ultra Compile Flow - Topographical or WLM Mode Ultra + DesignWare and DFTC licenses available # In “topo” mode (dc_shell-t –topo) specify Milkyway reference and design libraries create_mw_lib –tech -mw_reference_library \ open_mw_lib set_tlu_plus_files -max_tluplus -tech2itf_map set compile_auto_ungroup_delay_num_cells 99999999 set compile_auto_ungroup_count_leaf_cells true set compile_auto_ungroup_override_wlm true set_ungroup false # OPTIONAL: Disable unconditional auto-ungrouping # of DesignWare hierarchy (not usually recommended) set compile_ultra_ungroup_dw false # If design contains pipelined sub-designs and the pipeline registers # are grouped together at the input or output, relax timing set_multicycle_path –setup <#_stages> -from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg* # In “ topo” mode, if the floorplan is available, apply or extract the physical constraints source OR extract_physical_constraints # OPTIONAL: Exclude specific cells/design from adaptive retiming (-retime) set_dont_retime true # First compile compile_ultra –scan –retime –timing|-area # The design hierarchy may have changed due to auto-ungrouping/-uniquifying reset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if required set_dont_touch [get_cells U_Pipeline/R12_reg*] true # Optimize registers if pipeline violates timing; Skip if no pipeline issues: set_optimize_registers true –design My_Pipeline_Subdesign optimize_registers –only_attributed_designs # Continue if design is NOT meeting all constraints: # Apply more focus on violating critical paths, as necessary group_path –name -from -to \ –critical range <10% of max delay goal> -weight 5 # Select appropriate second compile # In “topo” mode in DC v2006.06, or any mode in DC v2007.03 or later compile_ultra –scan –incremental # In “WLM” mode in DC v2006.06 set_ultra_optimization true compile –boundary –scan –map_effort high –incremental (-area_effort medium|low|none) # In “topo” mode prior to DC v2007.03: Write out updated physical constraints write_physical_constraints –output PhysConstr.tcl DFT Flow – Expert or Ultra DFTC license available # Prior to the first compile set the # scan cell style set_scan_configuration –style .. # Perform the first test-ready compile compile –boundary –map high –scan # OR compile_ultra –timing -scan # Continue before the next compile: # Read in the scan specification file source scan_spec.tcl # Check for DFT rule violations dft_drc # Preview the scan chains preview_dft # Insert and optimize scan insert_dft ****************************************************** * * * Execute additional Ultra/Expert optimization * * techniques, as needed * * * ****************************************************** # After the final compile check the DFT QoR # and write out the scan DEF file dft_drc –coverage_estimate write_scan_def -out Some Scan Specification Commands set_scan_state test_ready set_dft_configuration ... set_dft_signal ... set_scan_path ... set_scan_configuration ... create_test_protocol Expert Compile Flow No Ultra license available; DFTC license available compile –boundary –scan –map_effort high # Continue if NOT meeting constraints # Note: -scan requires DFTC license compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none) # Continue if NOT meeting constraints: # Increase max-delay priority if OK to postpone DRC fixing set_cost_priority –delay # Note: The design hierarchy may have changed due to auto- # uniquifying # Apply more focus on violating critical paths, as necessary group_path –name -from \ -to –critical range <10% of max delay goal> -weight 5 # Repartition if design is poorly partitioned group –design -cell_name \ {U2 U7 ...} ungroup –start_level 2 U_NEW_CELL compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none) # Or, can ungroup all hierarchy in lieu of group/ungroup # commands with –ungroup_all compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none) –ungroup_all “Pseudo Ultra” Compile Flow Ultra license available; No DesignWare license available set compile_auto_ungroup_delay_num_cells 99999999 set compile_auto_ungroup_area_num_cells 99999999 set compile_auto_ungroup_count_leaf_cells true set compile_auto_ungroup_override_wlm true set_ungroup false # OPTIONAL: Disable unconditional auto-ungrouping # of DesignWare hierarchy (not usually recommended) set compile_ultra_ungroup_dw false # If design contains pipelined sub-designs and the pipeline registers # are grouped together at the input or output, relax timing set_multicycle_path –setup <#_stages> \ -from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg* # Enable Ultra optimizations available for compile set_ultra_optimization –no_auto_dwlib true set hlo_disable_datapath_optimization true set compile_slack_driven_buffering true compile –boundary –scan –map_effort high –auto_ungroup delay|area \ (-area_effort medium|low|none) # Note: The design hierarchy may have changed due to auto- # ungrouping and auto-uniquifying reset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if required set_dont_touch [get_cells U_Pipeline/R12_reg*] true # Optimize registers if pipeline violates timing; Skip if no pipeline issues: set_optimize_registers true –design My_Pipeline_Subdesign optimize_registers –only_attributed_designs # Continue if design is NOT meeting all constraints: compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none) # Continue if NOT meeting all constraints: set_cost_priority –delay # Ungroup DesignWare components amid combinational logic ungroup # Apply more focus on violating critical paths, as necessary group_path –name -from -to \ –critical range <10% of max delay goal> -weight 5 compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)

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DC Design Compiler 综合脚本命令及参考模板

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