TLK1221中文资料

TLK1221中文资料www.ti.comFEATURESRHAPackage(TopView)ENABLETD0TD1TD2TD3VDDTD4TD5TD6TD7SYNCRD0RD1RD2VDDRD3RD4RD5RD6RD7GNDATXNTXPVDDAVDDPLLGNDARXPRXNSYNCENPRBSENTD8TD9RBCMODEREFCLKLOOPENVDDRBCRD9RD8RBC1DESCRIPTIONTLK1221SLLS713–FEBRUARY2007ETHERNETTRANSCEIVER•0.6-to1.3-GigabitsPerSecond(Gbps)Serializer/Deserializer•LowPowerConsumption250mW(typ)at1.25Gbps•LVPECL-CompatibleDifferentialI/OonHigh-SpeedInterface•SingleMonolithicPLLDesign•SupportFor10-BitInterface•ReceiverDifferential-InputThresholds,200-mVMinimum•IndustrialTemperatureRangeFrom–40°Cto85°C•IEEE802.3GigabitEthernetCompliant•Designedin0.25µmCMOSTechnology•NoExternalFilterCapacitorsRequired•ComprehensiveSuiteofBuilt-InTestability•2.5-VSupplyVoltageforLowest-PowerOperation•3.3-VTolerantonLVTTLInputs•HotPlugProtection•40-Pin6-mm×6-mmQFNPowerPAD™PackageTheTLK1221gigabitEthernettransceiverprovidesforhigh-speedfull-duplexpoint-to-pointdatatransmissions.Thesedevicesarebasedonthetimingrequirementsofthe10-bitinterfacespecificationbytheIEEE802.3GigabitEthernetspecification.TheTLK1221supportsdataratesfrom0.6Gbpsthrough1.3Gbps.Theprimaryapplicationofthesedevicesistoprovidebuildingblocksforpoint-to-pointbasebanddatatransmissionovercontrolled-impedancemediaof50Ω.Thetransmissionmediacanbeprinted-circuitboardtraces,coppercablesorfiber-opticalmedia.Theultimaterateanddistanceofdatatransferisdependentupontheattenuationcharacteristicsofthemediaandthenoisecouplingtotheenvironment.TheTLK1221performsthedataserialization,deserialization,andclockextractionfunctionsforaphysicallayerinterfacedevice.Thetransceiveroperatesat1.25Gbps(typical),providingupto1Gbpsofdatabandwidthoveracopperoropticalmediainterface.Thisdevicesupportsthedefined10-bitinterface(TBI).IntheTBImode,theserializer/deserializer(SERDES)accepts10-bitwide8b/10bparallelencodeddatabytes.TheparalleldatabytesareserializedandtransmitteddifferentiallyatPECL-compatiblevoltagelevels.TheSERDESextractsclockinformationfromtheinputserialstreamanddeserializesthedata,outputtingaparallel10-bitdatabyte.Acomprehensiveseriesofbuilt-intestsisprovidedforself-testpurposes,includingloopbackandpseudorandombinarysequence(PRBS)generationandverification.Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.PowerPADisatrademarkofTexasInstruments.Allothertrademarksarethepropertyoftheirrespectiveowners.PRODUCTIONDATAinformationiscurrentasofpublicationdate.Copyright©2007,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.元器件交易网www.cecb2b.comwww.ti.comDifferencesBetweenTLK2201B,TLK2201BI,TLK1221,andTNETE2201TXPTXNRXPRXNSLLS713–FEBRUARY2007TheTLK1221ishousedinahigh-performance,thermallyenhanced,40-pinQFNpackage.Useofthispackagedoesnotrequireanyspecialconsiderationsexcepttonotethatthepad,whichisanexposeddiepadonthebottomofthedevice,isametallicthermalandelectricalconductor.ItisrequiredthattheTLK1221padbesolderedtothethermallandontheboardasitservesasthemaingroundconnectionforthedevice.TheTLK1221ischaracterizedforoperationfrom–40°Cto85°C.Thisdeviceusesa2.5-Vsupply.TheI/Osectionis3.3-Vcompatible.Withthe2.5-Vsupply,thechipsetisverypower-efficient,dissipatinglessthan200mWtypicalpowerwhenoperatingat1.25Gbps.TheTLK1221isdesignedtobehot-plugcapable.Apower-onresetcausesRBC0,RBC1,theparalleloutputsignalterminals,TXP,andTXNtobeheldinthehigh-impedancestate.TheTLK1221isthefunctionalequivalentoftheTNETE2201.Thereareseveraldifferencesbetweenthedevicesasnotedbelow.RefertoFigure12intheapplicationinformationsectionforanexampleofatypicalapplicationcircuit.•VCCis2.5VfortheTLK2201B,TLK2201BI,TLK1221,andTLK1201Avs3.3VforTNETE2201.•ThePLLfiltercapacitorsonpins16,17,48,and49oftheTNETE2201arenolongerrequired.TheTLK2201B,TLK2201BI,TLK1221,andTLK1201Ausethesepinstoprovideaddedtestcapabilities.Thecapacitors,ifpresent,donotaffecttheoperationofthedevice.•NopulldownresistorsarerequiredontheTXP/TXNoutputs.•TheTLK1221isaQFNversionoftheTLK2201BoptimizedforGBE-onlyTBI-modeoperationwithnoJTAGfunctionality.FunctionalBlockDiagramwww.ti.comDetailedDescriptionTransmissionLatencyTXP,TXNREFCLKTD(0–9)DataReceptionReceiverClockSelectModeSLLS713–FEBRUARY2007IntheTBImode,thetransmitterportionregistersincoming10-bit-widedatawords(8b/10bencodeddata,TD0–TD9)ontherisingedgeofREFCLK.REFCLKisalsousedbytheserializer,whichmultipliestheclockbyafactorof10,providingasignalthatisfedtotheshiftregister.The8b/10bencodeddataistransmittedsequentially,bits0through9,overthedifferentialhigh-speedI/Ochannel.Datatransmissionlatencyisdefinedasthedelayfromtheinitial10-bitwordloadtotheserialtransmissionofbit9.TheminimumlatencyinTBImodeis19bittimes.ThemaximumlatencyinTBImodeis20bittimes.Figure1.TransmitterLatency,Full-RateModeThereceiversectiondeserializesthedifferentialserialdata.Theserialdataisretimedbasedonaninterpolatedclockgeneratedfromthereferenceclock.Theserialdataisthenalignedtothe10-bitwordboundariesandpresentedtotheprotocolcontrolleralongwiththereceivebyteclocks(RBC0,RBC1).TheTLK1221onlysupportsTBI-modeoperationwithhalf-rateandfull-rateclocksonRBC0andRBC1.InTBImode,therearetwouser-selectableclockmodesthatarecontrolledbytheRBCMODEterminal:1)full-rateclockonRBC0and2)half-rateclocksonRBC0andRBC1.Table1.ModeSelectionRECEIVEBYTECLOCKRBCMODEMODETLK12210TBIhalf-rate30–65MHz1TBIfull-rate60–130MHzInthehalf-ratemode,tworeceivebyteclocks(RBC0andRBC1)are180degreesoutofphaseandoperateatone-halfthedatarate.Theclocksaregeneratedbydividingdowntherecoveredclock.Thereceiveddataisoutputwithrespecttothetworeceivebyteclocks(RBC0,RBC1),allowingaprotocoldevicetoclocktheparallelbytesusingtheRBC0andRBC1risingedges.Fortheoutputstotheprotocoldevice,byte0ofthereceiveddataisvalidontherisingedgeofRBC1.RefertothetimingdiagramshowninFigure2.www.ti.comRBC0RBC1SYNCRD(0–9)RBC0SYNCRD(0–9)ReceiverWordAlignmentSLLS713–FEBRUARY2007Figure2.SynchronousTimingCharacteristicWaveforms(TBIHalf-RateMode)Thereceiverclockinterpolatorcanlocktotheincomingdatawithouttheneedforalock-to-referencepreset.Thereceivedserialdatarate(RXPandRXN)isatthesamebaudrateasthetransmitteddatastream,±0.02%(200PPM)forproperoperation.Figure3.SynchronousTimingCharacteristicWaveforms(TBIFull-RateMode)ThesedevicesusetheIEEE802.3GigabitEthernetdefined10-bitK28.5character,whichcontainsthe7-bitcomma-patternwordalignmentscheme.Thefollowingsectionsexplainhowthisschemeworksandhowitrealignstotheproperbyteboundaryofthedata.CommaCharacteronExpectedBoundaryThesedevicesprovide10-bitK28.5characterrecognitionandwordalignment.The10-bitwordalignmentisenabledbyforcingtheSYNCENterminalhigh.Thisenablesthefunctionthatexaminesandcomparesserialinputdatatothe7-bitsynchronizationpattern.TheK28.5characterisdefinedbythe8b/10bcodingschemeasapatternconsistingof0011111010(anegativenumberbeginningwithdisparity),withthe7MSBs(0011111)referredtoasthecommacharacter.TheK28.5characterwasimplementedspecificallyforaligningdatawords.AslongastheK28.5characterfallswithintheexpected10-bitboundary,thereceived10-bitdataisproperlyalignedanddatarealignmentisnotrequired.Figure2showsthetimingcharacteristicsofRBC0,RBC1,SYNCandRD0–RD9whilesynchronized.(Note:theK28.5characterisvalidontherisingedgeofRBC1).CommaCharacterNotonExpectedBoundaryIfsynchronizationisenabledandaK28.5characterstraddlestheexpected10-bitwordboundary,thenwordrealignmentisnecessary.Realignmentorshiftingthe10-bitwordboundarytruncatesthecharacterfollowingthemisalignedK28.5,butthefollowingK28.5andallsubsequentdataisalignedproperlyasshowninFigure4.TheRBC0andRBC1pulsewidthsarestretchedorstalledintheircurrentstateduringrealignment.Withthisdesign,themaximumstretchthatoccursis20bittimes.Thisoccursduringaworst-casescenariowhentheK28.5isalignedtothefallingedgeofRBC1insteadoftherisingedge.Figure4showsthetimingcharacteristicsofthedatarealignment.www.ti.comINPUTDATARBC0RBC1RD(0–9)SYNCDataReceptionLatencyRXP,RXNRD(0–9)RBC0RBC1TestabilitySLLS713–FEBRUARY2007Figure4.WordRealignmentTimingCharacteristicWaveformsSystemsthatdonotrequireframeddatamaydisablebytealignmentbytyingSYNCENlow.WhenaSYNCcharacterisdetected,theSYNCsignalisbroughthighandisalignedwiththeK28.5character.ThedurationoftheSYNCpulseisequaltothedurationofthedata.Theserial-to-paralleldatalatencyisthetimefromwhenthefirstbitarrivesatthereceiveruntilitisoutputinthealignedparallelwordwithRD0receivedasthefirstbit.TheminimumlatencyinTBImodeis21bittimesandthemaximumlatencyis31bittimes.Figure5.ReceiverLatency,TBIHalf-RateModeShownTheloopbackfunctionprovidesforat-speedtestingofthetransmit/receivesectionofthecircuitry.TheenablefunctionallowsforallcircuitrytobedisabledsothatanIddqtestcanbeperformed.ThePRBSfunctionalsoallowsforbuilt-inself-test(BIST).www.ti.comLoopbackTestingENABLEFunctionPRBSFunctionSLLS713–FEBRUARY2007Thetransceivercanprovideaself-testfunctionbyenabling(LOOPENtohighlevel)theinternalloopbackpath.Enablingthisfunctioncausesserialtransmitteddatatoberoutedinternallytothereceiver.Theparalleldataoutputcanbecomparedtotheparallelinputdataforfunctionalverification.(Theexternaldifferentialoutputisheldinahigh-impedancestateduringtheloopbacktesting.)Whenheldlow,ENABLEdisablesallquiescentpowerinbothanaloganddigitalcircuitry.Thisallowsanultralow-poweridlestatewhenthelinkisnotactive.Thesedeviceshaveabuilt-in27–1PRBSfunction.WhenthePRBSENcontrolbitissethigh,thePRBStestisenabled.APRBSisgeneratedandfedintothe10-bitparalleltransmitterinputbus.DatafromthenormalparallelinputsourceisignoredduringPRBStestmode.ThePRBSpatternisthenfedthroughthetransmitcircuitryasifitwerenormaldataandsentouttothetransmitter.Theoutputcanbesenttoabiterrorratetester(BERT)ortothereceiverofanotherTLK1221.BecausethePRBSisnotreallyrandomandisreallyapredeterminedsequenceofonesandzeros,thedatacanbecapturedandcheckedforerrorsbyaBERT.Thesedevicesalsohaveabuilt-inBERTfunctiononthereceiversidethatisenabledbyPRBSEN.ItcanreceiveaPRBSpatternandcheckforerrors,andthenreporttheerrorsbyforcingtheSYNC/PASSterminallow.ThePRBStestingsupportstwomodes(normalandlatched),whicharecontrolledbytheSYNCENinput.WhenSYNCENislow,theresultofthePRBSbit-error-ratetestispassedtotheSYNC/PASSterminal.WhenSYNCENishigh,theresultofthePRBSverificationislatchedontheSYNC/PASSoutput(i.e.,asinglefailureforcesSYNC/PASStoremainlow).Table2.TERMINALFUNCTIONSTERMINALI/ODESCRIPTIONNAMENO.SIGNALDifferentialoutputtransmit.TXPandTXNaredifferentialserialoutputsthatinterfacetoaTXP38PECLcopperoranopticalI/Fmodule.TXPandTXNareputinahigh-impedancestatewhenTXN39OLOOPENishighandareactivewhenLOOPENislow.RXP34PECLDifferentialinputreceive.RXPandRXNtogetherarethedifferentialserialinputinterfaceRXN33IfromacopperoranopticalI/Fmodule.Referenceclock.REFCLKisanexternalinputclockthatsynchronizesthereceiverandtransmitterinterface(60MHzto130MHz).ThetransmitterusesthisclocktoregistertheREFCLK14Iinputdata(TD0–TD9)forserialization.IntheTBImodethatdataisregisteredontherisingedgeofREFCLK.Transmitdata.Theseinputscarry10-bitparalleldataoutputfromaprotocoldevicetothetransceiverforserializationandtransmission.This10-bitparalleldataisclockedintotheTD0–TD92–5,7–12ItransceiverontherisingedgeofREFCLKandtransmittedasaserialstreamwithTD0sentasthefirstbit.Receivedata.Theseoutputscarry10-bitparalleldataoutputfromthetransceivertotheRD0–RD929–27,25–19Oprotocollayer.ThedataisreferencedtoterminalsRBC0andRBC1.RD0isthefirstbitreceived.Receivebyteclock.RBC0andRBC1arerecoveredclocksusedforsynchronizingthe10-bitoutputdataonRD0–RD9.Inthehalf-ratemode,the10-bitoutputdatawordsarevalidontherisingedgesofRBC0RBC017andRBC1.Theseclocksareadjustedtohalf-wordboundariesinconjunctionwithORBC118synchronousdetect.Theclocksarealwaysexpandedduringdatarealignmentandneversliveredortruncated.RBC0registersbytes1and3ofreceiveddata.RBC1registersbytes0and2ofreceiveddata.Innormal-ratemode,onlyRBC0isvalidandoperatesat1/10ththeserialdatarate.Dataisalignedtotherisingedge.Receiveclockmodeselect.WhenRBCMODEislow,half-rateclocksareoutputonRBC0IRBCMODE13andRBC1.WhenRBCMODEishigh,afullbaud-rateclockisoutputonRBC0,andRBC1isP/D(1)heldlow.(1)P/D=Internalpulldownresistorwww.ti.comABSOLUTEMAXIMUMRATINGSDISSIPATIONRATINGSSLLS713–FEBRUARY2007Table2.TERMINALFUNCTIONS(continued)TERMINALI/ODESCRIPTIONNAMENO.Synchronousfunctionenable.WhenSYNCENishigh,theinternalsynchronizationfunctionIisactivated.Whenthisfunctionisactivated,thetransceiverdetectsthecommapatternSYNCEN32P/U(2)(0011111negativebeginningdisparity)intheserialdatastreamandrealignsdataonbyteboundariesifrequired.WhenSYNCENislow,serialinputdataisunframedinRD0–RD9.Synchronousdetect.TheSYNCoutputisassertedhighupondetectionofthecommapatternintheserialdatapath.SYNCpulsesareoutputonlywhenSYNCENisactivatedSYNC/PASS30O(assertedhigh).InPRBStestmode(PRBSEN=high),SYNC/PASSoutputsthestatusofthePRBStestresults(high=pass).TESTLoopenable.WhenLOOPENishigh(active),theinternalloopbackpathisactivated.Thetransmittedserialdataisdirectlyroutedtotheinputsofthereceiver.Thisprovidesaself-testILOOPEN15capabilityinconjunctionwiththeprotocoldevice.TheTXPandTXNoutputsareheldinaP/D(3)high-impedancestateduringtheloopbacktest.LOOPENisheldlowduringstandardoperationalstatewithexternalserialoutputsandinputsactive.PRBSenable.WhenPRBSENishigh,thePRBSgenerationcircuitryisenabled.ThePRBSIverificationcircuitinthereceivesideisalsoenabled.APRBSsignalcanbefedtothePRBSEN31P/D(3)receiveinputsandcheckedforerrors,whicharereportedbytheSYNC/PASSterminalindicatinglow.Whenthisterminalislow,thedeviceisdisabledforIddqtesting.RD0–RD9,RBCn,TXPandIENABLE1TXNarehigh-impedance.Thepullupandpulldownresistorsonanyinputaredisabled.P/D(2)WhenENABLEishigh,thedeviceoperatesnormally.POWERVDD6,16,26SupplyDigitallogicpower.ProvidespowerforalldigitalcircuitryanddigitalI/ObuffersAnalogpower.VDDAprovidespowerforthehigh-speedanalogcircuits,receiver,andVDDA37Supplytransmitter.VDDPLL36SupplyPLLpower.ProvidespowerforthePLLcircuitry.Thisterminalrequiresadditionalfiltering.GROUNDGNDA35,40GroundAnalogground.GNDAprovidesagroundforthehigh-speedanalogcircuits,RXandTX.GNDQFNPADGroundDigitallogicground.ProvidesagroundforthelogiccircuitsanddigitalI/Obuffers(2)P/U=Internalpullupresistor(3)P/D=Internalpulldownresistoroveroperatingfree-airtemperaturerange(unlessotherwisenoted)VALUE(1)UNITVDDSupplyvoltage(2)–0.3to3VVIInputvoltagerangeatTTLterminals–0.5to4VVIInputvoltagerangeatotherterminals–0.3toVDD+0.3VESDElectrostaticdischargeCDM:1,HBM:2kVTstgStoragetemperature–65to150°CTACharacterizedfree-airtemperaturerange–40to85°C(1)Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.(2)Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundterminal.TA≤25°CDERATINGFACTORTA=70°CTA=85°CPACKAGEPOWERRATINGABOVETA=25°CPOWERRATINGPOWERRATINGRHA(1)(2)2.85W28mW/°C1.57W1.4W(1)ThethermalresistancejunctiontoambientoftheRHApackageis35°C/Wmeasuredonahigh-Kboard.(2)Thethermalresistancejunction-to-case(exposedpad)oftheRHApackageis5°C/W.www.ti.comRECOMMENDEDOPERATINGCONDITIONSREFERENCECLOCK(REFCLK)TIMINGREQUIREMENTSTTLELECTRICALCHARACTERISTICSSLLS713–FEBRUARY2007overoperatingfree-airtemperaturerange(unlessotherwisenoted)MINNOMMAXUNITVDD,VDDA,Supplyvoltage2.32.52.7VVDDPLLIDD,IDDA,Frequency=1.25Gbps,PRBSpattern;ENABLETotalsupplycurrent113mAIDDPLL=1,VDD,VDDPLLandVDDA=2.7VPDTotalpowerdissipationFrequency=1.25Gbps,PRBSpattern235305mWTotalshutdowncurrent(IDD+IDDA+IDDQEnable=0;VDD,VDDPLLandVDDA=2.7V1000µAIDDPLL)PLLStartuplocktimeVDD,VDDA=2.5V500µsTAOperatingfree-airtemperature–4085°Coverrecommendedoperatingconditions(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITMinimumdatarateTYP–0.01%60TYP+0.01%fFrequencyMHzMaximumdatarateTYP–0.01%130TYP+0.01%Accuracy–100100ppmDCDutycycle40%50%60%JitterRandomplusdeterministic40psoverrecommendedoperatingconditions(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITVOHHigh-leveloutputvoltageIOH=–400µAVDD–0.22.3VVOLLow-leveloutputvoltageIOL=1mAGND0.250.5VVIHHigh-levelinputvoltage1.73.6VVILLow-levelinputvoltage0.8VIIHHigh-levelinputcurrentVDD=2.3V,VIN=2V40µAIILLow-levelinputcurrentVDD=2.3V,VIN=0.4V–40µACINInputcapacitance4pFwww.ti.comTRANSMITTER/RECEIVERCHARACTERISTICS~V~V~V~V80%20%0V~1V~–1VTX+TX–VODRXP,RXNRD(0–9)RBC0SLLS713–FEBRUARY2007overrecommendedoperatingconditions(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITVOD=|TxD–TxN|Rt=50Ω6008501100mVTransmitcommonmodevoltageV(CM)Rt=50Ω100012501400mVrangeReceiverinputvoltagerequirement,2001600mVVID=|RxP–RxN|Receivercommonmodevoltage100012502250mVrange,(RxP+RxN)/2CIReceiverinputcapacitance2pFDifferentialoutputjitter,random+t(TJ)Serialdatatotaljitter(peak-to-peak)deterministic,PRBSpattern,0.24UIRω=125MHzSerialdatadeterministicjitterDifferentialoutputjitter,PRBSt(DJ)0.12UI(peak-to-peak)pattern,Rω=125MHzDifferentialsignalrise,falltime(20%RL=50Ω,CL=5pF,seeFigure6tr,tf100250psto80%)andFigure8SerialdatajittertoleranceminimumDifferentialinputjitter,random+requiredeyeopening,(per0.25UIdeterministic,Rω=125MHzIEEE-802.3specification)Receiverdataacquisitionlocktime500µsfrompowerupDatarelocktimefromlossof1024Bittimessynchronizationtd(Txlatency)TxlatencySeeFigure12022UItd(Rxlatency)RxlatencySeeFigure5andFigure71824UIFigure6.DifferentialandCommon-ModeOutputVoltageDefinitionsFigure7.ReceiverLatency,TBINormalModeShownwww.ti.com50W50WCLOCK2V0.8VDATA1.4VLVTTLOUTPUTSWITCHINGCHARACTERISTICSTRANSMITTERTIMINGREQUIREMENTSSLLS713–FEBRUARY2007Figure8.TransmitterTestSetupFigure9.TTLDataI/OValidLevelsforACMeasurementoverrecommendedoperatingconditions(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITtr(RBC)Clockrisetime0.31.5nstf(RBC)Clockfalltime0.31.5ns80%to20%outputvoltage,C=5pF(seeFigure9)trDatarisetime0.31.5nstfDatafalltime0.31.5nsTBInormalmode(seeFigure3),Rω=125MHz,2.5nsdatavalidpriortoRBC0risingDatasetuptimetsu(d1)(RD0–RD9)TBInormalmode(seeFigure3),Rω=61.445nsMHz,datavalidpriortoRBC0risingTBInormalmode(seeFigure3),Rω=125MHz,2nsdatavalidafterRBC0risingth(d1)Dataholdtime(RD0–RD9)TBInormalmode(seeFigure3),Rω=61.444nsMHz,datavalidafterRBC0risingDatasetuptimeTBIhalf-ratemode,Rω=125MHz(seetsu(d3)2.5ns(RD0–RD9)Figure2)TBIhalf-ratemode,Rω=125MHz(seeth(d3)Dataholdtime(RD0–RD9)1.5nsFigure2)overrecommendedoperatingconditions(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITtsu(d4)Datasetuptime(TD0–TD9)1.6nsth(d4)Dataholdtime(TD0–TD9)0.8nstr,tfTD[0,9]datariseandfalltimeSeeFigure92nswww.ti.comTLK1221SLLS713–FEBRUARY2007Table3.AVAILABLEOPTIONSTAPACKAGEQFNPLASTICQUADFLATPACK(RHA)–40°Cto85°CTLK1221RHA11SubmitDocumentationFeedbackwww.ti.comAPPLICATIONINFORMATION8b/10bTransmissionCodeTLK1221SLLS713–FEBRUARY2007ThePCSmapsGMIIsignalsintoten-bitcodegroupsandviceversa,usingan8b/10bblockcodingscheme.ThePCSusesthetransmissioncodetoimprovethetransmissioncharacteristicsofinformationtobetransferredacrossthelink.TheencodingdefinedbythetransmissioncodeensuresthatsufficienttransitionsarepresentinthePHYbitstreamtomakeclockrecoverypossibleinthereceiver.Suchencodingalsogreatlyincreasesthelikelihoodofdetectinganysingle-ormultiple-biterrorsthatmayoccurduringtransmissionandreceptionofinformation.The8b/10btransmissioncodespecifiedforusehasahightransitiondensity,isrunlengthlimited,andisdc-balanced.Thetransitiondensityofthe8b/10bsymbolsrangesfrom3to8transitionspersymbol.Thedefinitionofthe8b/10btransmissioncodeisspecifiedinIEEE802.3GigabitEthernetandANSIX3.230-1994(FC-PH),clause11.8b/10btransmissioncodeusesletternotationdescribingthebitsofanunencodedinformationoctet.ThebitnotationofA,B,C,D,E,F,G,Hforanunencodedinformationoctetisusedinthedescriptionofthe8b/10btransmissioncode-groups,whereAistheLSB.Eachvalidcodegrouphasbeengivenanameusingthefollowingconvention:/Dx.y/forthe256validdatacode-groupsand/Kx.y/forthespecialcontrolcode-groups,whereyisthedecimalvalueofbitsEDCBAandxisthedecimalvalueofbitsHGF(notedasK).Thus,anoctetvalueofFErepresentingacode-g