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ARM汇编语言程序设计总结

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ARM汇编语言程序设计总结ARM汇编语言程序设计总结.ARM汇编语言程序设计总结.PAGE/NUMPAGESARM汇编语言程序设计总结.ARM汇编语言程序设计总结一、常用指令1.储存器接见指令LDRSTRLDRLoad32-bitwordtoMemory.SyntaxLDR{cond}Rd,[Rn]LDR{cond}Rd,[Rn,offset]LDR{cond}Rd,[Rn,offset]!LDR{cond}Rd,labelLDR{cond}Rd,[Rn],offset...

ARM汇编语言程序设计总结
ARM汇编语言程序 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 总结.ARM汇编语言程序设计总结.PAGE/NUMPAGESARM汇编语言程序设计总结.ARM汇编语言程序设计总结一、常用指令1.储存器接见指令LDRSTRLDRLoad32-bitwordtoMemory.SyntaxLDR{cond}Rd,[Rn]LDR{cond}Rd,[Rn,offset]LDR{cond}Rd,[Rn,offset]!LDR{cond}Rd,labelLDR{cond}Rd,[Rn],offsetDescriptionLDR{cond}Rd,[Rn](zerooffset)Rnisusedasaddressvalue.LDR{cond}Rd,[Rn,offset](Pre-indexedoffset)Rnandoffsetareaddedandusedasaddressvalue.LDR{cond}Rd,[Rn,offset]{!}(Pre-indexedoffsetwithupdate)Rnandoffsetareaddedandusedasaddressvalue.ThenewaddressvalueiswrittentoRn.LDR{cond}Rd,label(Program-relative)TheassemblercalculatesthePCoffsetandgeneratesLDR{cond}Rd,[R15,offset].LDR{cond}Rd,[Rn],offset(Post-indexedoffset)Rnisusedasaddressvalue.Aftermemorytransfer,theoffsetisaddedtoRn.ExampleLDRR8,[R10]//loadsr8fromtheaddressinr10.LDRNER2,[R5,#960]!//(conditionally)loadsr2fromaword960bytesabovetheaddressinr5,andincrementsr5by960.LDRR0,localdata//loadsawordlocatedatlabellocaldataSTRStoreregister32-bitwordstoMemory.Theaddressmustbe32-bitword-aligned.SyntaxSTR{cond}Rd,[Rn]STR{cond}Rd,[Rn,offset]STR{cond}Rd,[Rn,offset]!STR{cond}Rd,labelSTR{cond}Rd,[Rn],offsetDescriptionSTR{cond}Rd,[Rn](zerooffset)Rnisusedasaddressvalue.STR{cond}Rd,[Rn,offset](Pre-indexedoffset)Rnandoffsetareaddedandusedasaddressvalue.STR{cond}Rd,[Rn,offset]!(Pre-indexedoffsetwithupdate)Rnandoffsetareaddedandusedasaddressvalue.ThenewaddressvalueiswrittentoRn.STR{cond}Rd,label(Program-relative)TheassemblercalculatesthePCoffsetandgeneratesSTR{cond}Rd,[R15],offset.STR{cond}Rd,[Rn],offset(Post-indexedoffset)Rnisusedasaddressvalue.Aftermemorytransfer,theoffsetisaddedtoRn.ExampleLDRr8,[r10]//loadsr8fromtheaddressinr10.LDRNEr2,[r5,#960]!//(conditionally)loadsr2fromaword//960bytesabovetheaddressinr5,and//incrementsr5by960.STRr2,[r9,#consta-struc]//consta-strucisanexpressionevaluating//toaconstantintherange0-4095.STRBr0,[r3,-r8,ASR#2]//storestheleastsignificantbytefrom//r0toabyteatanaddressequalto//contents(r3)minuscontents(r9)/4.//r3andr8arenotaltered.STRr5,[r7],#-8//storesawordfromr5totheaddress//inr7,andthendecrementsr7by8.LDRr0,localdata//loadsawordlocatedatlabellocaldata2.一般数据办理指令ADDSUBADCSBCAND,ORR,EOR,CMPTSTUMULL,UMLAL,SMULL,andSMLALMUL,MLA,andMLSADCAddwithCarry.SyntaxADC{cond}{S}Rd,Rn,Op2DescriptionAddRnandOp2andCarryflagandstoreresulttoRd.ADCistypicalusedformulti-wordarithmetic.ConditionFlagsIfSisspecifiedupdateflags:N,Z,C,V.ExampleADDSR0,R2,R4//addR2+R4,storeresulttoR0,setflagsADCR1,R3,R5//addR3+R5withcarryfrompreviousADDS,storeresulttoR1ADDAddvaluesandstoreresulttoregister.SyntaxADD{cond}{S}Rd,Rn,Op2DescriptionAddRnandOp2andstoreresulttoRd.ConditionFlagsIfSisspecifiedupdateflags:N,Z,C,V.ExampleADDSR0,R2,R4//AddR2andR4andstoreresulttoR0,updateflagsADDR4,R4,#0xFF00//Addvaluein0xFF00andR4andstoreresultinR4SUBSubtractregisters.SyntaxSUB{cond}{S}Rd,Rn,Op2DescriptionsubtractsthevalueofOp2fromthevalueinRn.ConditionFlagsIfSisspecifiedupdateflags:N,Z,C,V.ExampleSUBSR8,R6,#240//R8=R6-240SBCSubtractwithcarry.SyntaxSBC{cond}{S}Rd,Rn,Op2Descriptionsynthesizemultiwordarithmetic.ConditionFlagsIfSisspecifiedupdateflags:N,Z,C,V.ExampleADDSR0,R2,R4ADDR4,R4,#0xFF00ANDLogicalANDoperation.SyntaxAND{cond}{S}Rd,Rn,Op2DescriptionLoadRdwithlogicalANDofRnwithOp2.Rd:=RnANDOp2ConditionFlagsIfSisspecified,N,Zflagsareupdated.CflagmaybeupdatedbycalculationofOp2.ExampleANDR9,R2,#0xFF00//LoadR9withR2andvaluein0xFF00ORRLogicalORoperation.SyntaxORR{cond}{S}Rd,Rn,Op2DescriptionORoperationsonthevaluesinRnandOp2.ConditionFlagsIfSisspecified,N,Zflagsareupdated.CflagmaybeupdatedbycalculationofOp2.ExampleORRR2,R0,R5//Rd=R0orR5CMPCompare.Usedincombinationwithconditionalbranchinstructions.SyntaxCMP{cond}Rn,Op2DescriptionsubtractsthevalueofOp2fromthevalueinRn(equalstotheSUBSinstructionwithadiscardedresult).Thisinstructionupdatestheconditionflags,butdonotplacearesultinaregister.ConditionFlagsN,Z,CandVflagsareupdated.ExampleCMPR2,R9//SubtractvalueofR9fromR2TSTTest.SyntaxTST{cond}Rn,Op2DescriptionperformsabitwiseANDoperationonthevalueinRnandthevalueofOp2.ThisissimilartotheANDSinstruction,exceptthattheresultisdiscarded.ConditionFlagsNandZflagsareupdatedaccordingtheresult.CflagmaybeupdatedduringthecalculationofOp2.ExampleTSTNEr1,r5,ASRr1MULMultiply(32-bitby32-bit,bottom32-bitresult).SyntaxMUL{cond}{S}Rd,Rm,RsDescriptionmultipliesthevaluesfromRmandRs,andplacestheleastsignificant32bitsoftheresultinRd.ConditionFlagsIfSisspecified:NandZflagsaccordingtotheresult.theCflaginARMarchitecturev4andearlierwillbecorrupted.theCflaginARMarchitecturev5andlaterisnotaffected.ExampleMULR10,R2,R5//R10:=R2*R53.分支控制指令B,BL,BX,BLX,andBXJBBranchtolabel.Usedtojumptoaspecificprogramlocation.SyntaxB{cond}labelDescriptionThejumpdistancemustbewithin-252to+258bytesforconditionaland±2KBytesforunconditionalbranch.ConditionFlagsnotmodified.ExampleCMPR1,#10//compareR10with#10BEQval_ok//jumptolabelval_okval_ok:val_err:Bval_err//jumptoitself(loopforever)BLBranchwithLink.Usetocallsubroutines.SyntaxBL{cond}labelDescriptionCopyaddressofnextinstructiontoR14andjumptolabel.Thejumpdistancemustbewithin4Mb±ofthecurrentinstruction.Notethatthismnemonicisgeneratedastwo16-bitThumbinstructions.ConditionFlagsnotmodified.ExampleBLsub+ROM//CallsubroutineatcomputedaddressADDSR1,#1//Add1toregister1,settingCPSRflagsontheresultthencallsubroutineiftheCflagisclear,wichwillbethecase//unlessR1held0xFFFFFFFFBXBranchindirectandswitchCPUmode(Thumb/ARM)asrequired.SyntaxBX{cond}RmDescriptionBranchtoaddressinRm.ChangetoARMmodeifbit0ofRmisclear.ConditionFlagsnotmodified.ExampleBXR5//branchindirecttoaddressfunction4.ARM伪指令1.符号定义伪指令GBLA,GBLL,andGBLSLCLA,LCLL,andLCLS2.数据定义伪指令DCBDCDandDCDU5.条件代码ConditionCodeMostARMinstructionsandtheThumbBranchinstructionincludeaconditioncodefield.ThisfieldismarkedintheCPUinstructionswith{cond}.AconditionalinstructionisonlyexecutedonmatchoftheconditionflagsintheProgramStatusRegister.Forexample,theBEQ(BinstructionwithEQcondition)branchesonlyiftheZflagisset.Ifthe{cond}fieldisemptytheinstructionisalwaysexecuted.{cond}SuffixTestedStatusFlagsDescriptionEQZsetequalNEZclearnotequalCS/HSCsetunsignedhigherorsameCC/LOCclearunsignedlowerMINsetnegativePLNclearpositiveorzeroVSVsetoverflowVCVclearnooverflowHICsetandZclearunsignedhigherLSCclearorZsetunsignedlowerorsameGENequalsVsignedgreaterorequalLTNnotequaltoVsignedlessthanGTZclearAND(NequalsV)signedgreaterthanLEZsetOR(NnotequaltoV)signedlessthanorequalAL(ignored)always(usuallyomitted)Examples:CMPR5,#10//compareR5with10BHIlab1//branchtolab1ifvalueinR5ishigherthan10:lab1:TSTR5,#10//testcontentofR5against10ADDEQR6,#40//add40toR6ifR5contains106.移位种类TheARMCPUhasverypowerfulshiftoperationsthatcanbeusedtogetherwithstandardCPUinstructions.Thevariousshifttypesareexplainedbelow:LogicalShiftRight(LSR)LogicalshiftrightisencodedwithLSR#norLSRRsintheOp2field.Thevalue0isshiftedintobit31andtheCarryflag(C)holdsthelastbitshiftedout.LogicalShiftLeft(LSL)LogicalshiftleftisencodedwithLSL#norLSLRsintheOp2field.Thevalue0isshiftedintobit0andtheCarryflag(C)holdsthelastbitshiftedout.ArithmeticShiftRight(ASR)ArithmeticshiftrightisencodedwithASR#norASRRsintheOp2field.Thesignbit(bit31ofvalue)isshiftedintothehighbit31andtheCarryflag(C)holdsthelastbitshiftedout.RotateRight(ROR)RotaterightisencodedwithROR#nintheTheCarryflag(C)holdsthelastbitshiftedout.Op2field.Bit0ofthevalueisshiftedintobit31.RotateRightExtended(RRX)RotaterightextendedisencodedwithRRXintheOp2field.ThevalueoftheCarryflag(C)isshiftedintobit31.Theshiftedoutbit0iswrittentoC.BinaryoperatorsRealViewCompilationToolsforμVisionVersionAssemblerGuide4.0Home>AssemblerReference>Expressions,literals,andoperators>BinaryoperatorsBinaryoperatorsarewrittenbetweenthepairofsubexpressionstheyoperateon.Binaryoperatorshavelowerprecedencethanunaryoperators.Binaryoperatorsappearinthissectioninorderofprecedence.NoteTheorderofprecedenceisnotthesameasinC,seeOperatorprecedenceinarmasmandC.MultiplicativeoperatorsMultiplicativeoperatorshavethehighestprecedenceofallbinaryoperators.Theyactonlyonnumericexpressions.Table3.9showsthemultiplicativeoperators.Table3.9.MultiplicativeoperatorsOperatorAliasUsageExplanation*A*BMultiply/A/BDivide:MOD:%A:MOD:BAmoduloBStringmanipulationoperatorsTable3.10showsthestringmanipulationoperators.InCC,bothAandBmustbestrings.IntheslicingoperatorsLEFTandRIGHT:AmustbeastringBmustbeanumericexpression.Table3.10.StringmanipulationoperatorsOperatorUsageExplanation:CC:A:CC:B:LEFT:A:LEFT:B:RIGHT:A:RIGHT:BShiftoperatorsBconcatenatedontotheendofATheleft-mostBcharactersofATheright-mostBcharactersofAShiftoperatorsactonnumericexpressions,shiftingorrotatingthefirstoperandbytheamountspecifiedbythesecond.Table3.11showstheshiftoperators.Table3.11.ShiftoperatorsOperatorAliasUsageExplanation:ROL:A:ROL:BRotateAleftbyBbits:ROR:A:ROR:BRotateArightbyBbits:SHL:<<A:SHL:BShiftAleftbyBbits:SHR:>>A:SHR:BShiftArightbyBbitsNoteSHRisalogicalshiftanddoesnotpropagatethesignbit.Addition,subtraction,andlogicaloperatorsAdditionandsubtractionoperatorsactonnumericexpressions.Logicaloperatorsactonnumericexpressions.Theoperationisperformedbitwise,thatis,independentlyoneachbitoftheoperandstoproducetheresult.Table3.12showsaddition,subtraction,andlogicaloperators.Table3.12.Addition,subtraction,andlogicaloperatorsOperatorAliasUsageExplanation+A+BAddAtoB-A-BSubtractBfromA:AND:&A:AND:BBitwiseANDofAandB:EOR:^A:EOR:BBitwiseExclusiveORofAandB:OR:|A:OR:BBitwiseORofAandBRelationaloperatorsTable3.13showstherelationaloperators.Theseactontwooperandsofthesametypetoproducealogicalvalue.Theoperandscanbeoneof:numericprogram-relativeregister-relativestrings.StringsaresortedusingASCIIordering.StringAislessthanstringBifitisaleadingsubstringofstringB,oriftheleft-mostcharacterinwhichthetwostringsdifferislessinstringAthaninstringB.Arithmeticvaluesareunsigned,sothevalueof0>-1is{FALSE}.Table3.13.RelationaloperatorsOperatorAliasUsageExplanation===A=BAequaltoB>A>BAgreaterthanB>=A>=BAgreaterthanorequaltoB<A!=A/=BAnotequaltoBBooleanoperatorsThesearetheoperatorswiththelowestprecedence.Theyperformthestandardlogicaloperationsontheiroperands.InallthreecasesbothAandBmustbeexpressionsthatevaluatetoeither{FALSE}.Table3.14showstheBooleanoperators.Table3.14.BooleanoperatorsOperatorAliasUsageExplanation:LAND:&&A:LAND:BLogicalANDofAandB:LEOR:A:LEOR:BLogicalExclusiveORofAandB:LOR:||A:LOR:BLogicalORofAandB{TRUE}or
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