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Cadence UVM SystemVerilog User Guide Product Version 10.2 June 2011 UVM Version 1.1 © 2007–2011 Cadence Design Systems, Inc. All rights reserved. Portions © CoWare, Free Software Foundation, Inc., Edison Design Group, LessTif Development Team, Terence Parr, University of Colorado, Synopsys, Bob Jenkins. Used by permission. Printed in the United States of America. Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA. Product IES contains technology licensed from, and copyrighted by: CoWare, Inc. 2121 N. First St. San Jose, CA, 95131 U.S.A. and is © 1996–2004, all rights reserved. Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA, 02111-1307 USA and is © 1989–1991, all rights reserved. Edison Design Group Inc. and is © 1988–1996, all rights reserved. LessTif Development Team and is © 2000–2001, all rights reserved. Terence Parr and is © 2000–2001, all rights reserved. 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UVM SystemVerilog User Guide, Cadence Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 How to Use this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 What is UVM? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Installing UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Cadence IES UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Open-Source UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Moving from OVM to UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Terminology in This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Conventions in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 UVM Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 uvm_component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 uvm_get . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 uvm_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 uvm_phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 uvm_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Controlling Transaction Recording with uvm_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 uvm_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Debugging with the Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reusing Module-Based Components in Class-Based UVM Environments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 The Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trivial Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 UVM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical SystemVerilog Module-Based UVM VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 The Wrapper Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contents June 2011 3 Product Version 10.2 Proxy Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Using the Proxy Interfaces in the Class-Based Environment . . . . . . . . . . . . . . . . . . . 30 UVM SystemVerilog User Guide, Cadence June 2011 4 Product Version 10.2 UVM SystemVerilog User Guide, Cadence 1 Introduction This book describes the Cadence extensions to UVM available to IES users and usage of the module-based components in an UVM environment in the following chapters: ■ UVM Tcl Commands ■ Reusing Module-Based Components in Class-Based UVM Environments The UVM Class Library is documented in the UVM Class Reference. How to Use this Book A typical verification team consists of multiple contributors with different skill sets and responsibilities. The different roles of developers and environment users require different depths of verification knowledge. The organization of this manual is based on the way a typical verification team divides its responsibilities. ■ Environment developers create the reusable testbench infrastructure. ■ Environment users (or integrators) write tests for and configure the testbench infrastructure created by the developer to meet a project’s verification goals. Because this document describes the Cadence extensions to UVM, you should also use the open source UVM User Guide as basic information on how to use UVM in general and to gain a thorough understanding of UVM. What is UVM? UVM is a complete verification methodology that codifies the best practices for development of verification environments targeted at verifying large gate-count, IP-based SoCs. Verification productivity stems from the ability to quickly develop individual verification components, encapsulate them into larger reusable verification components (UVCs), and reuse them in different configurations and at different levels of abstraction. UVM supports June 2011 5 Product Version 10.2 “bottom-up” reuse by allowing block-level components and environments to be encapsulated UVM SystemVerilog User Guide, Cadence Introduction and reused as blocks that can be composed into a system. “Top-down” reuse allows transaction-level verification environments to be assembled with system-level models of the design, and then reused as the design is refined down to RTL. UVM uses a SystemVerilog implementation of standard TLM interfaces for modular communication between components. When coupled with a proven reuse architecture for verification components, UVM delivers a common object-oriented use model and ensures that all UVM-compliant UVCs interoperate regardless of the origin or language implementation. Key features of UVM include: ■ Data design—Infrastructure for class property abstracting and simplifying the user code for setting, getting, and printing (text and GUI) property variables. ■ Stimulus generation—Classes and infrastructure to enable fine-grain control of sequential data streams for module-level and system-level stimulus generation. You can randomize the data based on the current state of the environment, including the DUT state, interface, or previously generated data. You are provided out-of-the-box stimulus generation, which you can customize to include user-defined hierarchical transactions and transaction streams. ■ Building and running the verification environment—Creating a complete verification environment for an SoC containing different protocols, interfaces and processors is becoming more and more difficult. Base classes are provided for each functional aspect of a verification environment in the UVM Class Library. The library provides facilities for streamlining the integration of user-defined types into the verification environment. A topology-built infrastructure and methodology provide you with flexibility in defining the required testbench structures. A common configuration interface enables you to query and set fields in order to customize run-time behavior and topology. ■ Coverage model design—Best known practices for incorporating coverage into a reusable UVC including global and fine-grain control design. ■ Built-in checking support—Best known practices for incorporating physical-layer and functional-layer checks into a reusable UVC, including global and fine-grain control design. ■ User example—The provided golden example is based on the XBus protocol. The example includes tests, sequences, testbench structures, and derived UVCs, using the methodology and base classes. June 2011 6 Product Version 10.2 UVM SystemVerilog User Guide, Cadence Introduction Installing UVM Cadence IES UVM The UVM Class Library is in the install_dir/tools/uvm directory. The following irun command-line options are available: Note: Though the Incisive Enterprise Simulator supports incremental elaboration, the standard and safe route for testbenches using UVM SystemVerilog is to use standard elaboration. See Multi-Snapshot Incremental Elaboration in the Cadence documentation library for further details. Open-Source UVM If you prefer to use the open-source library, you can download the UVM kit from www.accellera.org. The site requires that you register and log in before you can download the UVM kit. To set up the open-source UVM in a Cadence IES installation: 1. Make the UVM Class Library accessible by your SystemVerilog program by importing the library package into the scope in which you intend to use it: import uvm_pkg::* 2. Set the UVM_HOME environment variable to the uvm-1.1 directory at the top of the UVM installation hierarchy. % setenv UVM_HOME path_to_UVM_kit_install/uvm-1.1 3. Set your irun command-line options to include a search of the UVM source directories: % irun –uvmhome $UVM_HOME other_options Moving from OVM to UVM To assist you in migrating from OVM to UVM, Cadence provides a transformation Perl script -uvm Searches install_dir/tools/uvm/src and sets other command-line options -uvmhome $UVM_HOME Optionally specifies a different directory for the UVM installation June 2011 7 Product Version 10.2 that inspects all files under your specified top-level directory, and modifies them to convert UVM SystemVerilog User Guide, Cadence Introduction from OVM to the UVM library. As a limitation, this script is not based on a full parser functionality and, therefore, a small number of OVM-to-UVM replacements may be inaccurate. This script, named ovm2uvm.pl and installed in install_dir/uvm/bin, recourses a directory tree and processes all SystemVerilog files in the tree, making the required modifications. The following command invokes the script: % ovm2uvm.pl [options] [args] where: Example: % ovm2uvm.pl --top_dir /xyz/abc/src To convert your OVM library to UVM with the provided script correctly, use the following recommended steps: 1. Run the script with the --top_dir option. 2. Inspect the changes made in the produced ovm2uvm_XXX.patch file that contains the differences between the two directories as the result of executing the diff command (diff original-files changed-files). 3. Enable automatic writing of the changed files to disk by supplying --write to the command invocation. 4. Inspect the markers or perform a search to quickly find the marked changes made by the script. As an alternative, you could also use the facilities of an editor or an IDE(DVT) that normally can extract such special strings. For DVT you could use the --marker=FIXME option and DVT would present all occurrences of that marker in a special view. --help Explains the use model and options. --top_dir=s Specifies the top directory s from which to start; if not specified, the current directory is the starting point. --backup Makes a backup of all files handled by the script. --write Writes the changed files to disk (by default the script runs in “dry” mode). --marker=s Uses the marker supplied by the string s instead of the default marker -*-. For example, using the --marker="some- string" option you can mark the changes in the code with the specified unique marker string. June 2011 8 Product Version 10.2 UVM SystemVerilog User Guide, Cadence Introduction Terminology in This Book Term Definition Agent A device that contains the standard components necessary to drive HDL signals (the driver), provide stimulus to the driver (the sequencer), and collect data items along with enforcing checks and tabulating coverage (the monitor). An agent is capable of independent operation. Bus monitor A verification component responsible for extracting signal information at the bus level and translating it into events, data, and status information Checks and Coverage Functionality and behavior analysis that use coverage, covergroup, procedural code, or assertions in an UVM class- based monitor or SystemVerilog interface Component The fundamental building block used to create each element of an UVC. Each component (for example, driver, agent, and so on) is derived from the uvm_component base class. Data item A transaction object generated as stimulus in a verification environment Driver A verification component that connects at the pin-level interface to the DUT. It contains one or more transaction-level interfaces to communicate with other transaction-level components in the verification environment. DUT Device under test. The design (block, subsystem, or system) being verified, which may be a combination of hardware and software. Env The environment or “env” is the top-level component of the UVC. It contains one or more agents, as well as other top-level components such as a bus monitor. The environment is configurable to enable reuse. For example, active agents can be changed to be passive when the verification environment is reused in system verification. Exhaustive sequence A sequence that randomly selects each sequence that is available in the sequencer and executes it once Interface UVC A reusable verification component focusing on a specific protocol June 2011 9 Product Version 10.2 such as PCI, TCP/IP, Ethernet, and so on UVM SystemVerilog User Guide, Cadence Introduction Late randomization Postponement of the generation and randomization of data until the time when it is passed to the DUT Layered sequencer A sequencer that is used in place of a driver at a given layer of a protocol. Layered sequencers execute a sequence that converts a data item into one or more transactions at the lower layer of the protocol. They may also execute other sequences to generate additional streams of lower-layer items in parallel. Monitor A verification component that monitors signal-level behavior and communicates transactions to other components in the verification environment. A monitor may also perform specific checking and/or functional coverage gathering as needed. UVC UVM verification component. An UVC is an encapsulated, reusable, and configurable verification component for an interface protocol, a design sub-module, or a full system. Public interface An application programming interface (API) declared as public Random sequence A sequence that selects at random one of the sequences available for a specific sequencer and executes it Sequence A basic construct associated with a sequencer. Sequences generate data items and other sequences (subsequences) and drive one or more transactions to the DUT via the driver in an UVC. This construct can also be referred to as a driver sequence. Sequence item A data item (that is, transaction) generated by a sequence. This item is typically provided to a driver by a sequencer. For layering of stimulus, different data items can be defined for each layer. Lower-layer objects can be provided with items by the upper- layer objects. Sequence library A collection of sequences used by a sequencer Sequencer A verification component that mediates the generation and flow of data between sequences and a driver. The sequencer has a collection of sequences associated with it called a sequence library. This type of component is also referred to as a driver sequencer. Simple sequence A sequence that generates a single random data item Term Definition June 2011 10 Product Version 10.2 UVM SystemVerilog User Guide, Cadence Introduction Conventions in This Manual Sub