纳米电子封装22

Chapter 22 Flip Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities Debendra Mallik (*ü ) , Ravi Mahajan , and Vijay Wakharkar 22.1 Introduction After decades of following the roadmap laid out by Moore’s law [1] , silicon features have reached the nanoscale, which is below 100 nm in dimension, as illustrated in Fig. 22.1 . The first logic products with 90-nm transistors, using the traditional silicon dioxide insulator and polysilicon gate, went into volume production in 2003. More recently in 2007, 45-nm devices using a revolutionary high-k metal gate transistor technology have been introduced [2 , 3] . These nanoscale devices enable higher per- formance circuits, which in turn drive advanced features in their packaging. These devices can significantly lower the power consumption of high-performance logic products creating new applications in the fast-growing ultramobile market (Fig. 22.2 ) and thus requiring packaging to support the demands of these form factors. This chapter will discuss the challenges and opportunities in flip chip packaging for these nanoscale devices. In the early days of the semiconductor industry, microelectronics packaging pri- marily provided space transformation, and structural and environmental protection of the small but expensive integrated circuit (IC) devices so that they could be con- nected to relatively large electronic system boards. The role of microelectronics packaging has continued to expand over the past few decades to include electrical and thermal performance management, as well as enabling system miniaturization. Containing the cost of packaging and meeting environmental regulations have been critical constraints during this evolution. Electronics packaging technology has made significant advances over the years. To effectively describe these advances and future challenges, we will primarily focus on logic ICs in computing systems such as mobile PCs (personal computers), desktop PCs, and servers, in this chapter. That is because such systems generally need advanced packaging, driven mainly by the high-performance levels of the microproc- essors within them. We will also use examples of ultramobile systems typified by the cell phone to describe some of the form-factor-driven packaging technology. D. Mallik Intel Corporation , Chandler , AZ, USA J.E. Morris (ed.) Nanopackaging: Nanotechnologies and Electronics Packaging, 491 DOI: 10.1007/978-0-387-47326-0_22, © Springer Science + Business Media, LLC 2008 Morris_Ch22.indd 491Morris_Ch22.indd 491 9/29/2008 8:09:48 PM9/29/2008 8:09:48 PM 492 D. Mallik et al. Fig. 22.1 Feature size and transistor gate length scaling [4] Fig. 22.2 Mobile phone market trend (source: Prismark Partners LLC) The evolution of packages for the desktop PC is shown in Fig. 22.3 . In the early 1980s, the 8088 processor chip was housed in a ceramic dual in-line package (CDIP). It used gold wire-bonds to interconnect the silicon chip to the conducting leads on the ceramic package. This 800-mm 2 package had a total of 40 leads placed along its two long sides. With an operating frequency of only 5 MHz and low power of about 1–3 watts, fewer than 10% of the leads were needed to supply power to the chip. The remainder of the leads was used for signal transfer in and out of the microprocessor. The primary function of this package was to provide space trans- formation and environmental protection. By 1994, the Pentium ® Pro processor used a 3,000-mm 2 ceramic pin grid array (CPGA) package with 387 pins, a ® Pentium is a registered trademark of Intel Corporation and its subsidiaries in the United States and other countries. Morris_Ch22.indd 492Morris_Ch22.indd 492 9/29/2008 8:09:48 PM9/29/2008 8:09:48 PM 22 Flip Chip Packaging for Nanoscale Silicon 493 large copper-tungsten heat slug, and two chips – the CPU chip and a separate large SRAM cache chip. Over 40% of the pins were dedicated to deliver power to the chips, illustrating the increasing importance of power delivery. By the mid-1990s, cost and conductor resistance of the ceramic packages drove a significant shift in packaging technology. CPU packages for desktop PCs migrated to the plastic pin grid array (PPGA) technology, which used copper conductors on an organic substrate, unlike the tungsten conductors on a ceramic substrate. PPGA technology continued to use wire bonds to interconnect the silicon to the package. The wire bonding process requires the interconnect pads to be placed only on the periphery of the die. The inductance of the long wires and resistance of the long on-chip interconnects degraded power delivery performance. Additionally, placing both power and signal pads near the die periphery limited the ability to shrink the size of the chip. These limitations drove the other sig- nificant technology transitions in the 1990s. By 1999, advanced processors such as the Pentium III migrated to organic flip chip ball grid array (FCBGA) [5 , 6] and later to flip chip pin grid array (FCPGA) packages. In 2004, the flip chip land grid array (FCLGA) package was introduced to eliminate the fragile package pins in market seg- ments that could incorporate LGA. In addition to the changes in interconnect, increase in power consumption and power density nonuniformity has led to significant improvement in power delivery and thermal management technologies. Figure 22.4 shows a specific example of how package attributes have advanced to keep pace with Moore’s law-driven product requirements. Ultramobile systems, by nature, need miniaturized devices. As a consequence, the key components in these systems, such as the logic, memory, and wireless devices, have evolved to provide more computing, communication, and memory content within the package volume. The evolution of key packages for such systems is shown in Fig. 22.5 . The traditional scaling of the packages’ horizontal dimension has con- tinued throughout this evolution. Additionally, there has been significant progress in leveraging the packages’ vertical dimension to achieve high density of IC content. Fig. 22.3 Evolution of microprocessor packaging for the desktop PC Morris_Ch22.indd 493Morris_Ch22.indd 493 9/29/2008 8:09:48 PM9/29/2008 8:09:48 PM 494 D. Mallik et al. Silicon Process : 180 nm Package Size : 49.5 mm (sq.) Package Line/Space : 73 µm Thermal Demand : 23 W Power Delivery Impedance : 4.5 mΩ CPU Frequency : 700 MHz Front Side Bus : 100 MHz Die bump : Pb-Sn Package bump : Pb-Sn Eutectic Silicon Process : 45 nm Package Size : 37.5 mm (sq.) Pkg Line/Space : 14 µm Thermal Demand : 130 W Power Delivery Impedance : 1.2 mΩ CPU Frequency : 3 GHz Front Side Bus : 1333 MHz Die bump : Cu Package bump : SnAgCu 20071999 Fig. 22.4 Illustrative example showing how packaging has kept pace with silicon and microproc- essor advances Fig. 22.5 Evolution of packaging for the ultramobile electronic systems Material technologies play a significant role in packaging. Performance requirements, such as thermal management, power delivery, and signal integrity, as well as structural integrity, environmental and manufacturing considerations, have driven improvement in material technologies. This trend is expected to continue with progress along Moore’s law and with the scaling down of system form factors in ultramobile systems. Materials technology evolution is also affected by environ- mental regulations. In recent years, the electronic packages have been engineered to be environmentally friendly by complying with restrictions on hazardous materi- als. The environment-friendly initiative primarily consists of providing Pb-free packaging material solutions, as well as enabling of halogen-free substrate technology to eliminate the use of brominated flame retardants. The industry has responded Morris_Ch22.indd 494Morris_Ch22.indd 494 9/29/2008 8:09:49 PM9/29/2008 8:09:49 PM 22 Flip Chip Packaging for Nanoscale Silicon 495 quite well by eliminating Pb from high-performance microprocessor packaging [3 , 7] and continues to set the strategy for implementation of halogen-free packaging. In the following sections we will examine the trends for key characteristics of flip chip logic packaging discussed in this introduction in greater detail. 22.2 Space Transformation One primary function of the package in an electronic system is to provide cost-effective space transformation. The package transforms the high density of terminals on the small IC chip to a lower density of terminals on the larger package body. The lower density package terminals allow the system board to have larger feature sizes in order to manage its cost. Thus, the package becomes part of the interconnect between one IC component and another. There are three distinct areas of intercon- nect related to packaging. The portion of the interconnect that enables a transition from the die level to the package level is known as the first level interconnect (FLI). The interconnect within the package that creates the space transformation is referred to as routing. The portion of the interconnect that enables a transition from the pack- age to the next level, which is typically the motherboard, is referred to as the second level interconnect (2LI). Note that the number of 2LI terminals does not have to be equal to the number of FLI terminals. That is because package routing may combine a group of FLI terminals to a group of 2LI terminals based on electrical and manu- facturing considerations. Historically, there has been continued increase in demand for the numbers of contact terminals for both FLI and 2LI with every succeeding product generation. This is due to the inclusion of more functionality on the chip, higher data bandwidth between chips, and the need for smaller variation in supply voltage for the chip. The increased interconnect count leads to scaling of feature sizes across all domains of packaging. This trend is expected to continue as the semiconductor industry pursues the Moore’s law-driven roadmap. 22.2.1 Die-Package Interconnect The die-package interconnection for a flip chip package is typically made by a process called controlled collapse chip connection, or C4. In the original version of C4, solder bumps on the die were aligned on top of corresponding metal pads of the ceramic package and were then reflown to form joints with a controlled standoff height [8] . A variation of this chip joining process is predominantly used for organic packaging, and connects nonmelting die bumps to reflowable solder bumps on the package substrate. This process is also loosely referred to as a C4 process. Initially, die bumps for organic packages used high-melt (nonmelting) Pb–Sn sol- der (3–5% Sn and 97–95% Pb) with a melting temperature near 312°C. The sub- strate bumps used eutectic Sn–Pb solder with a melting temperature of 183°C (Fig. 22.6a ). Environmentally friendly considerations resulted in the use of Pb-free Morris_Ch22.indd 495Morris_Ch22.indd 495 9/29/2008 8:09:50 PM9/29/2008 8:09:50 PM 496 D. Mallik et al. material such as copper die bumps and SnAgCu (SAC) substrate solder as shown in Fig. 22.6b [3] . The increased number of terminals on a given chip size requires reduction in the die bump pitch to accommodate all the bumps. Figure 22.7 shows minimum input/ output (I/O) bump pitch trend for mainstream microprocessors. Finer bump pitch reduces C4 joint size and the space between the joints, creating technology chal- lenges related to the FLI. During the package assembly process, the finer bump pitch requires advanced equipment and material to precisely place the die and hold it in place until the C4 joints are formed. The smaller joint size reduces the solder volume and consequently the amount of solder collapse during the chip join reflow process. This demands good coplanarity for die bumps and for the mating package substrate contact area to reduce the risk of electrically open C4 joints. Fig. 22.6 Examples of flip chip C4 joints. ( a ) High lead die bump with ( b ) Cu die bump with SnAgCu (SAC) solder eutectic Pb–Sn solder Fig. 22.7 Minimum I/O bump pitch trend for Intel microprocessors Year M in im u m IO B u m p P it ch ( µ m ) 100 1998 2000 2002 2004 2006 2008 150 200 250 300 Morris_Ch22.indd 496Morris_Ch22.indd 496 9/29/2008 8:09:50 PM9/29/2008 8:09:50 PM 22 Flip Chip Packaging for Nanoscale Silicon 497 The finer bump pitch also impacts the choice of underfill material and process due to the reduction in horizontal spacing between the C4 joints and the reduction in verti- cal standoff height between the die and the package. The reduced space restricts the size of the filler particles, which are used in the underfill material to lower its coeffi- cient of thermal expansion (CTE) and to increase its fracture toughness. Also, the narrow spacing reduces control over the underfill flow dynamics, since the flow speeds may become more sensitive to manufacturing and design variations. Therefore, the finer bump pitch makes optimization of underfill process and material properties more challenging. At the same time, the reduced distance between the flip chip joints makes the FLI less tolerant to any voids and other defects, which may lead to increased material migration between neighboring joints. The small C4 joints need to deal with high current densities through them. These high current densities are a result of increasing total current (even at the same power consumption due to decreasing device voltage) and/or due to nonuniformity of on-chip current driven by variation in activity levels of devices at different loca- tions on the die. If not addressed properly through design, material, and process choices for the FLI, the high current density, in the presence of high silicon-chip temperature, may lead to electromigration-driven open failures [9] . Another important consideration for the design of the C4 joint is its influence on thermomechanical stresses in the on-chip interconnect. Over the past few genera- tions, silicon process engineers have focused on reducing the dielectric constant of the dielectric material (low k ) used in the on-chip interconnect. This has also resulted in lowering the mechanical strength of the on-chip interconnect making it more susceptible to failures induced by thermomechanical stresses due to packag- ing. The C4 joint needs to be compliant enough to minimize packaging-induced stresses on the silicon. In summary, the material and process choices for the FLI need to ensure assem- bly process scalability to smaller dimensions, while still providing compliancy between the silicon and the package, managing high current density through the joint, and being environmentally friendly. 22.2.2 Within Package Interconnect The bump pitch scaling drives the need for finer line width and spacing to route the signals from the on-chip terminals to the 2LI terminals. The high routing density is typically needed to escape the signal lines out of the congested area near the chip. Before we discuss the trend in within-package interconnect, we briefly describe the organic flip chip package substrate structure. Figure 22.8 shows a schematic of the cross section of an organic flip chip package substrate and a top view of its primary routing layer. The substrate is generally built around a core layer introduced to provide structural rigidity to the package. The core is made up of glass-fiber-reinforced polymer with mechanically drilled plated through-hole (PTH) vias, and conducting copper layers Morris_Ch22.indd 497Morris_Ch22.indd 497 9/29/2008 8:09:50 PM9/29/2008 8:09:50 PM 498 D. Mallik et al. fabricated by a subtractive photolithography process, which is similar to the widely used process for printed wiring board (PWB) technology. Typical thickness of the core is about 800 µm and the PTH diameter is about 250 µm. Buildup layers are added on both sides of the core layer, one symmetric pair at a time. A buildup layer is typically fabricated by first adding a relatively thin dielectric layer, generally, around 30-µm thick. Then, microvias, i.e., sub-100-µm diameter vias, are created by laser or other means. Copper patterns of about 15-µm thick are then added to form the interconnect layer and via connections to the underlying metal layer. The predominant process for forming the buildup layer conductors is the semiadditive process (SAP). Compared with the traditional subtractive process, the SAP enables formation of finer line widths and spaces on the package layers. The buildup layer pairs are sequentially added until the desired layer count is achieved. A protective solder resist layer is then added to the outer surfaces. This is followed by finish metallization such as electroless NiAu or NiPdAu for the C4 pads on the front side and 2LI pads on the backside. Finally, solder bumps are formed on the C4 pads to create an organic FCLGA package substrate. To create a FCPGA substrate, pins are soldered to the 2LI pads prior to chip assembly. For FCBGA, solder balls are attached to the 2LI pads after chip assembly. Typically, the C4 pad size is relatively large when compared with routing-line width and spacing. A large C4 pad diameter is used for various reasons. A large C4 pad size increases the joint size, which, in turn, improves resistance to joint crack- ing failure. A large pad lowers current density through the joint and enables high current carrying capability for the C4 joint by lowering electromigration. Also, a large C4 pad allows large solder volume. During the C4 joint formation process, the increased solder volume leads to higher solder collapse and helps achieve a high yielding C4 assembly process. Figure 22.8c shows a representative example of a routing scheme and dimensions for a flip chip package. The bump pitch scaling has consistently driven the line width and space to get finer (Fig. 22.9 ), and the trend is expected to continue. Finer features on the Fig. 22.8 Sketch of a typical organic flip chip package substrate Year M in im u n L in e W id th ( o r sp ac e) ( µ m ) 10 1998 2000 2002 2004 2006 2008 20 30 40 Morris_Ch22.indd 498Morris_Ch22.indd 498 9/29/2008 8:09:51 PM9/29/2008 8:09:51 PM 22 Flip Chip Packaging for Nanoscale Silicon 499 substrate bring a host of challenges to package substrate technology. These chal- lenges include technology to maintain adhesion of the resist and conductor materi- als during the photolithography process, and a clean process environment to minimize foreign material-related yield and reliability issues. From a different per- spective, the demand for fine line and space can be mitigated by aggressive reduc- tion in the microvia and C4 pad sizes. This would require innovation in substrate technology as well as assembly material and process technologies to produce mechanically robust via and C4 joint with high current-carrying capability. Innovative design techniques can also mitigate the demand on line and space scal- ing to some extent. One example of this would be to optimize the bump placement as demanded by high-density routing instead of placing the bumps on a fixed grid pattern. Another approach is to reduce the number of lines between the pads. This technique may require additional package layers, and hence higher cost, to do the escape routing, but would lower the demand for line and space scaling