74LVC4245A TI公司

www.ti.com FEATURES DESCRIPTION/ORDERING INFORMATION DB, DW, OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (5 V) VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND VCCB (3.3 V) VCCB (3.3 V) OE B1 B2 B3 B4 B5 B6 B7 B8 GND SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 • Bidirectional Voltage Translator • 5.5 V on A Port and 2.7 V to 3.6 V on B Port • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set at 3.3 V, and A port has VCCA, which is set at 5 V. This allows for translation from a 3.3-V to a 5-V environment, and vice versa.
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by VCCA. The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to align with the conventional '245 pinout. ORDERING INFORMATION TA PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74LVC4245ADW SOIC – DW LVC4245A Reel of 2000 SN74LVC4245ADWR SSOP – DB Reel of 2000 SN74LVC4245ADBR LJ245A –40°C to 85°C Tube of 60 SN74LVC4245APW TSSOP – PW Reel of 2000 SN74LVC4245APWR LJ245A Reel of 250 SN74LVC4245APWT (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1994–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com DIR OE A1 B1 To Seven Other Channels 2 3 22 21 Absolute Maximum Ratings (1) SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted) MIN MAX UNIT VCCA Supply voltage range –0.5 6.5 V A port (2) –0.5 VCCA + 0.5VI Input voltage range VControl inputs –0.5 6 VO Output voltage range A port (2) –0.5 VCCA + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through each VCCA or GND ±100 mA DB package 63 θJA Package thermal impedance (3) DW package 46 °C/W PW package 88 Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This value is limited to 6 V maximum. (3) The package thermal impedance is calculated in accordance with JESD 51-7. 2 www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions (1) Recommended Operating Conditions (1) SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 over operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted) MIN MAX UNIT VCCB Supply voltage range –0.5 4.6 V VI Input voltage range B port (2) –0.5 VCCB + 0.5 V VO Output voltage range B port (2) –0.5 VCCB + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCCB or GND ±100 mA DB package 63 θJA Package thermal impedance (3) DW package 46 °C/W PW package 88 Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This value is limited to 4.6 V maximum. (3) The package thermal impedance is calculated in accordance with JESD 51-7. for VCCA = 4.5 V to 5.5 V MIN MAX UNIT VCCA Supply voltage 4.5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VIA Input voltage 0 VCCA V VOA Output voltage 0 VCCA V IOH High-level output current –24 mA IOL Low-level output current 24 mA TA Operating free-air temperature –40 85 °C (1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. for VCCB = 2.7 V to 3.6 V MIN MAX UNIT VCCB Supply voltage 2.7 3.6 V VIH High-level input voltage VCCB = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCCB = 2.7 V to 3.6 V 0.8 V VIB Input voltage 0 VCCB V VOB Output voltage 0 VCCB V VCCB = 2.7 V –12IOH High-level output current mAVCCB = 3 V –24 VCCB = 2.7 V 12IOL Low-level output current mAVCCB = 3 V 24 TA Operating free-air temperature –40 85 °C (1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 www.ti.com Electrical Characteristics (1) Electrical Characteristics (1) SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 over recommended operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA MIN TYP (2) MAX UNIT 4.5 V 4.3 IOH = –100 µA 5.5 V 5.3 VOH V4.5 V 3.7 IOH = –24 mA 5.5 V 4.7 4.5 V 0.2 IOL = 100 µA 5.5 V 0.2 VOL V4.5 V 0.55 IOL = 24 mA 5.5 V 0.55 II Control inputs VI = VCCA or GND 5.5 V ±1 µA IOZ(3) A port VO = VCCA or GND 5.5 V ±5 µA ICCA VI = VCCA or GND, IO = 0 5.5 V 80 µA ∆ICCA(4) One input at 3.4 V, Other inputs at VCCA or GND 5.5 V 1.5 mA Ci Control inputs VI = VCCA or GND Open 5 pF Cio A port VO = VCCA or GND 5 V 11 pF (1) VCCB = 2.7 V to 3.6 V(2) All typical values are measured at VCC = 5 V, TA = 25°C.(3) For I/O ports, the parameter IOZ includes the input leakage current.(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated VCC. over recommended operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB MIN TYP (2) MAX UNIT IOH = –100 µA 2.7 V to 3.6 V VCC – 0.2 2.7 V 2.2 VOH IOH = –12 mA V3 V 2.4 IOH = –24 mA 3 V 2 IOL = 100 µA 2.7 V to 3.6 V 0.2 VOL IOL = 12 mA 2.7 V 0.4 V IOL = 24 mA 3 V 0.55 IOZ(3) B port VO = VCCB or GND 3.6 V ±5 µA ICCB VI = VCCB or GND, IO = 0 3.6 V 50 µA ∆ICCB(4) One input at VCCB – 0.6 V, Other inputs at VCCB or GND 2.7 V to 3.6 V 0.5 mA Cio B port VO = VCCB or GND 3.3 V 11 pF (1) VCCA = 5 V ± 0.5 V(2) All typical values are measured at VCC = 3.3 V, TA = 25°C.(3) For I/O ports, the parameter IOZ includes the input leakage current.(4) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated VCC. 4 www.ti.com Switching Characteristics Operating Characteristics Power-Up Considerations (1) SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1 and Figure 2) VCCA = 5 V ± 0.5 V,FROM TO VCCB = 2.7 V to 3.6 VPARAMETER UNIT(INPUT) (OUTPUT) MIN MAX tPHL 1 6.3A B ns tPLH 1 6.7 tPHL 1 6.1B A ns tPLH 1 5 tPZL 1 9OE A ns tPZH 1 8.1 tPZL 1 8.8OE B ns tPZH 1 9.8 tPLZ 1 7OE A ns tPHZ 1 5.8 tPLZ 1 7.7OE B ns tPHZ 1 7.8 VCCA = 4.5 V to 5.5 V, VCCB = 2.7 V to 3.6 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Outputs enabled 39.5 Cpd Power dissipation capacitance per transceiver CL = 0, f = 10 MHz pFOutputs disabled 5 TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems: 1. Connect ground before any supply voltage is applied. 2. Power up the control side of the device (VCCA for all four of these devices). 3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, keep DIR low. (1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021. 5 www.ti.com PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 2 × VCC Open GND 500 Ω 500 Ω VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS tPLH tPHL VOH VOL Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 1.5 V1.5 V VCC 0 V VOL + 0.3 V VOH - 0.3 V ≈0 V 3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf�≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. VCC 0 V 1.5 VInput 50% VCC 50% VCC 50% VCC 1.5 V 50% VCC VCC 0 V 1.5 V 1.5 V tw Input VOLTAGE WAVEFORMS PULSE DURATION SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 A PORT Figure 1. Load Circuit and Voltage Waveforms 6 www.ti.com PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 7 V Open GND 500 Ω 500 Ω VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NONINVERTING OUTPUTS tPLH tPHL VOH VOL Output Control Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 1.5 V1.5 V 3.5 V 0 V VOL + 0.3 V VOH - 0.3 V ≈0 V 3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Output tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf�≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. 3 V 0 V 1.5 VInput 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 3 V 0 V 1.5 V 1.5 V tw Input VOLTAGE WAVEFORMS PULSE DURATION SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 B PORT Figure 2. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LVC4245ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWT ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC4245APWTE4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2012 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74LVC4245APWTG4 ACTIVE TSSOP PW 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC4245A : • Enhanced Product: SN74LVC4245A-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74LVC4245ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74LVC4245ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74LVC4245APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 SN74LVC4245APWT TSSOP PW 24 250 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jan-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC4245ADBR SSOP DB 24 2000 346.0 346.0 33.0 SN74LVC4245ADWR SOIC DW 24 2000 346.0 346.0 41.0 SN74LVC4245APWR TSSOP PW 24 2000 346.0 346.0 33.0 SN74LVC4245APWT TSSOP PW 24 250 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jan-2012 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 9,907,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 2016 6,506,50 14 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–�8° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any