Gigabit CMOS Limiting Amplifier

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application Jungwon Han, Student Member, IEEE, Kwisung Yoo, Dongmyung Lee, Student Member, IEEE, Kangyeop Park, Student Member, IEEE, Wonseok Oh, Member, IEEE, and Sung Min Park, Member, IEEE Abstract—This paper presents a low-power, gigabit limiting amplifier (LA) for application to optical receivers that employ the negative impedance compensation technique not only to enhance the gain and bandwidth characteristics simultaneously, but also to allow low-voltage, low-power operations. Test chips of the LA were implemented in a standard 0.18- m CMOS process, demon- strating 2.5-Gb/s operation with 40-dB gain, 0.053-UI rms jitter for ��� � pseudorandom bit sequence inputs, 9.5-mV �� input sensitivity for �� �� bit error rate (BER), and 5.2-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of only 0.25 0.1 mm�. The proposed LA was adopted to realize a low-power, gigabit optical receiver. Fabricated using the same 0.18- m CMOS technology, the measured results of the optical receiver chip reveal 132.6-dB � transimpedance gain, 2.7-GHz bandwidth even with a large 1.5-pF input parasitic capacitance, 16-dBm optical sensitivity for 10 �� BER, and 51-mW power dissipation from a single 1.8-V supply. The area of the whole chip is 1.75 0.45 mm�. Index Terms—CMOS, DC-balanced transimpedance amplifier, limiting amplifier, negative impedance compensation, optical re- ceivers. I. INTRODUCTION T HE proliferation of Internet access and multimedianetworks has mandated the development of high-speed communication for enormous data. Therefore, optical com- munications have become very attractive even for short-reach applications, because optical communication systems can provide a number of advantages over copper-based systems, such as wider bandwidth, lower loss, lower crosstalk and elec- tromagnetic interference. Although most commercial products of optical systems have been implemented by using costly Manuscript received August 21, 2010; revised November 25, 2010; accepted December 21, 2010. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education, Science, and Technology under Contract 20100001557. J. Han, and S. M. Park are with the Department of Electronics Engineering, Ewha Womans University, Seoul 120-750, Korea (e-mail: hjw.jasmine@gmail. com; smpark@ewha.ac.kr). D. Lee and K. Yoo were with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, 120-749, Korea, and now are with the Semiconductor R&D Center, System LSI Business, Samsung Electronics Co., Ltd., Gyeonggi-Do 446-711, Korea. K. Park is with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea. W. Oh is with Korea Electronics Technology Institute, Seongnam 463-816, Korea. Digital Object Identifier 10.1109/TVLSI.2010.2104333 technologies such as GaAs, InP-based HBTs or SiGe HBT pro- cesses, CMOS technologies have been rapidly advanced over the past decades. Thus, the currently available, low-cost CMOS processes enable the fabrication of gigabit front-end circuits on a single silicon substrate along with other digital circuitry. Yet, deep-submicron CMOS devices demand significant scaling, i.e., low-voltage operations, thereby requiring novel circuit techniques to facilitate the stringent design constraints. A number of broadband techniques have been introduced to achieve wide bandwidth, including inductive peaking, reverse scaling, active feedback, and modified Cherry-Hooper. How- ever, the inductive peaking technique requires either a large chip area to implement passive inductors [1], [2] or a high supply-voltage to realize active inductors [3]–[5]. The reverse scaling technique may increase the power consumption due to the additional buffers [3], while the active feedback tech- nique needs large power dissipation to compensate the reduced DC-gain [6]. Finally, the modified Cherry-Hooper topology with negative capacitance still suffers the voltage-headroom issue, thus requiring zero- transistors [7]. In this work, the negative impedance compensation technique is incorporated to realize a low-power, low-voltage, gigabit lim- iting amplifier (LA) with a very small chip area [8]. Also, the proposed LA is applied to realize a low-power, gigabit optical receiver which consists of a DC-balanced transimpedance am- plifier (TIA), the LA, and an output buffer. Section II presents the architecture of the proposed, low-power, low-voltage LA. Section III demonstrates the measured results of the LA. Section IV describes the architec- ture of the differential optical receiver and the building blocks with its experimental results. Finally, the conclusion follows in Section V. II. CIRCUIT DESCRIPTION: PROPOSED LA Typically, a front-end optical receiver consists of a TIA, an LA, and a clock and data recovery (CDR) circuit. Among these blocks, LA particularly mandates high-gain and wide-band- width characteristics in order to guarantee the reliable operation of the following CDR circuit and to avoid intersymbol inter- ference (ISI) problems. In addition, it requires low noise characteristic to avoid degrading the input sensitivity even under a low supply voltage. Fig. 1(a) presents a conceptual schematic diagram of a conventional voltage amplifier, where the voltage gain is deter- mined by the transconductance and the output impedance 1063-8210/$26.00 © 2011 IEEE This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 1. Conceptual schematic diagrams of (a) a conventional voltage amplifier and (b) the improved voltage amplifier with negative impedance. . Although higher load resistance increases the midband voltage gain, it may incur a significant voltage drop across the resistor, thus prohibiting low-voltage operations. A novel remedy is to add a negative resistance in parallel with the load resistance, as shown in Fig. 1(b). Then, the total output resistance of the improved voltage amplifier is given by (1) where the negative resistance is selected to be close to so that the output resistance reaches a very high value, thereby producing a high midband gain. The negative resistor is implemented with active devices to avoid a large voltage drop across the load resistor. This, how- ever, decreases the 3-dB bandwidth rapidly due to both the in- creased output resistance and the parasitic capacitances from the active devices. Therefore, a negative capacitance circuit is added in parallel with the load capacitance to enlarge the bandwidth. Then, the total output capacitance is equal to , and the bandwidth can be significantly extended by selecting close to . Fig. 2 shows a block diagram of the proposed LA, consisting of an input buffer with 50- input-matching networks, four- stage gain cells, an offset cancellation feedback network, and an output buffer. Each gain cell includes the negative resistance and the negative capacitance circuits. Following careful considerations of design tradeoffs in LA, the number of the cascaded stages is set at four. This is because, for a circuit with identical stages in which each stage is an ideal voltage amplifier with the gain of and the 3-dB band- width of , the bandwidth of the overall circuit shrinks rapidly Fig. 2. Block diagram of the proposed LA. Fig. 3. Schematic diagrams of (a) the negative resistance circuit and (b) the negative capacitance circuit. [9]. Thus, it may provide high gain, but very limited bandwidth for a large . Nonetheless, the shrinkage of bandwidth becomes less than 15% even though increases from 5 to 10. Further- more, the gain per stage should become lower for a fixed overall gain, which may lead to rapid accumulation of input-referred noise [2]. Hence, each gain cell of this work is designed to pro- vide a 3-dB bandwidth of 6 GHz, which corresponds to a total bandwidth of 2.5 GHz. Fig. 3(a) depicts a schematic diagram of the negative resis- tance circuit, where the positive feedback loop formed by and causes the difference of the output currents to have opposite polarity with the differential voltage . Thus, the equivalent output resistance is given by , and the total output resistance is given by (2) Then, an extremely high output resistance can be obtained if is close to . Yet, the absolute value of the negative resistance should be kept smaller than to prevent latching. Fig. 3(b) presents a schematic diagram of the negative capaci- tance circuit [2], where the positive feedback is set so that the charge difference is in the opposite direction to that of the voltage difference . Then, the equivalent impedance of the negative capacitance circuit is given by for (3) This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. HAN et al.: LOW-POWER GIGABIT CMOS LA USING NEGATIVE IMPEDANCE COMPENSATION AND ITS APPLICATION 3 Fig. 4. Nyquist plot of the admittance of the negative capacitance circuit for the frequency range up to 2.5 GHz (� � 4 �m, � � ���� �m, � � 40 �A, � � 35 fF, and � � �� fF). Fig. 4 shows the Nyquist plot of the admittance of the negative capacitance circuit. The admittance of the load capacitance is always located on the imaginary axis because it is a positive capacitance, whereas the admittance of the negative ca- pacitance has both a real part and an imaginary part. Thus, the total output admittance hardly changes with increasing frequency due to the negative phase response of . This main- tains the high gain characteristic, while the negative capacitance enlarges the bandwidth of the LA. Fig. 5 illustrates the schematic diagram of a gain-cell in the proposed LA. The transfer function of the gain-cell is given by (4) Here, one zero and two poles occur in the transfer function as (5) For , the zero may be located at a lower fre- quency than the dominant pole , and this zero gives rise to a high-frequency peaking, thus extending the bandwidth. The poles of the proposed gain cell should always be negative to en- sure circuit stability, which requires the following inequality: (6) HSPICE simulations were conducted for this proposed LA by utilizing the model parameters of a standard 0.18- m CMOS technology. Fig. 6 shows the simulated frequency responses, where 16-dB larger voltage gain is achieved with the negative resistance and the 3-dB bandwidth is extended to 2.4 GHz Fig. 5. Schematic diagram of a gain cell in the proposed LA. Fig. 6. Simulated frequency responses of the proposed LA. by the negative capacitance. Namely, the total gain–bandwidth product is enhanced by a factor of 6.8 when compared with a conventional LA with simple differential pairs. III. EXPERIMENTAL RESULTS OF THE PROPOSED LA Test chips of the proposed LA were implemented in the 0.18- m CMOS process. Fig. 7 shows the chip microphoto- graph, where the chip core occupies an area of 250 100 m , and each pad includes an electrostatic discharge protection diode, with a parasitic capacitance of 0.5 pF. For the mea- surements, test chips were mounted on an FR-4 PC-board test fixture. Fig. 8 demonstrates the measured frequency response of the proposed LA, where the midband voltage gain of 41 dB and the bandwidth of 2.4 GHz are achieved, respectively. Fig. 9 presents the measured output eye-diagrams for 2.5-Gb/s input pseudorandom bit sequence (PRBS) with voltage levels of 10 mV , 100 mV , 500 mV , and 1 V . For all cases, the single-ended output voltage is mea- sured as 240 mV . Fig. 10 depicts the measured bit error rate (BER) for PRBS with various input signal levels, where the achieved elec- trical sensitivity is 9.5 mV for BER. Even for a large 1.2-V input overload-level, the measured BER remains below This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 7. Chip microphotograph of the proposed LA. Fig. 8. Measured frequency response of the proposed LA. . Hence, the dynamic range of the proposed LA is esti- mated to be greater than 42 dB. DC measurements reveal that the proposed LA chip dissipates only 5.2 mW from a single 1.2-V supply. Table I summarizes the performance in comparison with that of previously reported CMOS gigabit LAs. IV. APPLICATION: GIGABIT OPTICAL RECEIVER The LA proposed in the previous sections was applied to re- alize a low-power gigabit optical receiver. Fig. 11 illustrates the architecture of the differential optical receiver which consists of a dc-balanced transimpedance amplifier (TIA) and a four-stage LA with negative impedance compensation. A. DC-Balanced TIA The front-end TIA is one of the most critical blocks that de- termine the overall performance of the optical receivers, such Fig. 9. Measured eye-diagrams of the LA for 2.5-Gb/s � � � input PRBS with the following input voltage levels. (a) 10 mV . (b) 100 mV . (c) 500 mV . (d) 1.2 V . Fig. 10. Measured BER of the LA for 2.5-Gb/s � � � PRBS. as operation speed and sensitivity. Particularly, the degrada- tion of bandwidth caused by the large input parasitic capaci- tance from the optical device, i.e., p-i-n photodiode, has led to the development of several input configurations to alleviate the problem, such as common-source with input ladder filter [11], regulated cascode (RGC) [12], [13], and cascode with inductive peaking [14]. Among these, the RGC input configuration en- hances the effective input transconductance, thus lowering the input impedance significantly [12]. Thereby, large input para- sitic capacitance can be effectively isolated from the TIA band- width determination. Although both the common-source with ladder filter and the cascode with shunt-inductive peaking can relax the effect of the This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. HAN et al.: LOW-POWER GIGABIT CMOS LA USING NEGATIVE IMPEDANCE COMPENSATION AND ITS APPLICATION 5 TABLE I PERFORMANCE COMPARISON WITH THE PREVIOUSLY REPORTED CMOS GIGABIT LIMITING LAS Fig. 11. Architecture of the differential dc-balanced optical receiver with the proposed LA. Fig. 12. Simplified schematic diagram of the RGC TIA stage. Fig. 13. Chip microphotograph of the proposed optical receiver. large input parasitic capacitance, they require large chip areas due to the implementation of on-chip passive inductors [14]. In this work, the RGC input configuration (as shown in Fig. 12) is exploited to boost the effective transconductance of the input stage, thus providing virtual-ground impedance at the input node. This certainly relaxes the design tradeoff between gain and bandwidth [12]. Also, a third-order ladder filter network is employed as an ad- ditional input broadband circuit between the p-i-n photodiode and the RGC input stage. The ladder filter is easily realized by using a bond-wire inductor and an additional on-chip capacitor , since the photodiode is electrically mod- eled as a current source with a parasitic capacitance . Meanwhile, the TIA adopts a cascaded voltage-gain stage and a dc-balance buffer with a couple of low-pass filters (LPFs). The cascaded voltage-gain stage targets to achieve wide bandwidth, so that the total ac-response can guarantee the optimum speed even at the cost of signal gain. The dc-balance buffer takes the configuration of a current- mode-logic differential amplifier, where the size of its main tran- sistors is judiciously determined by simultaneous consideration of both the driving capability and the operation speed. The LPF comprises a couple of passive RC components, of which the cutoff frequency is designed to be a few hundred kHz in order to cancel the dc offsets generated in its differential structure. This provides a more suitable solution than the conventional large ac-coupling off-chip capacitors. B. Experimental Results The proposed optical receiver was fabricated using the same 0.18- m CMOS technology. Fig. 13 shows the chip micropho- This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS TABLE II PERFORMANCE SUMMARY AND COMPARISON WITH RECENTLY PUBLISHED GIGABIT CMOS OPTICAL RECEIVERS ���� � ��� Fig. 14. Measured optical eye-diagrams of a single-ended output of the optical receiver for � � PRBS at the following different data rates of (a) 1.25 Gb/s, (b) 2 Gb/s, (c) 2.5 Gb/s, and (d) 3.125 Gb/s. tograph, where the whole chip occupies the area of 1.75 0.45 mm . For optical measurements, the chip is integrated with a GaAs p-i-n photodiode on an FR-4 chip-on-board assembly. The responsivity of the p-i-n photodiode is 0.6 A/W at a wave- length of 850 nm and its parasitic capacitance is 1.5 pF under 3.3-V reverse bias voltage. Fig. 14 demonstrates the optically measured eye-diagrams for PRBS inputs at different data rates of 1.25, 2, 2.5, and 3.125 Gb/s. Here, the single-ended output voltage levels are measured to be 200 mV with a 25- equivalent output load resistance. Fig. 15 depicts the measured frequency response of the optical receiver, achieving a measured transimpedance gain of 132.6 dB and a 3-dB bandwidth of 2.7 GHz even for the large 1.5-pF input capacitance. This corresponds to a tran- simpedance gain-bandwidth product of 11.5 GHz . Also, the average input noise current spectral density is obtained to be Fig. 15. Measured frequency response of the optical receiver and its equivalent input noise current spectral density. 47 pA/sqrt(Hz), which corresponds to the optical sensitivity of 16 dBm for the BER of . DC measurements reveal that the whole optical receiver chip dissipates 51 mW from a single 1.8-V supply. Table II summa- rizes the performance of the proposed optical receiver in com- parison with recently published gigabit CMOS optical receivers. V. CONCLUSION A low-voltage gigabit LA was realized in a 0.18- m CMOS process, incorporating the negative impedance compensation technique to obtain low-power, high-gain, wide-bandwidth, and small chip-area characteristics simultaneously. This LA circuit was successfully exploited to realize a gigabit optical receiver in the same 0.18- m CMOS technology. The measured results of the proposed optical receiver confirm the circuit techniques, and This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 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