DEI1016

©2005DeviceEngineeringInc.Page1of17DS-MW-01016-01RevA01/07/2005Features•TwoReceiversandOneTransmitter•IndustryStandardPinforPinReplacementPart•WraparoundSelf-Testmode•Wordlengthcanbeconfiguredfor25bitor32bitsoperation•ParityStatusandgenerationofReceiveandTransmitWords•8WordTransmitterbuffer•LowPowerCMOSprocessing•SupportsmultipleARINCprotocols:429,571,575,706•Availableinextended(-55/+85°C)andMilitary(-55/+125°C)temperaturerangesGeneralDescription:TheDEI1016providesaninterfacebetweenastandardavionicstypeserialdigitaldatabusanda16-bit-widedigitaldatabus.Theinterfacecircuitconsistsofasinglechanneltransmitterwithan8X32bitbuffer,twoindependentreceivechannels,andahostprogrammablecontrolregistertoselectoperatingoptions.Thetworeceiverchannelsoperateidentically,eachprovidingadirectelectricalinterfacetoanARINCdatabus.Thetransmittercircuitcontainsan8wordby32bitbuffermemoryandcontrollogicwhichallowsthehosttowriteablockofdataintothetransmitter.Theblockofdataistransmittedautomaticallybyenablingthetransmitterwithnofurtherattentionbythehostcomputer.DataistransmittedinTTLformatontheD0(A)/D0(B)outputpins.ThesignalformatiscompatiblewithDEI’sextensivelineofARINC429LinedriversforeasyconnectiontotheARINCdatabus.DEI1016/DEI1016A/DEI1016B/DEI1016CARINC429TransceiverFamily385EastAlamoDriveChandler,AZ85225Phone:(480)303-0822Fax:(480)303-0824E-mail:info@deiaz.comDeviceEngineeringIncorporatedControlRegisterTXFIFO8WordsX32BitsReceiveDecoderReceiveDecoderTransmitEncoderARINC429Receive0ARINC429Receive1SelfTestDataARINC429TransmitDATABUSHostInterface/DR1,/DR2TXR/OE1,/OE2/LD1,/LD2ENTX/LDCW/DBCEN/MR323232321616Figure1:DEI1016BlockDiagram©2005DeviceEngineeringInc.Page2of17DS-MW-01016-01RevA01/07/2005Table1:DEI1016AbsoluteMaximumRatingsPARAMETERSYMBOLMINMAXUNITSSupplyVoltageVDD-0.5+7.0VDCInputVoltage(exceptpinsDI1(A,B)andDI2(A,B))VIN-0.6VCC+0.6VVoltageatpinsDI1(A,B)andDI2(A,B)VIN±29VClampdiodecurrent,anypinexceptDIinputs±25mADCOutputCurrentperpin±25mADCVorGNDcurrentperpin±50mAStorageTemperatureTSTG-65+150°CJunctionTemperature,operatingTJmax+145°CLeadTemperature(soldering,10sec)TLead+275°C1MCKClockFrequency1.16MHzTable2:DEI1016DCElectricalCharacteristicsUnlessnoted,operatingconditions:VDD=5V±10%,ExtendedTempDevices:Ta=-55ºCto+85ºC,MilitaryTempDevices:Ta=-55ºCto+125ºCPARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSARINCLINEINPUTSLogic1InputVoltageVIHVDIFFDI(A)andDI(B)6.51013VLogic0InputVoltageVILVDIFFDI(A)andDI(B)-6.5-10-13VNullInputVoltageVNULVDIFFDI(A)andDI(B)-2.50+2.5VCommonModeVoltageVCM-5+5VDifferentialInputImpedanceRI12kΩInputImpedancetoVDDRH12kΩInputImpedancetoGNDRG12kΩDifferentialInputCapacitanceCI20pFInputCapacitancetoVDDCH20pFInputCapacitancetoGNDCG20pFLOGICINPUTS(includingbi-directional)LowLevelInputVoltageVIL0.8VHighLevelInputVoltageVIH2.0VInputLeakageCurrentIINVIN=GNDtoVDD-10+10µAInputCapacitanceCIN15pFLOGICOUTPUTS(includingbi-directional)HighLevelOutputVoltageVOHIOH=20µA(CMOS)IOH=6mA(TTL)VDD–0.12.7VLowLevelOutputVoltageVOLIOL=20µA(CMOS)IOL=6mA(TTL)0.10.4VPOWERSUPPLYINPUTSupplyCurrentIDD1MCK=1MHz510mASupplyVoltageVDD4.555.5VDC©2005DeviceEngineeringInc.Page3of17DS-MW-01016-01RevA01/07/2005Table3:DEI1016ACElectricalCharacteristicsPARAMETERSYMBOLDataRate100kbpsDataRate12.5kbpsMINMAXMINMAXUNITS1MCKFrequencyf1MCK1.011.01MHz1MCKDutyCycleCKDC40604060%1MCKRise/FallTimeTCRF1010nsMasterResetPulseWidthTMR200200nsTransmitterDataRate(1MCK=1MHz)TDR9910112.412.6kbpsReceiverDataRate(1MCK=1MHz),(DATA=50%BIT/50%NULLTIME)RDR951058.014.5kbpsTable4:PinDefinitionsSYMBOLDEFINITIONVDDPowerInput.+5VDC±10%GNDPowerReturnandSignalGround.DI1(A)ARINC429Input.ReceiverChannel1,“A”inputDI1(B)ARINC429Input.ReceiverChannel1,“B”inputDI2(A)ARINC429Input.ReceiverChannel2,“A”inputDI2(B)ARINC429Input.ReceiverChannel2,“B”input/DR1LogicOutput.DataReady,Receiver1.ALowoutputindicatesvaliddatainreceiver1./DR2LogicOutput.DataReady,Receiver2.ALowoutputindicatesvaliddatainreceiver2.SELLogicInput.Receiverwordselect.ALowinputselectsreceiverWord1;HiselectsWord2tobereadonD[15:0]port./OE1LogicInput.Receiver1OutputEnable.ALowinputenablestheD[15:0]porttooutputReceiver1data.Word1orWord2willbeoutputasdeterminedbytheSELinput./OE2LogicInput.Receiver2OutputEnable.ALowinputenablestheD[15:0]porttooutputReceiver2data.Word1orWord2willbeoutputasdeterminedbytheSELinput.D[15:0]LogicInput/Tri-stateOutput.This16-bitbi-directionaldataportistheuPdatainterface.Receiverdataisreadfromthisport.ControlRegisterandTransmitterFIFOdataiswrittenintothisport./LD1LogicInput.LoadTransmitterWord1.ALowinputpulseloadsWord1intotheTransmitterFIFOfromD[15:0]./LD2LogicInput.LoadTransmitterWord2.ALowinputpulseloadsWord2intotheTransmitterFIFOfromD[15:0].TXRLogicOutput.TransmitterReady.AHioutputindicatestheTransmitterFIFOisemptyandreadytoacceptnewdata.DO(A)LogicOutput.Transmitterserialdata‘A’output.Thisisareturn-to-zeroformatsignalwhichwillnormallyfeedanARINC429LineDriverIC.AHioutputindicatestheTransmitterdatabitisa1.Thesignalreturnstozeroforsecondhalfofbittime.DO(B)LogicOutput.Transmitterserialdata‘B’output.Thisisareturn-to-zeroformatsignalwhichwillnormallyfeedanARINC429LineDriverIC.AHioutputindicatestheTransmitterdatabitisa0.Thesignalreturnstozeroforsecondhalfofbittime.ENTXLogicInput.EnableTransmitter.AHiinputenablestheTransmittertosenddatafromtheTransmitterFIFO.ThismustbeLowwhilewritingdataintoTransmitterFIFO.Transmittermemoryisclearedbyhigh-to-lowtransition./LDCWLogicInput.LoadControlRegister.ALowinputpulseloadstheControlRegisterfromD[15:0].1MCKLogicInput.ExternalClock.MasterclockusedbyboththeReceiversandTransmitter.The1MHzrateisaX10clockfortheHIdatarate(100kbps),andaX80clockforLOdatarate(12.5kbps).TXCKLogicOutput.TransmitterClock.Thisoutputsaclockfrequencyequaltothetransmitdatarate.Theclockisalwaysenabledandinphasewiththedata.TheoutputisHiduringthefirsthalfofthedatabittime./MRLogicInput.MasterReset.ALoinputresetstheTransmitterFIFO,bitcounters,wordcounter,gaptimers,/DRx,andTXR.TheControlRegisterisnotaffected.Usedonpowerupandsystemreset./DBCENLogicInputwithinternalpulluptoVDD.DataBitControlEnable.ALowinputenablesthetransmitterparitybitcontrolfunctionasdefinedbycontrolregisterbit4(PAREN).AHiinputforcestransmitterparitybitinsertionregardlessofPARENvalue.Thepinisnormallyleftopenortiedtoground.©2005DeviceEngineeringInc.Page4of17DS-MW-01016-01RevA01/07/2005Table6:DEI1016ControlWordNAMEDATABITDESCRIPTIONPAREND4TransmitterParityEnable.Enablesparitybitinsertionintotransmitterdatabit32.Parityisalwaysinsertedif/DBCENisopenorHI.If/DBCENisLO,Logic“0”onPARENinsertsdataonbit32,andLogic“1”onPARENinsertsparityonbit32./SLFTST1D5SelfTestEnable.Logic“0”enablesa“wraparound”testmodewhichinternallyconnectsthetransmitteroutputstobothreceiverinputs,bypassingthereceiverfrontend.Thetestdataisinvertedbeforegoingintoreceiver2sothatitsdataisthecomplementofthatreceivedbyreceiver1.Thetransmitteroutputisactiveduringtestmode.SDEN12D6S/DCodeCheckEnableforreceiver1.Logic“1”enablestheSource/DestinationDecoderforreceiver1.X1,Y12D7,D8S/DcomparecodeRX1.Ifthereceiver1S/Dcodecheckisenabled(SDENB1=1),thenincomingreceiverdataS/DfieldswillbecomparedtoX1,Y1.Iftheymatch,thewordwillbeacceptedbyreceiver1;ifnot,itwillbeignored.X1(D7)iscomparedtoserialdatabit9,Y1(D8)iscomparedtoserialdatabit10.SDEN22D9S/DCodeCheckEnableforreceiver1.Logic“1”enablestheSource/DestinationDecoderforreceiver1.X2,Y22D10,D11S/DcomparecodeRX2.Ifthereceiver2S/Dcodecheckisenabled(SDENB2=1),thenincomingreceiverdataS/DfieldswillbecomparedtoX2,Y2.Iftheymatch,thewordwillbeacceptedbyreceiver2;ifnot,itwillbeignored.X2(D10)iscomparedtoserialdatabit9,Y2(D11)iscomparedtoserialdatabit10.PARCKD12ParityCheckEnable.Logic“1”invertsthetransmitterparitybitfortestofparitycircuits.Logic“0”selectsnormaloddparity;logic“1”selectsevenparity.TXSEL3D13TransmitterDataRateSelect.Logic“0”setsthetransmittertotheHIdatarate.HIrateisequaltotheclockratedivided10.Logic“1”setsthetransmittertotheLOdatarate.LOrateisequaltotheclockratedividedby80.RCVSEL4D14ReceiverDataRateSelect.Logic“0”setsbothreceiverstoaccepttheHIdatarate.ThenominalHIdatarateistheinputclockdividedby10.Logic“1”setsbothreceiverstotheLOdatarate.ThenominalLOdatarateistheinputclockdividedby80.WLSEL5D15WordLengthSelect.Logic“0”setsthetransmitterandreceiverstoa32bitwordformat.Logic”1”setsthemtoa25bitwordformat.NOTUSEDD0-D3Whenwritingtothecontrolregister,thefour“notusedbits”are“don’tcare”bits.Thesefourbitswillnotbeusedonthechip.NOTES1)Thetestmodeshouldalwaysconcludewithtennull’s.Thissteppreventsbothreceiversfromacceptinginvaliddata.2)SDENBn,Xn&Ynshouldbechangedwithin20bittimesafter/DRngoeslowandthebitstreamhasbeenread,orwithin30bittimesafteramasterresethasbeenremoved.3)TXSELshouldonlybechangedduringthetimethatTXRishighorMasterResetislow.4)RCVSELshouldbechangedonlyduringaMasterResetpulse.Ifchangedatanyothertime,thenthenextbitstreamfrombothReceiver1andReceiver2shouldbeignored.5)WhenthecontrolwordiswrittentheeffectoftheWLSELbitwilltakeeffectimmediatelyonthefirstcompleteARINCwordreceivedortransmittedfollowingthecontrolwordwriteoperation.FunctionalDescription:TheDEI1016supportsanumberofvariousoptionswhichareselectedbydatawrittenintothecontrolregister.Dataiswrittenintothecontrolregisterfromthe16-bitdatabuswhenthe/LDCWsignalispulsedtoalogic“0”.Thetwelvecontrolbitscontrolthefollowingfunctions:1)WordLength(32or25bits)2)Transmitterbit32(ParityorData)3)Wraparoundselftest.4)SourceDestinationcodecheckingofreceiveddata.5)Transmitterparity(evenorodd)6)TransmitterandReceiverdatarate(100or12.5kbps)Table5:ControlRegisterFormatBITSYMBOLBITSYMBOLD15(MSB)WLSELD7X1D14RCVSELD6SDENB1D13TXSELD5/SLFTSTD12PARCKD4PAREND11Y2D3NOTUSEDD10X2D2NOTUSEDD9SDENB2D1NOTUSEDD8Y1D0NOTUSED©2005DeviceEngineeringInc.Page5of17DS-MW-01016-01RevA01/07/2005DataFormat:TheARINCserialdataisshuffledandformattedintotwo16bitwords(WORD1andWORD2)usedbythebi-directionaldatabusinterface.Figure2showsthemappingbetweenthe32bitARINCserialdataandthetwodatawords.Figure3describesthemappingforthe25bitserialwordusedwhencontrolregisterbitWLSELissettologic“1”.Figure3:MappingofSerialDatato/fromWord1andWord2in25bitformat.Figure3:MappingofSerialDatato/fromWord1andWord2in25bitformat.©2005DeviceEngineeringInc.Page6of17DS-MW-01016-01RevA01/07/2005ReceiverOperation:Sincethereceiversfunctionidentically,onlyonewillbediscussedindetail.Thereceiverconsistsofthefollowingcircuits.LineReceiverThefrontendoftheLineReceiverfunctionsasavoltageleveltranslator.Ittransformsthe±10voltdifferentialARINCdatasignalsinto5Voltinternallogiclevels.Thelinereceiversareprotectedagainstshortsto±29Voltsandprovidescommonmodevoltagerejection.TheoutputsoftheLineReceiverareoneoftwoinputstotheSelf-TestDataSelector.TheotherinputtotheDataSelectoristheself-testsignalfromthetransmittersection.Theself-testsignalsareinvertedgoingintoReceiver2.ThedataselectoriscontroledbyControlRegisterbitD5(SLFTST).thereceivedwordhasanoddnumberof1’s(noerror).Logic“1”indicatesthereceivedwordhasanevennumberof1’s(errorcondition).Ifthedataformathasdatainbit32insteadofparity,theusersoftwaremustcalculatethevalueofthe32ndbit.IfWord1andWord2togetherhaveanevennumberof1’s,thendatabit32isalogic“1”.Otherwise,itisalogic“0”.DataAccessToaccessthereceiverdata,theusersetsthereceiverdataselectinput(SEL)toalogic“0”andpulsestheoutputenable(/OEn)linewithalogic“0”.ThiscausesDataWord1tobeplacedonthe16bitdatabus.ToreadWord2,theusersetsthedataselectinput(SEL)toalogic“1”andpulsestheoutputenable(/OEn)lowtoplaceWord2onthedatabus.WhenbothWord1andWord2havebeenread,DRnwillbereset.Thisresetistriggeredbytheleadingedgeofthefinal/OEnpulse.Ifanewdatawordisreceivedbeforethepreviousdatahasbeenreadfromthereceiverbuffer(asindicatedbythe/DRnsignalflip-flop),thereceivebufferwillnotbeoverwrittenbythenewdata.Thenewdatawillremainintheshiftregisteruntileitherthe/DRnsignalisresetanditcanbewrittenintothereceivebufferoritisoverwrittenbythenextincomingdataword.Dataintheshiftregisterwillbeoverwrittenbynewincomingdata,whiledatathathasbeenlatchedintothereceivebuffercannotbeoverwritten.DataErrorConditionsIfthereceiverinputdatawordstringisbrokenbeforetheentiredatawordisreceived,thereceiverwillresetandignorethepartiallyreceiveddataword.Ifthereceiverinputdatawordstringisnotproperlyframedwithatleast1nullbitbeforethewordand1nullbitaftertheword,thereceiverwillresetandignoretheimproperlyframeddataword.TransmitterOperation:Thetransmittersectionconsistsofan8wordby32bitFIFO,paritygenerator,transmitterwordgaptimer,andaTTLoutputcircuit.FIFOBufferThe8x32buffermemoryallowstheusertoloadupto8wordsintothetransmitter,enableit,andthenignoreitwhilethetransmittershipsoutthedatawithoutfurtherattention.Dataisloadedintothebufferbypulsing/LD1toloadthefirst16bits(WORD1)fromthedatabus,andpulsing/LD2toloadWORD2./LD1mustalwaysprecede/LD2.Thetransmittermustalwaysbedisabledwhileloadingthebuffer(ENTX=logic"0").Ifthebufferisfullandnewdataispulsedwith/LD1and/LD2,thelast32bitwordinthebufferwillbeoverwritten.DatawillremaininthebufferuntilENTXispulsedtoalogic“1”,whichwillactivatetheFIFOclockanddataisshiftedoutseriallytothetransmitterdriver.Figure4:LineReceiverBlockDiagramIncomingDataTheincomingdata(eitherselftestorARINC)istriplesampledbythewordgaptimertogenerateadataclock.Thestartofeachbitisfirstdetectedandthenverifiedtworeceive-clockcycleslater.Thereceiveclockis1MHzforHIspeedand125KHzforLOspeedoperationandisgeneratedbytheReceiver/Transmittertimingcircuit.Thereceiveclockistentimesthenormaldataratetoensurenodataambiguity.DataClockThederiveddataclockthenshiftsthedatadowna32bitlongDataShiftRegister.Thedatawordlengthisselectableforeither25or32bitslongbyControlRegisterBitWLSEL.Assoonasthedatawordiscompletelyreceived,aninternalsignalisgeneratedbythewordgaptimercircuittoenableloadingdataintothe32bitreceivebufferlatch.S/DDecoderTheSource/Destinationdecodercomparestheusersetcode(XandY)withbits9and10ofthedataword.ThedecodercanbeenabledanddisabledbytheSDENBbitoftheControlRegister.Ifthetwocodesarematched,asignalisgeneratedtolatchinthereceiveddataintothereceiverbuffer.Otherwisethedatawordisignoredandnotlatchedintothereceivebuffer.Ifthedataislatched,thedatareadyflag(/DRn)issettoindicatetotheuserthatavaliddatawordisreadytoberead.ParityControlTheparityoftheincomingmessageischeckedwheneitherwordofthereceiverisread.Logic“0”indicates©2005DeviceEngineeringInc.Page7of17DS-MW-01016-01RevA01/07/2005FIFOBuffer(continued)Thebufferdataistransmitteduntilthelastwordinthebufferisshiftedout.Atthistimeatransmitterreadysignal(TXR)issettoalogic“1”indicatingthatthebufferisemptyandreadytoreceiveuptoeightmoredatawords.WritingintothebuffermemoryisdisabledwhenENTXissettologic“1”.TransmitterReadySignal(TXR)Thetransmitterreadyflag(TXR)issettologic“0”withthefirstoccurrenceofan/LD2pulsetoindicatethatthebufferisnotempty.OutputRegisterTheoutputregisterisdesignedsuchthatitcanshiftoutawordof25bitsor32bits.Thelengthiscontrolledbycontrolregisterbit"WLSEL".TXWordGapTimerTheTXwordgaptimercircuitinsertsa4bittimegapbetweenwords.Thisgivesaminimumrequirementofa29bittimeora36bittimeforeachwordtransmission.The4bittimegapisalsoautomaticallymaintainedwhenthenextnewblockofdataisloadedintothebuffer,whichmaytakelessthanonebittime.ParityGeneratorTheparitygeneratorcalculateseitheroddorevenparityasspecifiedbycontrolregisterbit"PARCK".Oddparityisnormallyused;evenparityisavailabletotestthereceiverparitycheckcircuit.Oddparitymeansthatthereisanoddnumberof1'sinthe25or32bitserialword.Bit8ofwordoneisreplacedwithaparitybitifparityisselectedbythecontrolregisterbit"PAREN"andthe/DBCENpin.Otherwise,bit8ispassedthroughasdata.TransmitterOutputThetransmitterdriveroutputsthreeTTLcompatiblesignals:1)DO(A),2)DO(B),and3)TXCLK.DO(A)andDO(B)arethetransmitterdataintworail,return-to-zeroformat.DO(A)indicatesalogic"1"databitbygoingtoa"1"forthe1sthalfofabittime,thenreturningto"0"forthe2ndhalf;DO(B)remainsat"0"forthewholebittime.Inthesamefashion,DO(B)indicatesalogic"0"databitbypulsingHIwhileDO(A)remainsLO.AnullbitisindicatedwhenbothsignalsremainLO.Itisillegalforbothsignalstobelogic"1".TheTXCLKisafreerunningclocksignalof50%dutycycleandinphasewithtransmitterdata.Theclockwillalwaysbelogic"1"duringthefirsthalfofabittime.Power-UpResetAninternalpower-upresetcircuitpreventserroneousdatatransmissionbeforeanexternalmasterresethasbeenapplied.25-bitWordOperation:TheTRANSCEIVERimplementsa25bitwordformatwhichmaybeusedinnon-ARINCapplicationstoenhancedatatransferrate.Theformatisasimplifiedversionofthe32bitARINCwordandisdescribedinFigure3.Itconsistsofan8bitlabel,a16bitdataword,andaparitybit.Theparitybitcanoptionallybereplacedwitha17thdatabit.TheSource/Destinationcodecheckingoptioncanbeenabledineitherreceiver.Itwilloperateonbits9and10ofthe25bitword.Self-TestOperation:Byselectingthecontrolregisterbit(/SLFTST)selftestoption,theusermayperformafunctionaltestoftheTRANSCEIVERandsupportcircuitry.Theusercanwritedataintothetransmitteranditwillbeinternallywrappedaroundintobothreceivers.Theusercanthenverifyreceptionandintegrityofthedata.Thereceiverlineinterfaceandtheuser'slinedriverswillnotbetested.Bysettingthetransmittertouseevenparity,theusercantestthereceiver'sparitycircuitoperation.Power-upresetandMasterReset:TheusermustapplyanactiveLopulsetotheMasterResetpin(/MR)afterpoweruporuponsystemreset.Precedingthemasterresetatpower-upaninternalpower-upresetoccurswhichwillclearthetransmittersuchthatnoerroneousserialdatastreamwillbetransmittedbeforemasterreset.Receivers,controlregister,andinternalcontrollogicareresetbymasterreset.Afterresettingthedevice,theusermustprogramthecontrolregisterbeforebeginningnormaloperation.Thecontrolregistermaybereprogrammedwithoutadditionalresetpulses.ProcessorInterface:Figure7showsatypicalresetandinitializationsequence.Theusermustpulsethe/MRpinlowtoresetthedevice.ToloadtheControlRegisterfromthedatabus,the/LDCWpinispulsedlowwhilethedesiredcontroldataisappliedonthedatabus.Figure5showsatypicaltransmitterloadingsequence.Itbeginswiththetransmittercompletingtransmissionofthepreviousdatablock.TheTXRflaggoesHItonotifytheuserthatdatamaybeloadedintothebuffer.TheusersetsENTXtoLOtodisabletheTransmitterandproceedstoloadatotalofsixARINCwordsintothebuffer.(Notethatuptoeightwordscouldhavebeenloaded).TheuserthenenablesthetransmitterbysettingENTXtoalogic"1"andthetransmitterbeginsit'ssequenceofsendingoutdatawords.Althoughnotshowninthefigure,thetransmitterloadingsequencecanbeinterruptedbyreceiverreadingcyclewithnointerferencebetweenthetwooperations.Figure6showsatypicalreceiverreadingsequence.Bothreceiversnotifytheuserofvaliddatareadybysettingtheirrespective/DRnlinestologic"0".TheuserrespondsbyfirstreadingthetwodatawordsfromReceiver1andthenfromReceiver2.TheSELlineisnormallyasystemaddresslineandmayassumeanystate,butmustbevalidwhenthe/OEnlineispulsedlow.©2005DeviceEngineeringInc.Page8of17DS-MW-01016-01RevA01/07/2005Figure5:TypicalTransmitterLoadSequenceFigure5:TypicalTransmitterLoadSequenceFigure6:TypicalReceiverReadSequenceFigure6:TypicalReceiverReadSequence©2005DeviceEngineeringInc.Page9of17DS-MW-01016-01RevA01/07/2005ValidDataMRLDCWD[15:0]tMRtPWLDtSDWtHDWFigure7:ResetandInitializationSequencetHSELtDOEDRtOEOEtDDROEtPWOEtSSELARINCDATABIT31BIT32Word1ValidWord2ValidtDDRN/DR1,/DR2/OE1,/OE2SELD[15:0]tDDRtDTSFigure8:ReceiverReadOperationandTimingFigure9:TransmitterWriteOperationandTiming©2005DeviceEngineeringInc.Page10of17DS-MW-01016-01RevA01/07/2005Figure10:TransmitterTimingDiagramTable7:DEI1016ACTimingCharacteristicsPARAMETERSYMBOLDataRate100kbpsDataRate12.5kbpsMINMAXMINMAXUNITSWRITECYCLETIMING/LD1,/LD2and/LDCWPulseWidthtPWLD130130nsDelaybetweenconsecutiveLoadPulsestLL00nsDatato/LD⇑Set-UpTimetSDW110110nsDatato/LD⇑HoldTimetHDW00nsDelay/LD2⇑toTXR⇓tDTXR840840nsREADCYCLETIMINGDelay,Bit32/25into/DR⇓tDDRN16128µsDelay,/DRn⇓to/OEn⇓tDDROE00ns/OE1or/OE2PulseWidthtPWOE200200nsDelaybetweenconsecutive/OEpulsestOEOE5050nsDelay,2nd/OE⇑to/DRn⇑tDOEDR200200nsSELto/OE⇓tovaliddatatSSEL2020nsSELto/OE⇑holdtimetHSEL2020nsDelay/OE⇓tovaliddatatDDR200200nsSELto/OE⇑todataHI-ZtDTS10501050nsTRANSMITTERTIMINGDelay,ENTX⇑tooutputdata1tDTD25200µsOutputDatanulltimetNUL4.955.0539.640.4µsOutputdatabittimetBIT4.955.0539.640.4µsDataskewbetweenTXCK⇑(⇓)andDO⇑(⇓)tSKTX0±500±50nsDatawordgaptimetGAP39.640.4316.8323.2µsDelay,endofTXWordtoTXR⇑tDTXR5050nsDelay,TXR⇑toE