双2-4译码器(74139)双2-4译码器(74139)
-- Dual 2-to-4 Decoder
-- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL
-- download from: www.pld.com.cn & www.fpga.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT139 is
port(A2, B2...
双2-4译码器(74139)
-- Dual 2-to-4 Decoder
-- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL
-- download from: www.pld.com.cn & www.fpga.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT139 is
port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;
Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic); end HCT139;
architecture VER1 of HCT139 is
begin
Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';
Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';
Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';
Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';
Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';
Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';
Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';
Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1'; end VER1
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