EDA技术实验
报告
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册
班 级：
姓 名：
学 号：
指导教师：
开课时间: 2013 至 2014 学年第 1 学期
实验名称
交通灯信号控制设计
实验时间
2013年12月05日
姓 名
实验成绩
一、实验目的
1.掌握VHDL语言的基本结构。
2.掌握VHDL层次化的设计
方法
快递客服问题件处理详细方法山木方法pdf计算方法pdf华与华方法下载八字理论方法下载
。
3.掌握VHDL基本逻辑电路的综合设计应用。
二、实验设备
计算机软件：Quartus II
EDA实验箱。主芯片：EPM7128SLC84-15或EP1K100QC208-3。下载电缆，导线等。
三、实验内容
设计并调试好一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器，具体要求如下：
1.主、支干道各设一个绿、黄、红指示灯，两个显示数码管。
2.主干道处于常允许通行状态，而支干道有车来时才允许通行。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯。
3.当主、支干道均有车时，两者交替允许通行，主干道每次放行45S，支干道每次放行25S，在每次由亮绿灯变成亮红灯的转换过程中，要亮5S的黄灯作为过渡，并进行减计时显示。
要求编写交通灯控制器电路逻辑图中的各个模块的VHDL语言程序，并完成交通灯控制器的顶层设计，然后利用开发工具软件对其进行编译和仿真，最后要通过实验开发系统对其进行硬件验证。
（一）编写交通灯控制器JTDKZ模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JTDKZ IS
PORT(CLK, SM, SB: IN STD_LOGIC;
MR, MY, MG, BR, BY, BG: OUT STD_LOGIC);
END ENTITY JTDKZ;
ARCHITECTURE ART OF JTDKZ IS
TYPE STATE_TYPE IS(A, B, C, D);
SIGNAL STATE: STATE_TYPE;
signal cnt:integer range 0 to 45;
BEGIN
PROCESS(CLK) IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
CASE STATE IS
WHEN A=>
IF(SB AND SM)='1' THEN
IF CNT=44 THEN
CNT<=0; STATE<=B;
ELSE
CNT<=CNT+1;STATE<=A;
END IF;
ELSIF(SB AND (NOT SM))='1' THEN
STATE<=B; CNT<=0;
ELSE STATE<=A; CNT<=0;
END IF;
WHEN B=>
IF CNT=4 THEN
CNT<=0;STATE<=C;
ELSE
CNT<=CNT+1;STATE<=B;
END IF;
WHEN C=>
IF(SM AND SB)='1' THEN
IF CNT=24 THEN
CNT<=0; STATE<=D;
ELSE
CNT<=CNT+1;STATE<=C;
END IF;
ELSIF SB='0' THEN
STATE<=D; CNT<=0;
ELSE STATE<=C; CNT<=0;
END IF;
WHEN D=>
IF CNT=4 THEN
CNT<=0; STATE<=A;
ELSE
CNT<=CNT+1;STATE<=D;
END IF;
END CASE;
END IF;
END PROCESS ;
RGY:PROCESS(STATE) IS
BEGIN
CASE STATE IS
WHEN A=>
MR<='0'; MY<='0'; MG<='1';
BR<='1'; BY<='0'; BG<='0';
WHEN B=>
MR<='0'; MY<='1'; MG<='0';
BR<='1'; BY<='0'; BG<='0';
WHEN C=>
MR<='1'; MY<='0'; MG<='0';
BR<='0'; BY<='0'; BG<='1';
WHEN D=>
MR<='1'; MY<='0'; MG<='0';
BR<='0'; BY<='1'; BG<='0';
END CASE;
END PROCESS RGY;
END ARCHITECTURE ART;
（二）编写45S定时单元CNT45S模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。
--45s定时模块源程序CNT45S.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY time_45s IS
PORT(SB,SM, CLK, EN45: IN STD_LOGIC;
DOUT45M, DOUT45B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY time_45s ;
ARCHITECTURE ART OF time_45s IS
SIGNAL CNT6B: STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(SB, SM, CLK, EN45) IS
BEGIN
IF(CLK'EVENT AND CLK= '1')THEN
IF SB='1' AND SM='1' THEN
IF EN45='1'THEN CNT6B<=CNT6B+1;
ELSE CNT6B<="000000";
END IF;
ELSE CNT6B<="000000";
END IF;
END IF;
END PROCESS;
PROCESS(CNT6B) IS
BEGIN
CASE CNT6B IS
WHEN "000000"=>DOUT45M<="01000101"; DOUT45B<="01010000"; --BCD数45, 50
WHEN "000001"=>DOUT45M<="01000100"; DOUT45B<="01001001"; --BCD数44, 49
WHEN "000010"=>DOUT45M<="01000011"; DOUT45B<="01001000"; --BCD数43, 48
WHEN "000011"=>DOUT45M<="01000010"; DOUT45B<="01000111"; --BCD数42, 48
WHEN "000100"=>DOUT45M<="01000001"; DOUT45B<="01000110"; --BCD数41, 50
WHEN "000101"=>DOUT45M<="01000000"; DOUT45B<="01000101"; --BCD数40, 49
WHEN "000110"=>DOUT45M<="00111001"; DOUT45B<="01000100"; --BCD数39, 48
WHEN "000111"=>DOUT45M<="00111000"; DOUT45B<="01000011"; --BCD数38, 48
WHEN "001000"=>DOUT45M<="00110111"; DOUT45B<="01000010"; --BCD数37, 50
WHEN "001001"=>DOUT45M<="00110110"; DOUT45B<="01000001"; --BCD数36, 49
WHEN "001010"=>DOUT45M<="00110101"; DOUT45B<="01000000"; --BCD数35, 48
WHEN "001011"=>DOUT45M<="00110100"; DOUT45B<="00111001"; --BCD数34, 48
WHEN "001100"=>DOUT45M<="00110011"; DOUT45B<="00111000"; --BCD数33, 50
WHEN "001101"=>DOUT45M<="00110010"; DOUT45B<="00110111"; --BCD数32, 49
WHEN "001110"=>DOUT45M<="00110001"; DOUT45B<="00110110"; --BCD数31, 48
WHEN "001111"=>DOUT45M<="00110000"; DOUT45B<="00110101"; --BCD数30, 48
WHEN "010000"=>DOUT45M<="00101001"; DOUT45B<="00110100"; --BCD数29, 50
WHEN "010001"=>DOUT45M<="00101000"; DOUT45B<="00110011"; --BCD数28, 49
WHEN "010010"=>DOUT45M<="00100111"; DOUT45B<="00110010"; --BCD数27, 48
WHEN "010011"=>DOUT45M<="00100110"; DOUT45B<="00110001"; --BCD数26, 48
WHEN "010100"=>DOUT45M<="00100101"; DOUT45B<="00110000"; --BCD数25, 50
WHEN "010101"=>DOUT45M<="00100100"; DOUT45B<="00101001"; --BCD数24, 49
WHEN "010110"=>DOUT45M<="00100011"; DOUT45B<="00101000"; --BCD数23, 48
WHEN "010111"=>DOUT45M<="00100010"; DOUT45B<="00100111"; --BCD数22, 48
WHEN "011000"=>DOUT45M<="00100001"; DOUT45B<="00100110"; --BCD数21, 50
WHEN "011001"=>DOUT45M<="00100000"; DOUT45B<="00100101"; --BCD数20, 49
WHEN "011010"=>DOUT45M<="00011001"; DOUT45B<="00100100"; --BCD数19, 48
WHEN "011011"=>DOUT45M<="00011000"; DOUT45B<="00100011"; --BCD数18, 48
WHEN "011100"=>DOUT45M<="00010111"; DOUT45B<="00100010"; --BCD数17, 50
WHEN "011101"=>DOUT45M<="00010110"; DOUT45B<="00100001"; --BCD数16, 49
WHEN "011110"=>DOUT45M<="00010101"; DOUT45B<="00100000"; --BCD数15, 48
WHEN "011111"=>DOUT45M<="00010100"; DOUT45B<="00011001"; --BCD数14, 48
WHEN "100000"=>DOUT45M<="00010011"; DOUT45B<="00011000"; --BCD数13, 50
WHEN "100001"=>DOUT45M<="00010010"; DOUT45B<="00010111"; --BCD数12, 49
WHEN "100010"=>DOUT45M<="00010001"; DOUT45B<="00010110"; --BCD数11, 48
WHEN "100011"=>DOUT45M<="00010000"; DOUT45B<="00010101"; --BCD数10, 48
WHEN "100100"=>DOUT45M<="00001001"; DOUT45B<="00010100"; --BCD数9, 50
WHEN "100101"=>DOUT45M<="00001000"; DOUT45B<="00010011"; --BCD数8, 49
WHEN "100110"=>DOUT45M<="00000111"; DOUT45B<="00010010"; --BCD数7, 48
WHEN "100111"=>DOUT45M<="00000110"; DOUT45B<="00010001"; --BCD数6, 48
WHEN "101000"=>DOUT45M<="00000101"; DOUT45B<="00010000"; --BCD数5, 50
WHEN "101001"=>DOUT45M<="00000100"; DOUT45B<="00001001"; --BCD数4, 49
WHEN "101010"=>DOUT45M<="00000011"; DOUT45B<="00001000"; --BCD数3, 48
WHEN "101011"=>DOUT45M<="00000010"; DOUT45B<="00000111"; --BCD数2, 07
WHEN "101100"=>DOUT45M<="00000001"; DOUT45B<="00000110"; --BCD数1, 06
WHEN OTHERS=>DOUT45M<="00000000"; DOUT45B<="00000000"; --BCD数00, 00
END CASE;
END PROCESS;
END ARCHITECTURE ART;
（三）编写25S定时单元CNT25S模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。
--25s定时模块源程序CNT25S.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY time_25s IS
PORT(SB, SM, CLK, EN25: IN STD_LOGIC;
DOUT25M, DOUT25B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY time_25s;
ARCHITECTURE ART OF time_25s IS
SIGNAL CNT_5Bit: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
PROCESS(SB, SM, CLK, EN25) IS
BEGIN
IF SB='0' OR SM='0' THEN
CNT_5Bit<="00000";
ELSIF(CLK'EVENT AND CLK= '1')THEN
IF EN25='1' THEN
CNT_5Bit<=CNT_5Bit+1;
ELSIF EN25='0'THEN
CNT_5Bit<="00000";
END IF;
END IF;
END PROCESS;
PROCESS(CNT_5Bit) IS
BEGIN
CASE CNT_5Bit IS
WHEN "00000"=>DOUT25B<="00100101"; DOUT25M<="00110000"; --BCD数25, 50
WHEN "00001"=>DOUT25B<="00100100"; DOUT25M<="00101001"; --BCD数24, 49
WHEN "00010"=>DOUT25B<="00100011"; DOUT25M<="00101000"; --BCD数23, 48
WHEN "00011"=>DOUT25B<="00100010"; DOUT25M<="00100111"; --BCD数22, 48
WHEN "00100"=>DOUT25B<="00100001"; DOUT25M<="00100110"; --BCD数21, 50
WHEN "00101"=>DOUT25B<="00100000"; DOUT25M<="00100101"; --BCD数20, 49
WHEN "00110"=>DOUT25B<="00011001"; DOUT25M<="00100100"; --BCD数19, 48
WHEN "00111"=>DOUT25B<="00011000"; DOUT25M<="00100011"; --BCD数18, 48
WHEN "01000"=>DOUT25B<="00010111"; DOUT25M<="00100010"; --BCD数17, 50
WHEN "01001"=>DOUT25B<="00010110"; DOUT25M<="00100001"; --BCD数16, 49
WHEN "01010"=>DOUT25B<="00010101"; DOUT25M<="00100000"; --BCD数15, 48
WHEN "01011"=>DOUT25B<="00010100"; DOUT25M<="00011001"; --BCD数14, 48
WHEN "01100"=>DOUT25B<="00010011"; DOUT25M<="00011000"; --BCD数13, 50
WHEN "01101"=>DOUT25B<="00010010"; DOUT25M<="00010111"; --BCD数12, 49
WHEN "01110"=>DOUT25B<="00010001"; DOUT25M<="00010110"; --BCD数11, 48
WHEN "01111"=>DOUT25B<="00010000"; DOUT25M<="00010101"; --BCD数10, 48
WHEN "10000"=>DOUT25B<="00001001"; DOUT25M<="00010100"; --BCD数9, 50
WHEN "10001"=>DOUT25B<="00001000"; DOUT25M<="00010011"; --BCD数8, 49
WHEN "10010"=>DOUT25B<="00000111"; DOUT25M<="00010010"; --BCD数7, 48
WHEN "10011"=>DOUT25B<="00000110"; DOUT25M<="00010001"; --BCD数6, 48
WHEN "10100"=>DOUT25B<="00000101"; DOUT25M<="00010000"; --BCD数5, 50
WHEN "10101"=>DOUT25B<="00000100"; DOUT25M<="00001001"; --BCD数4, 49
WHEN "10110"=>DOUT25B<="00000011"; DOUT25M<="00001000"; --BCD数3, 48
WHEN "10111"=>DOUT25B<="00000010"; DOUT25M<="00000111"; --BCD数2, 07
WHEN "11000"=>DOUT25B<="00000001"; DOUT25M<="00000110"; --BCD数1, 06
WHEN OTHERS =>DOUT25B<="00000000"; DOUT25M<="00000000"; --BCD数00, 00
END CASE;
END PROCESS;
END ARCHITECTURE ART;
（四）编写5S定时单元CNT05S模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。
--5s定时模块源程序CNT05S.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY time_5s IS
PORT(CLK, EN05M, EN05B: IN STD_LOGIC;
DOUT5: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY time_5s;
ARCHITECTURE ART OF time_5s IS
SIGNAL CNT_3Bit: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(CLK, EN05M, EN05B) IS
BEGIN
IF(CLK'EVENT AND CLK= '1')THEN
IF EN05M='1' OR EN05B='1' THEN
CNT_3Bit<=CNT_3Bit+1;
ELSE
CNT_3Bit<="000";
END IF;
END IF;
END PROCESS;
PROCESS(CNT_3Bit) IS
BEGIN
CASE CNT_3Bit IS
WHEN "000" =>DOUT5<="00000101"; --BCD数05
WHEN "001" =>DOUT5<="00000100"; --BCD数04
WHEN "010" =>DOUT5<="00000011"; --BCD数03
WHEN "011" =>DOUT5<="00000010"; --BCD数02
WHEN "100" =>DOUT5<="00000001"; --BCD数01
WHEN OTHERS=>DOUT5<="00000000"; --BCD数00
END CASE;
END PROCESS;
END ARCHITECTURE ART;
（五）编写显示控制单元XSKZ模块的VHDL程序，并对其进行编译和仿真，初步验证设计的正确性。
--显示控制模块源程序XSKZ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XSKZ IS
PORT(EN45, EN25, EN05M, EN05B:IN STD_LOGIC;
AIN45M, AIN45B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
AIN25M, AIN25B, AIN05: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dec_m, dec_b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY XSKZ;
ARCHITECTURE ART OF XSKZ IS
BEGIN
PROCESS(EN45,EN25,EN05M, EN05B,AIN45M,AIN45B,AIN05,AIN25M,AIN25B) IS
BEGIN
IF EN45='1' THEN
dec_m<=AIN45M(7 DOWNTO 0); dec_b<=AIN45B(7 DOWNTO 0);
ELSIF EN05M='1' THEN
dec_m<=AIN05(7 DOWNTO 0); dec_b<=AIN05(7 DOWNTO 0);
ELSIF EN25='1' THEN
dec_m<=AIN25M(7 DOWNTO 0); dec_b<=AIN25B(7 DOWNTO 0);
--ELSIF EN05B='1' THEN
ELSE
dec_m<=AIN05(7 DOWNTO 0); dec_b<=AIN05(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE ART;
（六）数码管动态扫描显示电路设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY disp_scan IS
PORT(CLK_scan: IN STD_LOGIC;
DEC_M: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DEC_B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG7: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY disp_scan;
ARCHITECTURE ART OF disp_scan IS
signal temp: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal CNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
PROCESS(CLK_scan) IS
BEGIN
IF CLK_scan'EVENT AND CLK_scan='1' THEN
IF CNT="111" THEN
CNT<="000";
ELSE
CNT<=CNT+'1';
END IF;
END IF;
END PROCESS;
LEDW<=CNT;
PROCESS(CNT,TEMP,DEC_B,DEC_M) IS
BEGIN
CASE CNT IS
WHEN "000" => TEMP<=DEC_M(7 DOWNTO 4);
WHEN "001" => TEMP<=DEC_M(3 DOWNTO 0);
WHEN "110" => TEMP<=DEC_B(7 DOWNTO 4);
WHEN "111" => TEMP<=DEC_B(3 DOWNTO 0);
WHEN OTHERS=> TEMP<="1111";
END CASE;
CASE TEMP IS
WHEN "0000"=> SEG7<="00111111";
WHEN "0001"=> SEG7<="00000110";
WHEN "0010"=> SEG7<="01011011";
WHEN "0011"=> SEG7<="01001111";
WHEN "0100"=> SEG7<="01100110";
WHEN "0101"=> SEG7<="01101101";
WHEN "0110"=> SEG7<="01111101";
WHEN "0111"=> SEG7<="00000111";
WHEN "1000"=> SEG7<="01111111";
WHEN "1001"=> SEG7<="01101111";
WHEN OTHERS=> SEG7<="00000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART;
（七）利用前面所设计的模块，完成交通灯信号控制器的顶层设计，并对其进行编译和仿真，初步验证设计的正确性。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY traffic IS
PORT(SB,SM, CLK, clk_scan: IN STD_LOGIC;
MR1,MY1,MG1,BR1,BY1,BG1:BUFFER STD_LOGIC;
--MR2,MY2,MG2,BR2,BY2,BG2:OUT STD_LOGIC;
ledw:out STD_LOGIC_VECTOR(2 DOWNTO 0);
seg7: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY traffic ;
ARCHITECTURE ART OF traffic IS
COMPONENT JTDKZ IS
PORT(CLK, SM, SB: IN STD_LOGIC;
MR, MY, MG, BR, BY, BG: OUT STD_LOGIC);
END COMPONENT JTDKZ;
COMPONENT time_45s IS
PORT(SB,SM, CLK, EN45: IN STD_LOGIC;
DOUT45M, DOUT45B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT time_45s ;
COMPONENT time_25s IS
PORT(SB, SM, CLK, EN25: IN STD_LOGIC;
DOUT25M, DOUT25B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT time_25s;
COMPONENT time_5s IS
PORT(CLK, EN05M, EN05B: IN STD_LOGIC;
DOUT5: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT time_5s;
COMPONENT XSKZ IS
PORT(EN45, EN25, EN05M, EN05B:IN STD_LOGIC;
AIN45M, AIN45B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
AIN25M, AIN25B, AIN05: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dec_m, dec_b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT XSKZ;
COMPONENT disp_scan IS
PORT(CLK_scan: IN STD_LOGIC;
DEC_M: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DEC_B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG7: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT disp_scan;
SIGNAL DATA_45M: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATA_45B: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATA_25M :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATA_25B :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATA_05 :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DEC_M :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DEC_B :STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
U0:JTDKZ PORT MAP(CLK,SM,SB,MR1,MY1,MG1,BR1,BY1,BG1);
U1:time_45s PORT MAP(SB,SM,CLK,MG1,DATA_45M,DATA_45B);
U2:time_25s PORT MAP(SB,SM,CLK,BG1,DATA_25M,DATA_25B);
U3:time_5s PORT MAP(CLK,MY1,BY1,DATA_05);
U4:XSKZ PORT MAP(MG1,BG1,MY1,BY1,DATA_45M,DATA_45B,DATA_25M,DATA_25B,DATA_05,DEC_M,DEC_B );
U5:disp_scan PORT MAP(clk_scan,DEC_M,DEC_B,ledw,seg7);
END ARCHITECTURE ART;
（八）逻辑综合结果
使用Quartus Ⅱ进行逻辑综合，给出电路的 RTL视图及逻辑综合后的资源使用情况。
（九）管脚锁定及硬件验证情况
按如下要求进行引脚锁定：
set_location_assignment PIN_78 -to CLK
set_location_assignment PIN_79 -to CLK_SCAN
set_location_assignment PIN_53 -to LEDW[2]
set_location_assignment PIN_47 -to LEDW[1]
set_location_assignment PIN_46 -to LEDW[0]
set_location_assignment PIN_163 -to SB
set_location_assignment PIN_160 -to SM
set_location_assignment PIN_36 -to BG1
set_location_assignment PIN_38 -to BR1
set_location_assignment PIN_37 -to BY1
set_location_assignment PIN_39 -to MG1
set_location_assignment PIN_41 -to MR1
set_location_assignment PIN_40 -to MY1
set_location_assignment PIN_132 -to SEG7[7]
set_location_assignment PIN_131 -to SEG7[6]
set_location_assignment PIN_128 -to SEG7[5]
set_location_assignment PIN_127 -to SEG7[4]
set_location_assignment PIN_126 -to SEG7[3]
set_location_assignment PIN_125 -to SEG7[2]
set_location_assignment PIN_122 -to SEG7[1]
set_location_assignment PIN_121 -to SEG7[0]
将CLK0设置为1HZ；CLK1设置为1KHZ，拨动开关K0，K1，观察红绿灯及倒计时显示情况，验证是否满足预期功能。
四、实验设计
1、系统设计
设计并调试好一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器。
2、VHDL程序
3、仿真波形
traffic
Time 5s
Time 25s
Time45s
Xskz
Jtdkz
Scan
图4.3
4、芯片引脚锁定文件
图4.4
五、实验结果及
总结
初级经济法重点总结下载党员个人总结TXt高中句型全总结.doc高中句型全总结.doc理论力学知识点总结pdf
1、系统仿真情况
如图4.3
2、逻辑综合结果
如4.4
3、硬件验证情况
4、实验过程出现的问
题
快递公司问题件快递公司问题件货款处理关于圆的周长面积重点题型关于解方程组的题及答案关于南海问题
及解决方法
实验未发现问题。
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