IMX6硬件设计指南与硬件启动

i.MXHWDesignGuideandBoardBringUpFAE:LindaLinConsolidatedbyi.MXFAE(Draftver0.2)Aug.6,2014Topics1.i.MX6HWDesignReferenceBoard.(gothroughschematicofi.MX6SDP)2.i.MX6HardwareDevelopmentGuide.(IMX6DQ6SDLHDG.pdf)3.i.MXHWCheckingList.(Exceli.MX6HWDesignCheckingList)4.i.MX6XPowerdesign5.DDRCalibrationandStressTest.6.IOMuxTool7.i.MX6XHardwarebringupi.MX6HWDesignReferenceBoard.RelatedHardwarematerialsSABRESDP_DESIGN:SDP/AIboardschematic/layout.IMX6DQ6SDLHDG.pdf:i.MX6Xhardwaredesignguide,includeschematic/layoutcheckpoints,iomuxtools,bringup,IBIS/BSDL,RMIIinterface.IMX6DQ/DLS_A/I/CEC.pdf:i.MX6XDatasheet:includechipsetelectricalCharacteristicslikethevoltagerange,MaxcurrentandPowersequence.IMX6DQ/DLS_RM.pdf:i.MX6XChipsetreferencemanual.AN4509:i.MX6DQPowerConsumptionMeasurement.AN4576:i.MX6DLSPowerConsumptionMeasurement.IMX6_IOMUX_TOOL:iomuxconfigurationtools.Mfgtools-Rel-4.1.0_130816_MX6Q_UPDATER.tar.gz:MFGtools.L3.0.35_4.1.0_130816_images_MX6.tar.gz:linuxdemoimage.HWDesignCheckingListfori.Mx6Rev2.6.xlsx:i.MX6Xhardwarechecklist,downloadfrom:DDR_Stress_Tester_v1.0.3.zip:DDRtesttools,downloadfrom:i.Mx6DQSDLDDR3ScriptAid:DDRconfigurationtools,Downloadfrom:Freescalei.MX6DRAMPortApplicationGuide-DDR3i.MX6ReferenceSolutionRelatedMaterialSelect“SABREPlatformforSmartDevices”HardwareMaterial(Schematic,PCB,Gerber.etc);SABREBoardforSmartDevices(SDB)i.MX6Quad1GhzCortex-A9ProcessorCanbeconfiguredasi.MX6DualFreescaleMMPF0100PMIC1GBDDR3memory(nonterminated)3”x7”8-layerPCBDisplayconnectors2xLVDSconnectorsConnectorfor24bit4.3”800x480WVGAwith4-wiretouchscreenHDMIConnectorAudioWolfsonAudioCodecMicrophoneandheadphonejacksExpansionConnectorCameraCSIportsignalsI2C,SSI,SPIsignalsConnectivity2xFull-sizeSD/MMCcardslot22-pinSATAconnector10/100/1000Ethernetport1xhigh-speedUSBOTGportmPCI-econnectorDebugJTAGconnectorSerialtoUSBconnectorAdditionalFeatures3-axisFreescaleacceleCompassPowersupplyNobatterychargerOSSupportLinuxandAndroidJBfromFreescale;Others:supportby3rdpartiesToolsSupportLauterbach,ARM(DS-5),Macraigordebug/IDEtoolchainPartNumbers:MCIMX6Q-SDB($399)Display(9.7”):MCIMX-LVDS1($499)Display(4.3”):MCIMX28LCD($199)SABREPlatformforSmartDevices(SDP)i.MX6Quad1GHzCortex-A9Processori.MX6DualLite1GHzCortex-A9ProcessorFreescaleMMPF0100PMIC1GBDDR3memory(nonterminated)3”x7”8-layerPCBDisplayconnectorsNative1024x768LVDSdisplay(comeswithkit)2ndLVDSconnectorConnectorfor24bit4.3”800x480WVGAwith4-wiretouchscreenHDMIConnectorMIPIDSIconnectorAudioWolfsonAudioCodecMicrophoneandheadphonejacksDual1WSpeakersExpansionConnectorEnablesparallelLCDorHDMIoutputCameraCSIportsignalsI2C,SSI,SPIsignalsConnectivity2xFull-sizeSD/MMCcardslot22-pinSATAconnector10/100/1000Ethernetport1xhigh-speedUSBOTGportmPCI-econnectorDebugJTAGconnectorSerialtoUSBconnectorAdditionalFeatures3-axisFreescaleaccelGPSreceiverAmbientLightSensoreCompassDual5MPCamerasPowersupplyBatteryChargerBatteryconnectorsOSSupportLinuxandAndroidJBfromFreescale;Others:supportby3rdpartiesToolsSupportLauterbach,ARM(DS-5),Macraigordebug/IDEtoolchainPartNumbers:MCIMX6Q-SDP($999)MCIMX6DL-SDP($999)Display(4.3”):MCIMX28LCD($199)WiFi:SilexWiFimoduleSABREPlatformforAutomotiveInfotainment(AI)PowerandMemoryFreescaleMMPF0100PMIC2GBDDR3memory(i.MX6Dual/Quad)1GBDDR3memory(i.MX6Solo)32GBParallelNORFlashNANDSocketDisplayLVDSconnectorcompatiblewithMCIMX-LVDS1ParallelRGBdisplayinterfaceHDMIoutputconnectorDebugJTAGconnectorDebugUARTconnectorConnectivityandExpansionSDCardSlotHighSpeedUSBOTGEthernetSATAMIPICSIPCIeMLB150INICconnector281-pinMXMcardedgeconnectorformainboardexpansionCanbereusedfromi.MX53SABREAIConnectivityandExpansionSDcardslot(WiFimoduleorSD)BluetoothorBluetooth+WiFiheaderAM/FMtunerheaderSiriusXMModuleheader(de-pop’’d)GPS(UART)moduleconnector2xCANDualHighSpeedUSBHostconnectorsMLB25/50INICconnectorSPINORflashDisplayI/OLVDSconnectorcompatiblewithMCIMX-LVDS1AnalogVideoInputLVDSInputAudioCirrusmultichannelaudiocodecUpto8outputsDualmicrophoneinputsStereoLineLevelInputSPDIFreceiverOSSupportLinuxOthers:futuresupportby3rdpartiesCPUCardDetailsBaseBoardDetailsPartNumbersBaseBoard:MCIMXABASEV1($699)CPUCards:MCIMX6SAICPU1($799)MCIMX6QAICPU1($799)Display:MCIMX-LVDS1($499)i.MX6SMARTDEVICESYSTEMBlockDiagrami.MX6SMARTDEVICESYSTEMSchematicHere,openi.MX6SabreSDSchematic,gothroughit.i.MX6HardwareDevelopmentGuide.Suggestion:Pre-design:Studythedatasheet,powerconsumption,schematictounderstandourchipsetrequirement.In-design:Checkthehardwaredesignguide,iomuxtoolsAfter-design:FilltheHWdesigncheckinglist,providetheiomuxdatatosoftware.Hardware-bringup:Checkthepower,powersequence,clock,reset,providethebootconfigurationtosoftware,runddrtest.Debugport:SuggesttohaveUSBOTGPort:Forimageprogram,YoucanuseitasUSBhostport,noproblem.MFGjustuseUSBdevicemode.Debugserialport,i.MX6Xubootcanchangetosupporteveryserialportasdebugport.Sdcardslot:SuggesttokeepatleastoneSdcardslot,itwillhelptousetheSdcardboot,whichcanburnimagedirectlyfromPCtoSdcard.NoneedtodebugtheMFGkernel.Jtag(optional).SuggesttousetheGPIOBoot_cfgbutnotthefuseBoot_cfg.Andbootmodepincanbepulled,becausewecanusethenon-imageboottoenterthedownloadmodei.MX6HardwareDevelopmentGuideHere,open<>,gothroughit.1).DesignChecklist2).i.MX6SeriesLayoutRecommendations3).RequirementsforPowerManagement4).AvoidingBoardBring-upProblemsi.MXHWCheckingList.i.MXHWCheckingListHere,open<>,gothroughit.Clear1Isvoltagelevelmatchedonbus/signal/logic/buffertwoside?Clear2Suggestdrawingpull-upsnearpinareawithpowerdomaindescriptioninschematic.Clear3Pleasetakecareclocksourcecanmeetrequirementofperipheraldevices.(frequency/drivingcapability/jitter/tolorance/fly-timeetc.)Clear4WhenBuffer/Levelshifter/switchareused,SIimpactiononsignalshouldbeconsidered.Clear5ThecontrolsignalspolarityforDirectionSellect/EN/RESETshouldbecheckedforallthedevices.Clear6IOconfigurationshouldbecheckedusingIOMUXToolwhichprovidedbyFreescale.Clear7TheTESTandFAULTmodeinputsoftheindividualchipsshouldbetiedtotheproperlevelfornormaloperation.Clear8Pinsequence/direction/gendersofconnectorshouldbeconfirmedwithMechnicalconsideration.Clear9Pull-upsandvoltagesshouldbeverifiedforOC/ODsignals.Clear10Properpull-upandpull-downresistorvaluesprovidedtoavoidexcesssourcingorsinkingcurrent.Clear11Thepolaritiesofthecapsanddiodesconnectedto–vevoltagesshouldbeverified.Clear12Suggestallactivelowsignals--include“_B”atendofthesignalnetnameandallclocksignalsinclude“CLK”aspartofnetname.Clear13Pleaseconfirmifallpowersourcehavesufficientpowercapacityandgoodenoughripplenoiselevelforrequirementofpowerinput.Clear14Poweron/offsequencingshouldbeverifiedwhenmultiplepowersourcesareused.Clear15ThecurrentratingofDiodes/Inductorsusedinthepowersupplyandotherhighcurrentsectionsshouldbeprovidedproperly.Clear16PleasepayattentiononEMI/EMC/ESD/Ligteningconsideration(decouplingcaps/TVSdiodes/chokes/filters/beads/fueseetc).Clear17Pleaseconfirmifunusedpinsareconfiguredproperlyfollowingformalrecommend.Clear18Pleaseconfirmbootmodeandconfigurationpinsaresetproperlyandcanmeettheactualbootrequirment.Clear19Pleasetakecarewatchdog/cold/keyresetsystemdesign,PMICandbootdevicealsoshouldberesetatsametime.i.MX6XPowerdesigni.MX6PowerRelateddocIMX6DQCEC.pdf:i.MX6Dual/6QuadApplicationsProcessorsforConsumerProductsAN4509.pdf:i.MX6Dual/6QuadPowerConsumptionMeasurementIMX6SDLCEC.pdf:i.MX6Solo/6DualLiteApplicationsProcessorsforConsumerProductsAN4576.pdf:i.MX6DualLitePowerConsumptionMeasurementSDPschematic(PF0100):SPF-27392.pdfSaberliteschematic(DiscreteDCDC)(fromboundarydevices)IMX6DQ6SDLHDG.pdf(optional):DesignChecklist:Table2-6.PoweranddecouplerecommendationsPowerSupply,andCommonHardwareDesigni.MX6System-PowerDesignConsiderationsSystemPowerRequirements(oneachpowerrail)MaxCurrentrequirementVoltagerangeSystemOver-VoltageProtectionPowerOnSequencingSystemcontrolfunctionsLayout&decouplei.MX6PowerRailRequirementsToFunctionproperly,thei.MX6Processorrequiresninedifferentpowerrails(Somemaybecombined)VDDARMPowertoARMCoresAllowedvoltage:0.9V–1.5VVDDSOCVPPowertoonchipSystemPeripherals(VDDSOC_CAP):HDMIPHY,SATAPHY,PCIEPHY,&ARMCoreCachePowertoImageprocessingmodules(VDDPU_CAP)VPU,GPU2D,GPU3D,OpenVGAllowedvoltage:0.9V–1.5Vi.MX6PowerRailRequirements(con)VDDHIGHVPHPowertoonchipSystemPeripherals(VDDHIGH_CAP)MIPI,HDMI,SATA,PCIE,LVDS,USB,PLLsPowertomiscPeripherals(NVCC_PLL_OUT)USD,PLLs,24MHzOsc.SharedpowerofSNVSmoduleAllowedvoltage:2.7V–3.3VVSNVS32KHzOscillatorandSRTCfunctionsSharedpowerofSNVSmoduleAllowedvoltage:2.8V–3.3Vi.MX6PowerRailRequirements(con)USB_H1/OTG_VBUSPowertoUSBPHYAllowedvoltage:4.4V–5.25VNVCC_DRAMPowersupplyforDRAMmemoryAllowedvoltage:1.14V–1.575V(DependsontypeDRAM)EthernetIOpins(NVCC_RGMII)Allowedvoltage:1.14–1.9VGeneralIOpins(NVCC_)Typically1.8Vor3.3VAllowedvoltage:1.65V–3.6Vi.MX6PowerRailRequirements-SummaryInatypicalapplication,sixdifferentvoltagesarerequiredfortheprocessortofunction:FunctionTypicalVoltageVDDARM,VDDSOC1.375VVDDHIGH,VSNVS3.0VUSB_VBUS5.0VNVCC_DRAM1.5VNVCC_3.3V3.3VNVCC_1.8V1.8Vi.MX6PowerRequirements–VDDARM,VDDSOCDatasheetMaxRequirementsforVDDARM:3920mADatasheetMaxRequirementsforVDDSOC:1890mATypicalMaximumCurrentRequirements(AN4509):Showingthreeseparatevideooutputs1080pVideoplaybackHDMI1080pVideoplaybackIPUParallelport(LCD)3DgraphicsthroughLVDSportVDDARM:1625mAVDDSOC:1250mAi.MX6PowerRequirements–VDDHIGH,VSNVSDatasheetMaxRequirementsforVSNVS:300uAPullUpresistorsonVSNVSwilladdtocurrentrequirementsDatasheetMaxRequirementsforVDDHIGH:160mATypicalMaximumCurrentRequirements(AN4509):VDDHIGH:85mAi.MX6PowerRequirements–DRAM,IOPinsDatasheetMaxRequirementsforDRAM:1900mATypicalMaximumCurrentRequirements(AN4509):DRAM:1390mADatasheetrequirementsforIOPins,use:I(A)=NxCxVx(0.5xF)N–NumberofIOpinssuppliedC–Equivalentexternalcapacitiveload(Farads)V–IOvoltage(Volts)(0.5xF)–Datachangerate,whereF=Frequency(Hz)Typical=2-3mAfora3.3VpinSummaryPowerRequirements*MaximumvaluesaremutuallyexclusivePowerRailVoltageTypicalMaximumVDDARM1.375V1625mA3920mAVDDSOC1.375V1250mA1890mAVDDHIGH2.8V85mA160mAVSNVS3.0V-300uADRAM1.5V1390mA1900mAUSB5.0V500mA530mAI/OPins3.3V300mA500mA*I/OPins1.8V50mA275mA*TypicalConsumerDevicePowerRequirementsFunctionVoltageTypicalMaximumSDCard3.3V100mAWIFI/BT3.3V1000mA3G/4GModem3.3V2000mA3000mALVDS3.3/5V300/370mAHDMI5V50mAEthernet3.3V130mAAudio1.8/5V40/100mA80/530mASATA5V500-1000mA1500mAeMMC3.3V100mA200mACAN5V70mAGPS1.5/3.3V20/100mACamera1.5/1.8V150/20mAGrandTotalPowerRequirementsVoltageTypicalFullPower1.375V1875mA5800mA1.5V1500mA2300mA1.8V100mA350mA3.0V160mA200mA3.3V2000mA5000mA5.0V1500mA3300mAi.MX6System-PowerDesignConsiderationsTotalSystemPowerRequirementsTypicalSystemrequirements(5Vsource):2.9ATypicalSystemrequirements(3.7Vsource):4.1ASystemOver-VoltageProtectionSelectPowercomponentswithhighvoltagetoleranceDesignOver-Voltageprotectionsub-systemUserbatterychargingcircuitwithprotection.PowerOnSequencingSystemcontrolfunctionsStand-by,reducedpoweroptionsi.MX6System-PowerOn/OffSequencingPowerOnSequencingVDD_SNVS_IN= 表 关于同志近三年现实表现材料材料类招标技术评分表图表与交易pdf视力表打印pdf用图表说话 pdf ，示波器i.MX6XHardwarebringup:Step1　目视检查检查主要器件是否有错贴的情况，比如说二极管，三极管，有没有安装位置反向或旋转的问题。可以在PCBA时使用X光检查，有条件的使用BSDL检查来确认焊接与连线i.MX6XHardwarebringup:Step2　电源检查使用万用表，先空板检查每个电源有没有对地短路的情况。使用限流电源上电，检查i.MX6X每路电源的电压是否符合我们datasheet要求，量测电压是要求在电源输出端和i.MX6X电源输入端(越近越好，如在滤波电容上量测)都量测一下，以避免IR跌落。VDD_ARM/SOC_IN供给i.MX6X内部逻辑电路，需要仔细检查，VDD_SNVS_IN，NVCC_JTAG,NVCC_DRAM也对正常启动很重要，NVCC_LVDS2V5也供给了DDRI/OPads,也必须要正常供给。i.MX6X在各路电源稳定后，才能释放reset(POR_B)。如前电源上电时序要求，检查上电时序。i.MX6XHardwarebringup:Step3　时钟检查一般在电源电压正确，无跌落，24Mhz和32K晶体会自动起振。可使用示波器量测这两个时钟，如果24Mhz不工作，则系统不能启动，如果外部没有32K，或32K不工作，则i.MX6X会自动使用内部晶振，但根据newerrataIM6DQCERev.4,07/2014:ERR007926ROM:32kHzinternaloscillatortiminginaccuracymayaffectSD/MMC,NAND,andOneNANDboot,由于内部romcode的GPT使用这个时钟，而GPT被用于外设访问中一些event和timeout控制，所以不稳定的时钟有可能导致romcodes读取外设失败，所以建议连接外部32K.i.MX6XHardwarebringup:Step4　准备bringup文档一般硬件 工程 路基工程安全技术交底工程项目施工成本控制工程量增项单年度零星工程技术标正投影法基本原理 师需要准备三份文档描述板级 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 电源文档:每一路电源的源，供给到?输出，输入电压，测量点,时序。如SDPschematic:i.MX6XHardwarebringup:Step4　准备bringup文档IOMUX文档：可以使用iomux工具导出，也可以手动准备,内容最好包括：以方便软件工程师配置IOMUX，这个表应该至少包括所有数字管脚,软件工程师根据这个表来配置iomux文件:arch\arm\mach-mx6\Board-mx6q_sabersd.hstaticiomux_v3_cfg_tmx6q_sabresd_pads[]={…/*UART1fordebug*/MX6Q_PAD_CSI0_DAT10__UART1_TXD,//CSI0_DAT10为管脚名，UART1_TX会功能名。Notes:1i.MX6X基本所有的可做为GPIO的pin在reset状态下都是iomux设为gpio,gpio设为输入高阻，iopad设为100K上拉的.2i.MX6X的datasheet中也列出了一些例外:Formostofthesignals,thestateduringresetissameasthestateafterreset,However,therearefewsignalsforwhichthestateduringresetisdifferentfromthestateafterreset:EIM_A16~A25,EIM_DA0~DA15,EIM_EB1~EB3,EIM_LBA/RW/WAIT,GPIO_17/19,KEY_COL0，请注意有一些pin是用于bootgpio的.管脚名脚管序号网络名IOMUX用于CSI0_DATA10M1UART1_TXALT3UART1_TXi.MX6XHardwarebringup:Step4　准备bringup文档Boot_Cfg文档：说明Boot_cfg配置，以SDP的eMMCboot为例FuseSBMR1定义GPIO管脚默认值设置值　默认值定义　BOOT_CFG1[7:6]Bit7_6启动设备接口EIM_DA7_6000101:BootfromUSDHCBOOT_CFG1[5]bit5SD/MMCSelEIM_DA5010:SD/eSD/SDXC;1:MMC/eMMCBOOT_CFG1[4]bit4FastBootSuppoEIM_DA4000:NormalBoot;1:FastBootBOOT_CFG1[3:2]bit3_2SD/MMC速度模式　EIM_DA3_20000MMC:0x:HighSpeedMode;1x:NormalSpeedModeSD:0x:High/Normal;10:SDR50;11:SDR104BOOT_CFG1[1]bit1SDPowerCycleeMMCResetEIM_DA100MMC:0:eMMCresetdisabled.1:eMMCresetenabledviaSD_RSTpad(onUSDHC3/4)SD:0:Nopowercycle1:PowercycleenabledvisSD_RSTpad(onUSDHC3/4)BOOT_CFG1[0]bit0SDLoopbackClockSourceSel(SDR50/104only)EIM_DA0000:throughSDpad1:directBOOT_CFG2[7:5]bit15_13BusWidth/SDCalibrationStepEIM_DA15~13000010SD:BusWidth:xx0:1bit;xx1:4bit.SDCalibrationStep:00x~11x:1~3delaycellsMMC000~010:1,4,8bit.101~110:4,8bitDDR(MMC4.4)i.MX6XHardwarebringup:Step4　准备bringup文档SDP的BootSelect为:所以eMMC启动的SBMR1=0Xxxx5860FuseSBMR1定义GPIO管脚默认值设置值　默认值定义　BOOT_CFG2[4:3]Bit12_11启动设备接口EIM_DA12_11001100~11:USDHC1~4BOOT_CFG2[2]Bit10DLLOverride(eMMC)EIM_DA10000:BootROMdefault;1:ApplyvalueperfuseMMC_DLL_DLY[6:0]BOOT_CFG2[1]Bit9BootACKdisable/PulldownDuringPowerCycleEnableEIM_DA900MMC:0:BootACKEnabled;1:BootACKDisabled.SD:0:UsethedefaultSDpadsettingsduringpowercycle.1:SetPulldownonSDpadsduringpowercycleBOOT_CFG2[0]bit8OverridePadSettingsEIM_DA8000:Usethedefaultvalues.1:UsePAD_SETTINGSvalues.i.MX6XHardwarebringup:Step5　确认启动配置　i.MX6X在上电正确，时钟正确，POR正确后，会首先执行内部的ROMcodes，这个ROMcodes,首先会读取SBMR2寄存器的值，来判断启动模式，如果为下载模式，则进入下载模式。　如果为正常启动模式则会根据读取SBMR1寄存器的值来初始化相应启动设备的控制器，并尝试去读取相应设备上的镜像，并认证。如果认证成功，则根据镜像开头的数据结构来初始化外部DDR，然后将镜像拷贝到外存，并跳转到外存执行bootloader。如果镜像认证失败，则又进入下载模式。　进入下载模式后，i.MX6X会通过USBOTG口与hostPC联系，并 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为一个HID设备。所以从PC上可以看到一个USBHID设备信息。如果有这个信息报出，证明i.MX6X的最小系统工作了(电源，时钟，POR，内部ROMcodes已经执行并进入了下载模式)。如果我们已经设置为正常启动模式，并且配置boot_cfg相应的GPIO，则可以使用示波器量测启动设备上相应的时钟：Nand:CEpinforreadenableclockSPI-NOR:SlaveSelectorClockpin.MMC/SD:SD_CLKpin.如果有时钟，则说明ROMcodes已经开始读取相应启动设备，硬件Boot_cfgGPIO配置是正确的。如果没有，则说明Boot_cfgGPIO配置可能有问题，需要再次检查硬件。i.MX6XHardwarebringup:Step6　测试外部内存　　i.MX6X最小系统工作以后，下一步需要保证外部内存已经工作了，这样才可以确保bootloader软件可以工作。所以接下来需要测试外部DDR.根据DDRdatasheet,使用Mx6DQSDLDDR3ScriptAid工具来生成DDR初始化脚本。连接硬件，运行DDR_Stress_Tester.exe–tmx6x–dfMX6QD_SabreSD_DDR3_528MHz_64bit.inc，根据提示来校准DDR及进行压力测试。如果压力测试通过，则说明外部DDR工作正常。DDR测试详细请参看文档MX6X_DDR3_调校_应用手册_V1.docDDR初始化脚本可作为bootloader中的DDR初始化数据结构用,在文件:uboot\board\freescale\mx6q_sabersd\flash_header.s使用\u-boot-2009.08\include\configs\mx6q_sabresd_iram.h可以编译出基于内部iRam运行的uboot,对比运行在外部DDR的uboot可以判断是否为外部DDR问题。i.MX6XHardwarebringup:完成以上步骤完成后，则可以初步说明i.MX6X系统(i.MX6X，电源，外部DDR)工作正常。可以进行接下来的软件bringup工作。软件定制基本包括:根据DDR初始化脚本来配置uboot的flash_header数据结构。根据IOMUX文档来配置uboot和内核的iomux数组。根据板级的外设情况来准备一个相对较小的内核，并编译出MFG和正常内核。使用MFG烧写启动设备，调试MFG内核。烧写成功后，启动，如果有uboot串口消息打出，则可以使用串口消息来继续调试。i.MX6XHardwarebringup:一些调试 方法 快递客服问题件处理详细方法山木方法pdf计算方法pdf华与华方法下载八字理论方法下载 １:确认启动配置刚才说到可以通过量测启动设备相应的管脚clock信号来判断Boot_cfg设置是否正确，而如果MFG及MFG镜像可以工作，也可以使用MFG直接读取SBMR1寄存器来获取：将MFG的uboot换成正常启动的uboot，即替换掉\Mfgtools-Rel-4.1.0_130816_MX6Q_UPDATER\Profiles\MX6QLinuxUpdate\OSFirmware\u-boot-mx6q-sabresd.bin(MFG的uboot和正常启动的uboot对比一个不同就是MFG的uboot取消了等待3S输入的功能，而正常的uboot可以)启动板子，进入下载模式(bootmode为下载，或是启动镜像认证失败都会进入)。进入下载模式后就可以运行MFG，将正常启动的uboot镜像下载到外部内存并运行起来。在串口上键入“空格”，停下uboot,然后使用uboot的”md”命令就可以读取sbmr1寄存器：”md020d8004”(sbmr1寄存器地址)，在SDP,eMMC启动时为0x00005860，与上文我们配置的一致。所以总结下来如果系统因为启动模式不对而进入到下载模式，我们可以通过MFG来精确确认SBMR1寄存器值，从而了解是那些Boot_CfgGPIO配置不对。此课件下载可自行编辑修改，供参考！部分内容来源于网络，如有侵权请与我联系删除！