845主板电路图

5 5 4 4 3 3 2 2 1 1 D D C C B B A A Schematic Page# COVER SHEET1 Revision X2 Last Change : 2002-09-26 2 3 4 5 BLOCK-POWER BLOCK DIAGRAM 6 7 8 CPU-P4 BUS CPU-P4 POWER 9 10 MCH-SYSBUS & CLOCK MCH-AGP & DDR MCH-POWER11 12 13 14 DDR-DIMM 0 ICH4-SYSBUS & PCI SIO0-LPC47M107 15 16 19 17 18 LAN-10/100/1000 BUS 20 21 23 22 24 25 26 27 28 AC97-AD1885 VGA-COUGAR-01 CLK-ICS950201 CONN-PCI CONN-COM1/COM2/LPT USB0-USB1-LAN0 DDR-POWER POWER Prefix Netobject H_ P4 HOSTBUS SIGNAL CLOCK SIGNALCK_ ICH4-LPC & IDE & USB ICH4-POWER GLUE LOGIC SIO1-LPC47N227 CONN-COM3/COM4/KBC VGA-COUGAR-02 VGA-COUGAR-03 CONN-01 IDE-FLOPPY 29 30 31 SYSTEM CONTROL M_ MEMORY BUS SIGNAL V_ POWER G_ AGP BUS SIGNAL CPU-ITP DDR-DIMM 1 32 USB2-USB5 33 LAN-10/100/1000 CONN A_ CRITICAL ANALOG TRACES MECH-ROUTE NOTES 34 35 F_ FLOPPY DISK SIGNAL L_ LPC BUS SIGNAL P_ PCI BUS SIGNAL AC_ AC97 SIGNAL KB_ KEYBOARD SIGNAL LP_ LPT1284 SIGNAL MS_ MOUSE SIGNAL ZV_ ZV VIDEO PORT SIGNAL AUD_ ANALOG AUDIO SIGNAL GND_ GND SIGNAL DERIVED I2C_ I2C BUS SIGNAL IDE_ IDE SIGNAL INT_ INTERRUPT SIGNAL LANn_ LAN CONTROLLER n SIGNAL SPn_ SERIAL PORT n SIGNAL USB_ USB PORT SIGNAL APIC_ APIC SIGNAL General Note: All Parts marked 'XXX1' will not be assembled in V1. All Parts marked 'XXX2' will not be assembled in V2. EEn_ SERIAL EEPROM LANn EN_ ENABLE FOR POWER SOURCES FWH_ FIRMWARE HUB SIGNAL GND GND POWER MIDI_ MIDI SIGNAL Changes from X1 to X2 1 2 All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity R712 changed from 10k to 15k to adjust voltage 3 PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5) 4 Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error PU R758 added at CN34.7 (SYS_RESET#)5 6 7 8 9 10 PU R759 added at U39.4 (VIDPWRGD) C717 changed from 4u7 to 1u R607 not populated 11 12 13 R571 and R572 not populated (FWH Test Pins) R585 and R586 not populated (for LVDS 18 Bit) 14 15 16 R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset R501 and R494 not populated due to PCI config of LAN 82540 U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25) R496 changed to 4k7 and set to GND (PD M66EN) R525 and R499 is now populated R530 not populated due to wrong V_2V5LAN voltage 17 18 19 U20.G4 is now 51R Pulldown to GND U20.H4 is now 33R Pullup to V_3V3LAN 20 21 22 23 AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4) Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R) R615 changed to 4K32 due to Cougar Bug 24 HW Rev changed to 2 at Glue Logic 25 26 R373 is now populated with 10M CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND 27 PU R761-R765 added to VID[0:4] PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options) 28 29 30 HD-LED-power connected to V_5V0 instead of V_5V0SB PD R768 added to PS_ON PU R769 added to U3.28 (PGOOD408#) 31 32 33 PD R770, R771, R772 added to power enables (default off, if CPLD not configured) PD R773-R776 added to serial port shut down pins Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs 34 Removed R383, R384, R385 35 Added D25 to avoid crossvoltages from VGA Monitor 36 Added D26 to avoid crossvoltages LPT Port 37 Alternative population of L7 to L12 with resistors (0R) PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R38 39 U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar 40 Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM 41 CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING) 42 V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25) 43 Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. * Other names and brands may be claimed as the property of others. Intel (R) 845E Interactive Client Reference Design APPENDIX C B444B-W 2.00 COVER SHEET Intel (R) 845E Interactive Client Reference Design C 1 35Monday, April 21, 2003 Title Size Document Number Rev Date Sheet of 5 5 4 4 3 3 2 2 1 1 D D C C B B A A SET = Intel Pentium 4 Processor-M HW REV 2 SW REV 0 B444B-W 2.00 GLUE LOGIC Intel (R) 845E Interactive Client Reference Design C 18 35Monday, April 21, 2003 Title Size Document Number Rev Date Sheet of DPSLP DPSLPX CPUSLPX# CPUSLP 7SEG0AX XC_CK1 7SEG0DP 7SEG0D 7SEG1DX VID0 7SEG1BX 7SEG0A 7SEG1CX 7SEG0EX DPSLP 7SEG1GX 7SEG0C7SEG0CX PORT_EN 7SEG0F PWMVID0 XCTMS 7SEG1G 7SEG0DPX 7SEG1A L_AD2 7SEG0DX PWMVID4 L_AD3 7SEG0BX 7SEG0FX XCTDI 7SEG0G XCTCK 7SEG1F VID1 7SEG1FX XCTDO 7SEG0E XC_CK0 7SEG1E 7SEG1C 7SEG1DPX PWMVID1 7SEG0GX 7SEG0B VID4 7SEG1DP L_AD0 PWMVID3 PWMVID2 7SEG1AX VID2 7SEG1D VID3 CPUSLP 7SEG1B L_AD1 7SEG1EX NW_MOBILE# SW_REV2 SW_REV1 SW_REV0 DELAY3V3 GND GND GND V_3V3SB V_3V3 V_3V3SB V_3V3SB GND V_3V3SB GND GND GND V_3V3SB V_3V3SB V_3V3SB GND V_3V3SB V_3V3SB V_3V3SB GND GND GND V_3V3SB V_3V3SB GND V_3V3SB GND GND Q6 BC847/B 3 1 2 R402 10KA R424 150RA R4 07 0R A R423 150RA C293 100nA R4 05 10 KA U7 XCR3128XL 18 34 3 39 51 66 82 91 26 38 43 5974 86 95 11 4 15 73 62 72 71 70 69 68 67 65 64 63 75 76 77 78 79 80 81 83 84 85 61 60 58 57 56 55 54 53 52 90 89 88 87 40 41 42 44 45 46 47 48 49 50 2 1 100 99 98 97 96 94 93 92 5 6 7 8 9 12 13 14 37 36 35 33 32 31 30 29 28 27 16 17 19 20 21 22 23 24 25 10 VCC2 VCC3 VCC1 VCC4 VCC5 VCC6 VCC7 VCC8 GND1 GND2 GND3 GND4GND5 GND6 GND7 PORT_EN/PE TDI/F1 TMS/H1 TDO/A1 TCK/C1 A2 A3 A4 A5 A6 A10 A12 A13 A14 B0 B1 B2 B3 B4 B5 B6 B10 B11 B12 C2 C3 C5 C6 C10 C11 C12 C13 C14 CLK0/IN0 CLK1/IN1 CLK2/IN2 CLK3/IN3 D1 D2 D3 D4 D5 D6 D10 D11 D12 D13 E0 E1 E2 E3 E4 E5 E6 E12 E13 E14 F2 F3 F4 F5 F6 F13 F14 F15 G1 G2 G3 G4 G5 G6 G10 G11 G12 G13 H2 H3 H5 H6 H10 H11 H12 H13 H14 F10 U8 TDSR1150 7 6 4 2 1 10 9 5 3 8 A B C D E F G DP AN1 AN2 R411 150RA R393 470RA Q7 BC847/B 3 1 2 R760 10KA R394 470RA R399 10KA JP3 SM02/RA XXX1 XXX2 1 2 R398 10KA R392 470RA R400 10KA R418 150RA U9 TDSR1150 7 6 4 2 1 10 9 5 3 8 A B C D E F G DP AN1 AN2 R419 150RA R412 150RA C295 100nA + C741 4u7/TA R4 08 0R A R416 150RA R415 150RA C297 100nA R4 09 0R A R406 10KA R410 150RA R414 150RA R395 10KA R417 150RA R401 10KA CN4 SM09/RA 1 2 3 4 5 6 78 9 VCC GND NC1 TCK NC2 TDO TDINC3 TMS C294 100nA R397 10KA R421 150RA R768 10KA R413 150RA R420 150RA R4 03 10 KA R422 150RA R425 150RA C296 100nA R396 10KA R4 04 10 KA CPUSLP#6,15 DPSLP# 7 V_3V36,8,12,15..17,19,20,23,26..29,33,35 GND4,7,8,10..17,19..35 V_3V3SB15..17,19,20,24,25,29,31..33,35 SLP_S4#16 CK_32KSUS16,19 SLP_S3#16,31,32 XC_GPIO3 16 P_RST0#9,15,33 PCI_STOP#12 PGOOD408#12 L_FRAME#16,19,20,33 CK_CPLD12 PWRDWN#12 SKTOCC#6 SLP_S5#16 RSMRST#16 PWMVID[0..4]35 L_AD[0..3]16,19,20,33 VID[0..4]7,33 RI# 16,24 SERIRQ15,19,20,29 CLKRUN#20,24,29 XC_LAN0RST# 15 CPU_STOP#12 PWROK_VRM35 PWROK_ATX35 VRMPWRGD_ICH 16 PWRGD_ICH 16 VRMOUTEN 35 VIDPWRGD35 PG_VDDR34 PG_V1V534 EN_VDDR 34 EN_V1V5 34 SD_DDRVTT# 34 ITP_DBR#7,8 EN_1V2VID 35 XC_GPIO2 16 XC_GPIO1 16 XC_GPIO4 16 PS_ON35 EN_DDRSUP# 34 5 5 4 4 3 3 2 2 1 1 D D C C B B A A I/O base address at 0x02E KEY IR PORT GAME PORT/MIDI B444B-W 2.00 SIO0-LPC47M107 Intel (R) 845E Interactive Client Reference Design C 19 35Monday, April 21, 2003 Title Size Document Number Rev Date Sheet of L_AD0 L_AD3 L_AD2 SYSOPT0 L_AD1 LP_D[0..7] LP_D0 V_IR XJ2Y XJ2X XJ1Y XJ1XJ1X J1Y J2X J2Y J2B2 J2B1 J2B1 J2B2 J2X J2Y LP_D1 LP_D2 LP_D3 LP_D4 LP_D5 LP_D6 LP_D7 IRRX_IR IRRX_IR IRTX_IR MIDI_OUTX MIDI_INX MIDI_OUT MIDI_IN MIDI_OUT V_GAME IRTX_IR GND_IR J1B1 J1X J1B1 J1B2 J1B2 J1Y MIDI_IN V_GAMEF GND GND GND GND GND GND GND GND GND V_3V3 V_3V3 V_3V3SB V_3V3SB V_3V3SB V_5V0V_5V0 V_5V0 V_5V0 V_5V0 V_5V0SB V_5V0SB GND GND F1 SMD075-2 1 2 R428 1KA C308 47pA + C299 4u7/TA + C304 4u7/TC R437 220RA + C313 4u7/TC C309 10nA C300 100nA R431 2KA R435 4K7A R4 38 2K A U10 LPC47M107 31 607 76 28 30 27 25 24 26 29 19 91 90 88 87 86 89 85 84 95 96 100 97 98 99 92 94 15 13 14 16 4 3 5 8 9 11 10 12 1 2 83 82 66 67 80 81 77 79 78 75 74 73 72 71 70 69 68 63 62 61 17 23 22 21 20 48 49 50 51 52 54 55 56 57 58 59 6 32 33 34 35 36 37 38 39 40 41 42 4345 46 47 64 18 53 65 93 44 G ND G ND G ND G ND GPIO43/DDRC SER_IRQ LPCPD# LDRQ# LFRAME# PCI_RESET# PCI_CLOCK CLOCKI DCD1# RI1# CTS1# SYSOP/RTS1# DSR1# DTR1# TXD1 RXD1 GPIO52/IRRX/RXD2 GPIO53/IRTX/TXD2 GPIO57/DTR2# GPIO54/DSR2# GPIO55/RTS2# GPIO56/CTS2# GPIO50/RI2# GPIO51/DCD2# WP# INDEX# TRAK0# RDATA# DSKCHG# MTR0# DS0# DIR# STEP# WGATE# WDATA# HDSEL# GPIO40/DRVDEN0 GPIO41/DRVDEN1 STB# AFD# INIT# SLCTIN# ACK# ERR# SLCT BUSY PE PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 KBDRST#/GPIO36 GP35/IRTX2 GP34/IRRX2 IO_PME#/GPIO42 LAD3 LAD2 LAD1 LAD0 LED1/GPIO60 LED2/GPIO61 IO_SMI#/GPIO27 FAN_TACH2/GPIO30 FAN_TACH1/GPIO31 FAN2/GPIO32 FAN1/GPIO33 KDAT KCLOCK MDAT MCLOCK CLOCKI32 J1B1/GPIO10 J1B2/GPIO11 J2B1/GPIO12 J2B2/GPIO13 J1X/GPIO14 J1Y/GPIO15 J2X/GPIO16 J2Y/GPIO17 AG ND GPIO20/P17 GPIO21/P16/DS1# GPIO22/P12/MTR1#GPIO24/SYSOPT MIDI_IN/GPIO25 MIDI_OUT/GPIO26 A20M/GPIO37 VT R VC C VC C VC C VR EF C311 10nA R432 2KA C305 47pA C306 47pA C312 10nA C301 100nA C310 10nA C302 100nA R429 1KA C298 100nA R430 1KA R426 10KA FB5 BLM21B601S C303 100nA R436 220RA CN6 SM16/WA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R434 2KA FB7 BLM21B601S CN5 SM06/SA XXX1 XXX2 1 2 3 4 5 6 R4 39 2K A R433 2KA FB6 BLM21B601S C307 47pA R427 1KA P_RST1#15,20,24,26 FAN2_SENSE33 CK_14M12,16,20,27 CK_LPC012 CK_32KSUS16,18 FAN1_SENSE33 LPCPD#16,20 SP2_TXD 21 SP1_RTS# 21 LP_AFD# 21 F_DIR# 30 SP1_TXD 21 SP2_DTR# 21 F_HDSEL# 30 LP_SLIN# 21 F_STEP# 30 SP1_DTR# 21 F_DRVDEN0 30 F_DS1# 30 F_DS0# 30 LP_STB# 21 F_WDATA# 30 F_MTR0# 30 F_DRVDEN1 30 LP_INIT# 21 F_MTR1# 30 F_WGATE# 30 SP2_RTS# 21 LP_ERR# 21 SP1_CTS# 21 F_RDATA# 30 F_WP# 30 SP2_RXD 21 SP2_RI# 21 F_TRAK0# 30 SP2_DSR# 21 LP_BUSY 21 SP1_DCD# 21 LP_PE 21 F_DSKCHG# 30 SP1_RXD 21 F_INDEX# 30 SP1_RI# 21 SP2_DCD# 21 LP_ACK# 21 SP2_CTS# 21 SP1_DSR# 21 KB_RST#15 SIO0_SMI#16 A20GATE15 FAN2_PWM33 L_DRQ#016 PWM_BL27 SIO0_PME#16 LP_D[0..7] 21 LP_SLCT 21 KB_CLK22 KB_DAT22 MS_DAT22 L_FRAME#16,18,20,33 MS_CLK22 L_AD[0..3]16,18,20,33 SERIRQ15,18,20,29 V_3V3SB15..18,20,24,25,29,31..33,35 GND4,7,8,10..18,20..35 V_3V36,8,12,15..17,20,23,26..29,33,35 V_5V0SB17,21,22,31..35 V_5V017,20,21,23,25..27,29..35 PWR_LED_GRN33 PWR_LED_YEL33 SP1_SD#21 SP2_SD#21 5 5 4 4 3 3 2 2 1 1 D D C C B B A A FIR PORT KEY I/O base address at 0x04E B444B-W 2.00 SIO1-LPC47N227 Intel (R) 845E Interactive Client Reference Design C 20 35Monday, April 21, 2003 Title Size Document Number Rev Date Sheet of IRRX_FIR IRTX_FIR V_FIRL_AD2 IRRX_FIR L_AD0 L_AD3 L_AD1 IRTX1_FIR MODE_IRRX_FIR SYSOPT1 GND GND GND GND GND GND V_3V3 V_3V3 V_3V3SB V_3V3SB V_3V3SB V_5V0 V_5V0 + C319 4u7/TC C314 100nA R441 100KA CN7 SM06/SA 1 2 3 4 5 6 U11 LPC47N227 53 31 65 60 93 7 76 28 30 27 25 24 26 29 19 18 91 90 88 87 86 89 85 84 95 96 100 97 98 99 92 94 15 13 14 16 4 3 5 8 9 11 10 12 1 2 83 82 66 67 80 81 77 79 78 75 74 73 72 71 70 69 68 63 62 61 17 23 22 21 20 48 49 50 51 52 54 55 56 57 58 59 6 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 64 VC C G ND VC C G ND VC C G ND G ND CLKRUN# SER_IRQ LPCPD# LDRQ# LFRAME# PCI_RESET# PCI_CLOCK CLOCKI VC CS B DCD1# RI1# CTS1# RTS1# DSR1# DTR1# TXD1 RXD1 RXD2 TXD2 DTR2# DSR2# RTS2# CTS2# RI2# DCD2# WP# INDEX# TRAK0# RDATA# DSKCHG# MTR0# DS0# DIR# STEP# WGATE# WDATA# HDSEL# DRVDEN0 DRVDEN1 DS0#/STB# DRVDEN0#/AFD# DIR#/INIT# STEP#/SLCTIN# DS1#/ACK# HDSEL#/ERR# WGATE#/SLCT MTR1#/BUSY WRDATA#/PE PD7 MTR0#/PD6 PD5 DSKCHG#/PD4 RDATA#/PD3 WP#/PD2 TRK0#/PD1 INDEX#/PD0 IRMODE/IRRX3 IRTX2 IRRX2 IO_PME# LAD3 LAD2 LAD1 LAD0 GPIO10 GPIO11/SYSOPT GPIO12/IO_SMI# GPIO13/IRQIN1 GPIO14/IRQIN2 GPIO15 GPIO16 GPIO17 GPIO20 GPIO21 GPIO22 GPIO24 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO23/FDC_PP + C315 4u7/TA C316 100nA C317 100nA R442 10KA C320 100nA R443 82RA R444 4K7A R440 100KA FB8 BLM21B601S C318 100nA CK_14M12,16,19,27 P_RST1#15,19,24,26 CK_LPC112 LPCPD#16,19 SP4_DTR# 22 SP3_RTS# 22 SP3_TXD 22 SP4_RTS# 22 SP3_DTR# 22 SP4_TXD 22 SP4_DCD# 22 SP3_DCD# 22 SP3_CTS# 22 SP4_RXD 22 SP3_RXD 22 SP4_DSR# 22 SP3_RI# 22 SP4_RI# 22 SP3_DSR# 22 SP4_CTS# 22 SERIRQ15,18,19,29 CLKRUN#18,24,29 L_DRQ#116 SIO1_PME#16 SIO1_SMI#16 L_FRAME#16,18,19,33 L_AD[0..3]16,18,19,33 V_5V017,19,21,23,25..27,29..35 V_3V3SB15..19,24,25,29,31..33,35 V_3V36,8,12,15..17,19,23,26..29,33,35 GND4,7,8,10..19,21..35 SP3_SD#22 SP4_SD#22 5 5 4 4 3 3 2 2 1 1 D D C C B B A A LPT COM2 COM1 B444B-W 2.00 CONN COM1/COM2/LPT Intel (R) 845E Interactive Client Reference Design C 21 35Monday, April 21, 2003 Title Size Document Number Rev Date Sheet of SP1_DCD1# V_SP2V- V_SP1C1+ V_SP1V- V_SP1V+ V_SP2C2+ V_SP2C1+ V_SP2V+ SP1_TXD1 V_SP1C1- V_SP2C1- V_SP1C2+ SP1_CTS1# V_SP1C2- SP1_RI2# SP2_RI1# SP1_RTS2# SP1_DSR1# V_SP2C2- GND_LPT SP1_RI1# SP1_DTR1# SP1_DCD2# SP1_TXD2 SP1_RXD1 SP1_RTS1# SP1_RXD2 SP1_EN SP2_EN V_5V0LPT SP2_DCD1# SP2_CTS2#SP2_CTS1# SP2_DCD2# SP2_RTS1# SP2_RTS2# SP2_DTR1# SP2_DSR1# SP2_TXD1 SP2_DSR2# SP2_TXD2 SP2_DTR2# SP2_RXD2SP2_RXD1 SP2_RI2# LP_D0 LP_D[0..7] LP_DX7 LP_DX0 LP_DX3 LP_DX2 LP_DX6 LP_STBX# LP_DX1 LP_DX4 LP_DX5 LP_STBOUT# LP_DOUT0 LP_D1 LP_D2 LP_D3 LP_D4 LP_D5 LP_D6 LP_D7 LP_PEX LP_SLCTX LP_AFDX# LP_SLINX# LP_BUSYX LP_INITX# LP_ERRX# LP_ACKX# LP_DOUT1 LP_DOUT2 LP_DOUT3 LP_DOUT4 LP_DOUT5 LP_DOUT6 LP_DOUT7 SP1_DSR2# SP1_CTS2# SP1_DTR2# GND GND GND GND GND V_5V0 V_5V0 V_5V0SB V_5V0SB V_5V0SB V_5V0SB V_5V0SB SHIELD SHIELD SHIELD SHIELD GND GND GND SHIELD GND GND GND GND GND C322 100nA C336 100nA FB45 BLM11A601SPT U12 MAX213ECAI 11 13 12 14 22 6 7 8 20 5 26 19 2410 17 15 16 25 23 3 2 9 1 4 27 18 2821 VCC V+ C1+ C1- RXOUT4 DRIN2 DRIN1 RXOUT1 DRIN3 RXOUT2 RXOUT3 RXOUT5 ENGND V- C2+ C2- SD# RXIN4 DROUT2 DROUT1 RXIN1 DROUT3 RXIN2 RXIN3 RXIN5 DROUT4DRIN4 FB44 BLM11A601SPT FB33 BLM11A601SPT FBN4ABLA3216A601 1 2 C3 54 22 0p A CA 1C 47 0p X4 5 6 C3 53 22 0p A C3 56 22 0p A CA 1A 47 0p X4 1 2 FBN3ABLA3216A601 1 2 C3 61 22 0p A C3 58 22 0p A C3 62 22 0p A C323 100nA R445 10KA C3 60 22 0p A FBN4DBLA3216A601 7 8 CA 1D 47 0p X4 7 8 C3 59 22 0p A FB41 BLM11A601SPT FBN3DBLA3216A601 7 8 FBN1ABLA3216A601 1 2 C3 50 22 0p A FB30 BLM11A601SPT CN8B SW47/XA B2 B3 B4 B6 B7 B8 B9 B5 B1 RX2 TX2 DTR2# DSR2# RTS2# CTS2# RI2# GND2 DCD2# FB31 BLM11A601SPT FBN3CBLA3216A601 5 6 FB35 BLM11A601SPT R776 10KA C338 100nA CN8C SW47/XA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C16 C15 C17 C18 C19 C20 C21 C22 C23 C24 C25 DR1 DR2 DR3 DR4 STRB# D0 D1 D2 D3 D4 D5 D6 D7 ACK# BUSY PE SLCT AFD# INIT# ERR# SLCTIN# GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 DR1 DR2 DR3 DR4 C3 52 22 0p A D26 BAT54 FBN2CBLA3216A601 5 6 C3 51 22 0p A CF1 PAC_LPT1284 28 1 22715 12 10 8 26 20 22 3 14 13 11 9 7 6 5 4 16 17 18 19 21 23 24 25 AF D# IN IT # SL IN # ER R# AC K# BU SY PE SL CT STBOUT# VCC GND STBIN# D7IN D6IN D5IN D4IN D3IN D2IN D1IN D0IN D7OUT D6OUT D5OUT D4OUT D3OUT D2OUT D1OUT D0OUT CA 4D 47 0p X4 7 8 FBN3BBLA3216A601 3 4 C335 100nA FB42 BLM11A601SPT CA 2C 47 0p X4 5 6 FBN1DBLA3216A601 7 8 C3 47 22 0p A FB34 BLM11A601SPT C3 49 22 0p A C334 100nA FBN2ABLA3216A601 1 2 CA 3D 47 0p X4 7 8 CA 4B 47 0p X4 3 4 FB28 BLM11A601SPT CA 2A 47 0p X4 1 2 FBN1BBLA3216A601 3 4 FB38 BLM11A601SPT CN8A SW47/XA A2 A3 A4 A6 A7 A8 A9 A5 A1 RX1 TX1 DTR1# DSR1# RTS1# CTS1# RI1# GND1 DCD1# R775 10KA FBN2DBLA3216A601 7 8 CA 3A 47 0p X4 1 2 CA 4A 47 0p X4 1 2 R446 10KA C3 63 22 0p A FB43 BLM11A601SPT CA 2B 47 0p X4 3 4 FBN1CBLA3216A601 5 6 C337 100nA U13 MAX213ECAI 11 13 12 14 22 6 7 8 20 5 26 19 2410 17 15 16 25 23 3 2 9 1 4 27 18 2821 VCC V+ C1+ C1- RXOUT4 DRIN2 DRIN1 RXOUT1 DRIN3 RXOUT2 RXOUT3 RXOUT5 ENGND V- C2+ C2- SD# RXIN4 DROUT2 DROUT1 RXIN1 DROUT3 RXIN2 RXIN3 RXIN5 DROUT4DRIN4 FB29 BLM11A601SPT FBN2BBLA3216A601 3 4 CA 3C 47 0p X4 5 6 C325 100nA CA 4C 47 0p X4 5 6 FBN4CBLA3216A601 5 6 FB32 BLM11A601SPT CA 2D 47 0p X4 7 8 FB39 BLM11A601SPT C3 57 22 0p A FB40 BLM11A601SPT FB36 BLM11A601SPT CA 3B 47 0p X4 3 4 C321 100nA FBN4BBLA3216A601 3 4 CA 1B 47 0p X4 3 4 C324 100nA C3 55 22 0p A C3 48 22 0p A SP1_RTS#19 SP2_RTS#19 SP1_DTR#19 SP1_TXD19 SP1_SD#19 SP2_DTR#19 SP2_TXD19 LP_STB#19 LP_INIT#19 LP_AFD#19 LP_SLIN#19 SP2_RXD19 SP1_RI#19 SP1_RXD19 SP1_CTS#19 SP2_DSR#19 SP2_RI#19 SP1_DCD#19 SP1_DSR#19 SP2_CTS#19 SP2_DCD#19 LP_BUSY19 LP_ERR#19 LP_PE19 LP_SLCT19 LP_ACK#19 LP_D[0..7]19 V_5V0SB17,19,22,31..35 V_5V017,19,20,23,25..27,29..35 GND4,7,8,10..20,22..35 SHIELD23,25,27,31,32 SP2_SD#19 5 5 4 4 3 3 2 2 1 1 D D C C B B A A COM3 COM4 KBC & MOUSE B444B-W 2.00 CONN COM3/COM4/KBC Intel (R) 845E Interactive Client Reference Design C 22 35Monday, April 21, 2003 Title Size Document Number Rev Date Sheet of V_SP3C2+ SP3_DCD1# SP3_DTR1# V_SP3C1- SP3_CTS1# V_SP4C1- SP3_RI1# V_SP4C2- V_SP3V- SP3_TXD1 SP3_RTS1# SP3_RXD1 V_SP3C2- V_SP4C1+ V_SP4V+ SP3_DSR1# V_SP4V- V_SP4C2+ SP3_RI2# V_SP3V+ V_SP3C1+ SP4_EN SP3_RXD2 SP3_TXD2 SP3_DTR2# SP3_RTS2# SP3_CTS2# SP3_DCD2# SP3_EN SP3_DSR2# SP4_DCD2# SP4_TXD2 SP4_RI2# SP4_RXD2 SP4_RTS2# SP4_CTS2# SP4_DTR2# MS_DATOUT MS_CLKOUT KB_CLKOUT KB_DATOUT SP4_CTS1# SP4_TXD1 SP4_RTS1# SP4_RI1# SP4_RXD1 SP4_DCD1# SP4_DTR1# SP4_DSR1# SP4_DSR2# V_KBOUT GND GND GND GND GND GND GND SHIELD GND GND GND V_5V0SB V_5V0SB V_5V0SB V_5V0SB V_5V0SB V_5V0SB V_5V0SB GND GND GND GND GND FB59 BLM11A601SPT R4 49 4K 7A R447 10KA CN11 SM10/SA 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 C3 71 47 0p A C3 82 47 0p A C3 73 47 0p A C3 75 47 0p A CN9 SM10/WA 1 3 5 7 9 2 4 6 8 10 DCD# RX TX DTR# GND DSR# RTS# CTS# RI# NC F2 SMD075-2 1 2 FB56 BLM11A601SPT FB48 BLM11A601SPT C3 93 47 pA XX X1 XX X2 R773 10KA FB50 BLM11A601SPT FB49 BLM11A601SPT C3 86 47 0p A C379 100nA FB51 BLM11A601SPT FB64 BLM11A601SPT FB55 BLM11A601SPT R4 51 4K 7A FB47 BLM11A601SPT C3 83 47 0p A FB65 BLM11A601SPT FB57 BLM11A601SPT FB52 BLM11A601SPT C3 85 47 0p A C366 100nA C3 69 47 0p A CN10 SM10/WA 1 3 5 7 9 2 4 6 8 10 DCD# RX TX DTR# GND DSR# RT