基于multisim及锁相环的2PSK2ASK2FSK的调制解调电路仿真

基于multisim及锁相环的2PSK2ASK2FSK的调制解调电路仿真 LANZHOU UNIVERSITY OF TECHNOLOGY 毕业 设计 领导形象设计圆作业设计ao工艺污水处理厂设计附属工程施工组织设计清扫机器人结构设计 题 目 基于Multisim的锁相环解调系统仿真 学生姓名 学 号 专业班级 指导教师 学 院 计算机与通信学院 答辩日期 to organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at using the Internet and doing mass work well, follow the mass line, "face to face", and "key of keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and better the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out 兰州理工大学毕业设计 基于Multisim的锁相环解调系统仿真 PLL Demodulation System Simulation Based on Multisim I 兰州理工大学毕业设计 摘要 实现调频波解调的方法有很多，而锁相环鉴频是利用现代锁相环技术来实现鉴频，具有工作稳定，失真小，信噪比高等优点，所以被广泛用在通信电路系统中。锁相环其原理是通过鉴相 检测 工程第三方检测合同工程防雷检测合同植筋拉拔检测方案传感器技术课后答案检测机构通用要求培训 输入信号和输出信号的相位差，并将检测出的相位差信号转换成电压信号输出，该信号经低通滤波器滤波后形成压控振荡器的控制电压，对振荡器输出信号的频率实施控制。 该文首先介绍了锁相环技术发展的现状、方向以及背景，并对PLL的原理进行了阐述。在以上的基础上，分别设计了2ASK、2PSK、2FSK的调制解调电路，其功能为数字基带信号经过调制输出一个模拟信号，然后用锁相环进行解调，最后采用Multisim软件进行仿真。在对2ASK、2FSK、2PSK解调时，低通滤波器输出的波形失真比较大，不过最后经过抽样判决电路整形后可以再生数字基带脉冲。在整个电路设计中，力求要做到电路简单，并完成任务书提到的要求。 关键词:调制;解调; Multisim;锁相环 I Abstrack There are many ways to realize frequency wave demodulation, and PLL frequency which has the advantages of stable operation, small distortion, high signal-to-noise ratio and so on is achieved by using modern PLL frequency technology, so it is widely used in communication circuit system. Phase-locked loop through the difference of the phase detection of input signal and the output signal phase, and the detected phase difference signal into output voltage signal, the signal through a low pass filter. After the formation of the voltage control oscillator , the output signal of the oscillator frequency control. This paper first introduces the present situation, development direction, phase-locked loop technology as well as the background, and the principle of PLL is discussed. On the basis of the above, the modulation and demodulation circuit of 2ASK, 2PSK, 2FSK which function is a digital baseband signal is modulated by an analog signal and output were designed, and then useing the PLL demodulation, finally using Multisim software simulation. In the 2ASK, 2FSK, 2PSK demodulation, the output of the low pass filter waveform distortion is relatively large, but finally it can regenerate digital baseband pulse sampling decision circuit after shaping. In the circuit design, and strive to do a simple circuit, and complete the task book mentioned requirements. Keywords: modulate ;modulation ;PLL;Multisim IIthe fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 目 录 第1章 绪论 ..............................................................1 1.1 研究背景 ..........................................................1 1.2 研究现状 ..........................................................1 1.3 研究内容介绍 ......................................................2 第2章 基本原理..........................................................3 2.1 Multisim介绍 .....................................................3 2.2 锁相环基本原理 ...................................................5 2.2.1锁相环的基本组成 ............................................5 2.2.2 锁相环的工作原理 ............................................5 第3章 调制解调电路设计..................................................8 3.1 2FSK调制解调电路设计............................................8 3.1.1 2FSK调制电路设计原理......................................8 3.1.2 2FSK调制单元电路的设计....................................9 3.1.3 2FSK解调单元电路的设计...................................12 3.1.4 2FSK解调电路的整体设计...................................15 3.2 2PSK调制解调电路设计...........................................17 3.2.1 2PSK调制解调电路设计原理.................................17 3.2.2 2PSK调制与解调电路的设计与仿真 ..........................18 3.3 2ASK调制解调电路设计 ..........................................19 3.3.1 2ASK调制解调电路设计原理 ................................19 3.3.2 2ASK调制与解调电路的设计与仿真 ..........................20 3.4 解调结果分析 ....................................................22 总结 .....................................................................24 参考文献 .................................................................25 附录:(外文翻译).........................................................26 致谢 .....................................................................49 III 兰州理工大学毕业设计 第1章 绪论 1.1 研究背景 实现调频波解调的方法有很多，而锁相环鉴频是利用现代锁相环技术来实现鉴频方法，具有工作稳定失真小，信噪比高等优点，所以被广泛用在通信电路系统中。锁相环路是一种反馈电路，锁相环的英文全称是Phase-Locked Loop，简称PLL。其作用是使得电路相位同步。因锁相环可以实现输出信号频率对输入信号频率的自动跟踪，所以锁相环通常用于闭环跟踪电路。锁相环在工作的过程中，当输出信号的频率与输入信号的频率相等时，输出电压与输入电压保持固定的相位差值，即输出电压与输入电压的相位被锁住，它还具有载波跟踪特性。作为一个窄带跟踪滤波器，可提取淹没在噪声中的信号;用高稳定的参考振荡器锁定，可提供高稳定的频率源;可进行高精度的香味与频率测量等等。如今锁相环解调器在通信、雷达、测量和自动化控制等领域应用极为广泛，随着电子技术的发展，对锁相环解调的研究和应用得到了越来越多的关注。 现在通过分析与研究，加深对锁相环解调方式的理解，并根据它的原理，设计出2FSK、2PSK、2ASK的调制电路，并通过锁相环解调出来。 1.2 研究现状 锁相环解调技术的发展十分迅速，如今已经在很多领域都应用了锁相环解调的理论。可用于手机中、SDH网络中、在汽车MP3无线发射器中‘测量汽车转速都是十分典型的应用。调频波的特点是频率随调制信号幅度的变化而变化，压控振荡器的振荡频率取决于输入电压的幅度。当载波信号的频率与锁相环的固有振荡频率ω0相等时，压控振荡器输出信号的频率将保持ω0不变。若压控振荡器的输入信号除了有锁相环低通滤波器输出的信号uc外，还有调制信号ui，则压控振荡器输出信号的频率就是以ω0为中心，随调制信号幅度的变化而变化的调频波信号。当然，锁相环的许多优越性使得锁相环解调技术在很多我们周围都可以见到的物品中发挥着其巨大的功效。 如今，锁相环路理论与研究日臻完善，应用范围遍及整个电子技术领域。随着通信及电子系统的飞速发展，促使集成锁相环和数字锁相环突飞猛进。现在品种齐全繁多，提高系统的工作稳定性和可靠性和小型化，目前仍朝着集成化，数字化，多用化方向迅 1 速发展。 1.3 研究内容介绍 调制和解调电路是通信设备中重要组成部分。用待传输的低频信号去控制高频载波参数电路称为调制电路，解调是调制的逆过程，从高频已调信号中还原出原调制信号称为解调电路。 该文主要建立了2ASK、2FSK、2PSK的调制解调电路。解调电路中使用了锁相环解调。锁相环路的输出信号频率可以精确地跟踪输入参考信号频率的变化,环路锁定后输入参考信号和输出参考信号之间的稳态相位误差可以通过增加环路增益被控制在所需数值范围内.这种输出信号频率随输入参考信号频率变化的特性称为锁相环的跟踪特性.利用此特性可以做载波跟踪型锁相环及调制跟踪型锁相环。为了实现信息的远距离传输，收信端接收到信号后必须进行解调才能恢复原信号。所谓的解调就是用携带信息的输出信号uo来还原载波信号ui的参数，载波信号的参数有幅度、频率和位相，所以，解调有调幅(AM)、调频(FM)和调相(PM)三种。调幅波的特点是频率与载波信号的频率相等，幅度随输入信号幅度的变化而变化;调频波的特点是幅度与载波信号的幅度相等，频率随输入信号幅度的变化而变化;调相波的特点是幅度与载波信号的幅度相等，相位随输入信号幅度的变化而变化。该文中调制出2FSK、2ASK、2PSK，调制时采用的是锁相环解调出来,最后用Multisim进行仿真出效果。在对2ASK、2FSK、2PSK解调时，低通滤波器输出的波形失真比较大，不过最后经过抽样判决电路整形后可以再生数字基带脉冲。 2the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 第2章 基本原理 2.1 Multisim介绍 随着电子技术和计算机技术的发展，电子产品已与计算机紧密相连，电子产品的智能化日益完善，电路的集成度越来越高，而产品的更新周期却越来越短。 Multisim 10是加拿大 Interactive Image Technologies公司 2001 年推出的 Multisim 最新版本。可以设计、测试和演示各种电子电路，包括电工电路、模拟电路、数字电路、射频电路及部分微机接口电路等。可以对被仿真的电路中的元器件设置各种故障，如开路、短路和不同程度的漏电等，从而观察不同故障情况下的电路。 它有丰富的元件库，为用户提供元器件模型的扩充和技术;虚拟测试仪器仪表种类齐全，其操作方法与实际仪器十分相似;具有较为详细的电路分析功能，可以完成电路的瞬态分析和稳态分析、时域和频域分析、器件的线性和非线性分析、电路的噪声分析和失真分析、离散傅里叶分析、电路零极点分析、交直流灵敏度分析等 18 种电路分析方法，提供了多种输入输出接口，Multisim10可以与国内外流行的印刷电路板设计自动化软件Protel及电路仿真软件Pspice之间的文件接口，也能通过Windows 电路图送往文字处理系统中进行编辑排版，同时还支持VHDL和Verilog HDL语言的电路仿真与设计。 Multisim 10 把所有的元件分成13类库，再加上放置分层模块、总线、登录网站共同组成元件工具栏。 Multisim 10提供了18种仪表，仪表工具栏通常位于电路窗口的右边，也可以用鼠标将其拖至菜单的下方，呈水平状。 Multisim 10具有以下特点: (1)Multisim 10是一个电路原理设计、电路功能测试的虚拟仿真软件。其元器件库提供数千种电路元器件供实验选用，同时也可以新建或扩充已有的元器件库，而且建库所需的元器件参数可以从生产厂商的产品使用手册中查到，因此可以很方便地在工程设计中使用。 (2)Multisim 10 的虚拟测试仪器仪表种类齐全，有一般实验用的通用仪器，如万用表、信号发生器、双通道示波器、直流电源;还有一般实验室少有或没有的仪器，如波 3 特图示仪、字信号发生器、逻辑分析仪、逻辑转换器、失真度测量仪、频谱分析仪和网络分析仪等。 (3) Multisim 10 具有较详细的电路分析功能，可以完成电路的瞬态和稳态分析、时域和频域分析、器件的线性和非线性分析、电路的噪声和失真分析、离散傅里叶分析、电路零极点分析、交直流灵敏度分析等，以帮助设计人员分析电路的性能。 (4) Multisim10可以设计、测试和演示各种电子电路，包括电工电路、模拟电路、数字电路、射频电路及部分微机接口电路等。可以对被仿真的电路中的元器件设置各种故障，如开路、短路和不同程度的漏电等，从而观察不同故障情况下的电路工作状况。在进行仿真的过程中还可以存储测试点的所有数据，列出被仿真电路的所有元器件清单，以及存储测试仪器的工作状态、显示波形和具体数据。 Multisim10是一个电路原理设计、电路功能测试的虚拟仿真软件。它用软件的方法模拟电子线路元器件和仪器仪表，实现了“软件即元器件”和“软件即仪器”。 Multisim10是一个电路原理设计、电路功能测试的虚拟仿真软件，该软件为电子工程师提供了一个电路设计与仿真平台，不仅与国际著名的模拟电路仿真软件spice兼容，而且具有较强的 VHDL和 Verilog设计与仿真功能。它具有界面形象、直观易懂、采用图形方式创建电路的特点;它丰富的元件库中提供了超过16000个组件，全部采用世纪模型，确保了仿真结果的真实性和实用性;它采用开放式的库管理模式，能自动地生成模拟和数字组件模型，这对新器件的补充十分有利。Multisim10的虚拟测试仪器种类齐全，有一般实验用的通用仪器，如万用表、信号发生器、双通道示波器、直流、交流电源;还有一般实验室少有或没有的仪器，如波特图示仪、字信号发生器、逻辑分析仪、逻辑转换器、失真度测试仪、频谱分析仪和网络分析仪等。 Multisim10具有较为详细的电路分析功能，可以完成电路的瞬态和稳态分析、时域和频域分析、器件的线性和非线性分析、电路的噪声分析和失真分析、离散傅里叶分析、电路零极点分析、交直流灵敏度分析等电路分析方法，以帮助设计人员分析电路的性能。 Multisim10可以设计、测试和演示各种电子电路，包括电工电路、模拟电路、数字电路、射频电路及微机接口电路等;可以对被仿真的电路中的元器件设置各种故障，如开路、短路和不同程度的漏电等，从而观察不同故障情况下的电路工作状况。在进行仿真的同时，软件还可以存储测试点的所有数据，列出被仿真电路的所有元器件清单，以及存储测试仪器的工作状态、显示波形和具体数等。 4the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 2.2 锁相环基本原理 2.2.1锁相环的基本组成 许多电子设备要正常工作，通常需要外部的输入信号与内部的振荡信号同步，利用锁相环路就可以实现这个目的。锁相环路是一种反馈控制电路，简称锁相环(PLL)。锁相环的特点是:利用外部输入的参考信号控制环路内部振荡信号的频率和相位。因锁相环可以实现输出信号频率对输入信号频率的自动跟踪，所以锁相环通常用于闭环跟踪电路。锁相环在工作的过程中，当输出信号的频率与输入信号的频率相等时，输出电压与输入电压保持固定的相位差值，即输出电压与输入电压的相位被锁住，这就是锁相环名称的由来。 锁相环通常由鉴相器(PD)、环路滤波器(LF)和压控振荡器(VCO)三部分组成，锁相环组成的原理框图如图2.1所示。 LFVCOPD 图2.1 锁相环基本组成 锁相环中的鉴相器又称为相位比较器，它的作用是检测输入信号和输出信号的相位差，并将检测出的相位差信号转换成电压信号输出，该信号经低通滤波器滤波后形成压控振荡器的控制电压，对振荡器输出信号的频率实施控制。 2.2.2 锁相环的工作原理 锁相环中的鉴相器通常由模拟乘法器组成，利用模拟乘法器组成的鉴相器电路如图2.2所示。 Ui(t) UoU 图2.2 乘法器 鉴相器的工作原理是:设外界输入的信号电压和压控振荡器输出的信号电压分别 5 为: (2-1) utUtt,，sin,,，，，，，，imii，， (2-2) utUtt,，cos,,，，，，，，oomoo，， 式中的ω为压控振荡器在输入控制电压为零或为直流电压时的振荡角频率，称为0 电路的固有振荡角频率。则模拟乘法器的输出电压u为: D (2-3) UKUUtttt,，，sin[()]cos[()],,,,Dmomiioo 11{sin[()]cos[()]}{sin[()]cos[()]}UKUUttttKUUtttt,，，，，，,，,,,,,,,, (2-4) Dmomiioomomiioo22 用低通滤波器LF将上式中的和频分量滤掉，剩下的差频分量作为压控振荡器的输 入控制电压。即为: Ut()Ut()cc 1UtKUUtttt,，,，,,,, (2-6) ()sin{[()][()]}cmomiioo2 (2-7) ,,，,Uttttsin{[][()()]},,,,dmioio 式中的ω为输入信号的瞬时振荡角频率，和分别为输入信号和输出信号,()t,()tioi的瞬时位相，根据相量的关系可得瞬时频率和瞬时位相的关系为: 即 ,,,()()ttdt,， (2-9) do, 则，瞬时相位差θ为 d ,,,,,,,，,[]()()tttt (2-10) dioio dt,(),()t) (2-11) ,dt 对两边求微分，可得频差的关系式为 ddttdtt,,,,,()[()()],,dioio,， (2-12) dtdtdt 上式等于零，说明锁相环进入相位锁定的状态，此时输出和输入信号的频率和相位 6the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 保持恒定不变的状态，为恒定值。当上式不等于零时，说明锁相环的相位还未锁Ut()c 定，输入信号和输出信号的频率不等，随时间而变化。 Ut()c 因压控振荡器的压控特性如图2.3所示，该特性说明压控振荡器的振荡频率ω以u ω为中心，随输入信号电压的变化而变化。该特性的表达式为 Ut()0c (2-13) ,,()()tKut,，uoc0 图2.3 压控特性 上式说明当随时间而变时，压控振荡器的振荡频率ω也随时间而变，锁相环Ut()uc ，自动跟踪捕捉输入信号的频率，使锁相环进入锁定的状态，并保持进入“频率牵引” ω=ω的状态不变。 0i 7 第3章 调制解调电路设计 3.1 2FSK调制解调电路设计 3.1.1 2FSK调制电路设计原理 2FSK即叫做二进制移频键控或二进制频移键控。 2FSK信号产生的方法一般有两种:一种叫直接调频法，另一种叫频移键控法。 (1)模拟调频法:即直接利用一个矩形脉冲序列对一个载波进行调频而获得。如图3.1所示: 模拟调频器S(t) 2FSK 图3.1 模拟调频法 直接调频法是频移键控通信方式早期采用的实现方法。其优点是调制方便，设备简单，得出的是2FSK信号，相位连续。 (2)键控法:即利用受矩形脉冲序列控制的开关电路对两个不同的独立频率源进行选通。如图3.2所示: f1振荡器选通开关 e(t) 反相器相加器 f2振荡器选通开关 图 3.2 键控法 2FSK键控法的特点是转换速度快、波形好、稳定度高且易于实现，故应用广泛，但设备要复杂些，得出的是2FSK信号，相位不连续。 该文采用键控法产生2FSK信号，即用一个受基带脉冲控制的开关电路去选择两个独立频率源的振荡作为输出。设计原理图如图3.3所示: 8the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 变频电路2FSK脉冲信号f1(产生正 弦波) 开关 4066BD 变频电路 双D触发器2f1(产生正基带 弦波)信号 图 3.3 2FSK调制原理图 3.1.2 2FSK调制单元电路的设计 要将时钟脉冲信号经过2FSK调制成为2FSK信号，我们采用一个受基带脉冲控制的开关电路去选择两个独立的频率源作为输出。键控法产生的2FSK信号频率稳定度可以做得很高并且没有过度频率，它的转换速度快，波形好。 1)四双向模拟开关CD4066 CD4066的引脚功能如图3.4所示。每个封装内部有4个独立的模拟开关，每个模拟开关有输入、输出、控制三个端子，其中输入端和输出端可互换。当控制端加高电平时，开关导通;当控制端加低电平时开关截止。模拟开关导通时，导通电阻为几十欧姆;模拟开关截止时，呈现很高的阻抗，可以看成为开路。模拟开关可传输数字信号和模拟信号，可传输的模拟信号的上限频率为40MHz。各开关间的串扰很小，典型值为,50dB。 图 3.4 四双向模拟开关CD4066 输入的基带信号由转换开关分成两路，一路控制f1=32KHz的载频，另一路经倒相 9 去控制f2=16KHz的载频。当基带信号为“1”时，模拟开关1打开，模拟开关2关闭，此时输出f1=32KHz，当基带信号为“0”时，模拟开关2开通。此时输出f2=16KHz，于是可在输出端得到2FSK已调信号。如图3.5所示: 图 3.5 模拟开关 2)变频电路 变频电路是将输入的二进制数字基带信号通过控制载频转换成已调信号，即2FSK调制信号。两路载频分别经射随、LC选频、射随再送至模拟开关。其中LC选频电路函 1数: ，选频网络如图3.6所示: ,fLC,2 图3.6 变频电路图 3)2FSK调制的整体电路图的设计 10the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 图3.7 2FSK的Multisim调制仿真电路图 4)2FSK调制电路的仿真 图3.8 脉冲信号输出波形 11 图3.9 变频电路输出波形 图3.10 2FSK的仿真效果图 3.1.3 2FSK解调单元电路的设计 锁相环通常由鉴相器(PD)、环路滤波器(LF)和压控振荡器(VCO)三部分组 12the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 成，该文锁相环解调原理框图如图3.11所示。 调制信号 模拟乘法器低通滤波器抽样判决基带信号 定时脉冲 压控振荡器 图 3.11 2FSK解调原理框图 1)锁相环中的鉴相器通常由模拟乘法器组成，利用模拟乘法器组成的鉴相器电路如图3.12所示: Ui(t) UoU 图3.12 乘法器 2)低通滤波器如图3.13所示: 用低通滤波器LF将和频分量滤掉，剩下的差频分量作为压控振荡器的输入控制电压u(t)。 C 13 图3.13 环路滤波器 3)压控振荡器的压控特性如图3.14所示，该特性说明压控振荡器的振荡频率ωu以ω为中心，随输入信号电压u(t)的变化而变化。该特性的表达式为 0c (3-1) ,,()()tKut,，uoc0 图3.14 压控特性 上式说明当u(t)随时间而变时，压控振荡器的振荡频率ω也随时间而变，锁相cu环进入“频率牵引”，自动跟踪捕捉输入信号的频率，使锁相环进入锁定的状态，并保持ω=ω的状态不变。压控振荡器的电路图如图3.15所示: 0i 图3.15压控振荡器 4)抽样判决电路(LM311) 14the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 工作原理:LM311是当2脚电压高于3脚电压时输出高电平，反之则输出低电平。引脚功能如下。 1脚 GROUND/GND 接地 2脚 INPUT+ 正向输入端 3脚 INPUT- 反相输入端 7脚 OUTPUT 输出端 5脚 BALANCE 平衡 6脚 BALANCE/STROBE 平衡/选通 8脚 V+ 电源+ 4脚 V- 电源- 图3.16 LM311引脚图 图3.17 抽样判决电路图 3.1.4 2FSK解调电路的整体设计 2FSK解调电路的设计是采用锁相环进行解调，2FSK信号通过锁相环最终解调出数字基带信号。2FSK基于Multisim仿真的解调电路的整体电路设计图如图3.18所示: 15 图3.18 2FSK的Multisim的解调仿真电路 图3.19 2FSK的Multisim解调电路的仿真 16the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 3.2 2PSK调制解调电路设计 3.2.1 2PSK调制解调电路设计原理 PSK分为二进制相位键控(2PSK)和多进制相位键控(MPSK)。该文主要介绍2PSK的调制与解调。在二进制数字调制中,当正弦载波的相位随二进制数字基带信号离散变化时,则产生二进制移相键控(2PSK)信号。通常用已调信号载波的 0?和 180?分别表示二进制数字基带信号的 1 和 0。 二进制移相键控信号的调制原理图如下所示。其中图3.20是采用模拟调频的方法产生2PSK信号,图3.21是采用数字键控的方法产生2PSK信号.本设计调制2PSK时采用的是键控法。 双极性st()不归零码型变et()乘法器2psk换 cos,tc 图 3.20 模拟调频法 开关电路et()2psk0cos,tc ,0移相180 st() 图3.21 键控法 2PSK信号的解调通常都是采用相干解调, 该文的解调器原理图如图 3.22 与2FSK解调原理相同。 17 调制信号模拟乘法器低通滤波器抽样判决基带信号 定时脉冲 压控振荡器 图3.22 2PSK解调原理框图 3.2.2 2PSK调制与解调电路的设计与仿真 2PSK调制电路采用键控法调制，而解调电路的设计是采用锁相环进行解调，2PSK信号通过锁相环最终解调出数字基带信号。2PSK基于multisim仿真的调制解调电路的整体电路设计图如图3.23所示: 图3.23 2PSK调制解调电路图 2PSK调制仿真图与解调后的仿真图如图3.24。 18the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 图3.24 2PSK调制解调电路图仿真结果 3.3 2ASK调制解调电路设计 3.3.1 2ASK调制解调电路设计原理 在二进制数字振幅调制中，载波的幅度随着调制信号的变化而变化，实现这种调制的方式有两种:(1)模拟相乘法:通过相乘器直接将载波和数字信号相乘得到输出信号，这种直接利用二进制数字信号的振幅来调制正弦载波的方式称为模拟相乘法，其电路如图3.25所示。在该电路中载波信号和二进制数字信号同时输入到相乘器中完成调制。(2)数字键控法:用开关电路控制输出调制信号，当开关接载波就有信号输出，当开关接地就没信号输出，其电路如图3.26所示。 开关电路et()st()2ASKcost,c乘法器et()2ask cos,tst()c 图3.25模拟相乘法 图3.26数字键控法 19 2ASK/OOK信号有两种基本的解调方法:非相干解调(包络检波法)和相干解调(同步检测法)，相应的接收系统如图3.27、图3.28所示。 图3.27非相干解调方式 图3.28相干解调方式 该文2ASK的调制方法采用的是模拟相乘法，而调制则采用的是相干解调。该文的2ASK解调原理框图3.29如下: 调制信号 模拟乘法器低通滤波器抽样判决基带信号 定时脉冲 压控振荡器 图3.29 2ASK解调原理框图 3.3.2 2ASK调制与解调电路的设计与仿真 2ASK调制电路采用键控法调制，而解调电路的设计是采用锁相环进行解调，2ASK信号通过锁相环最终解调出数字基带信号。2ASK基于Multisim仿真的调制解调电路的整体电路设计图如图3.30所示: 20the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 图3.30 2ASK调制解调电路图 图3.31 2ASK调制解调仿真图 21 3.4 解调结果分析 由于在解调2ASK、2FSK、2PSK时的数字基带信号都为1KHZ,而在解调时压控震荡器的中心频率都为1KHZ，所以该文中三个信号的解调电路都是一样的。锁相环鉴频电路环路输入频率跟随输出频率变化，即跟踪，实现环路锁定困难，会出现毛刺。低通滤波器输出的波形失真比较大，不过最后经过抽样判决电路整形后可以很好的解调出数字基带脉冲。 在解调设计选取参数时，发现低通滤波器中C2的值最影响波形的输出，以2FSK解调为例，一开始我在C2设为10nF，出来的波形如下图3.32: 图3.32 C2=10nF时的波形 可见解调出来的基带信号出现严重失真。后经过不断的尝试改变C2的值，最 终把C2的值设为100nF，终于解调出很好的数字基带信号如下图3.33: 22the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 图3.33 C2=100nF时的波形 23 总结 该文分别设计了2ASK、2PSK、2FSK的调制解调电路，其功能为数字基带信号经过调制输出一个模拟信号，然后用锁相环进行解调，最后采用Multisim软件进行仿真。在对2ASK、2FSK、2PSK解调时，低通滤波器输出的波形失真比较大，不过最后经过抽样判决电路整形后可以再生数字基带脉冲。 经过一个学期的时间，终于完成这次基于Multisim的锁相解调系统设计的毕业设计任务。我首先查阅了大量的书本资料，接着又上网搜集了许多有用信息，有时候为了找到一个合适的电路而苦恼，有时候又为取得一点成功而由衷的高兴。当最终的电路 方案 气瓶 现场处置方案 .pdf气瓶 现场处置方案 .doc见习基地管理方案.doc关于群访事件的化解方案建筑工地扬尘治理专项方案下载 设计出来以后，我请教了我的指导老师何老师及学的比较好的同学，他们的一个小小指点就给我们很大启示和灵感，对我的电路图提出了很多有价值的建议，在此对热心帮助我的老师和同学表示衷心感谢。 在此次毕业设计中，我充分体会到了熟练运用相关软件的重要性，不像以前做的课程设计，并没有多少工作在计算机里实现的，就仅仅画出了电路图之后用元器件在面包板上搭电路就行了。本次毕业设计都高度依赖计算机，从仿真到绘制原理图，再到参数调节，可以说每一步都很艰难，每一步都是我一步一个脚印结结实实踩下去的。通过毕业设计，我增强了对通信电子技术的理解，学会查寻资料)比较方案，学会通信电路的设计)计算;进一步提高分析解决实际问题的能力，创造一个动脑动手)独立开展电路实验的机会，锻炼分析)解决通信电子电路问题的实际本领，真正实现由课本知识向实际能力的转化;通过典型电路的设计与仿真加深对基本原理的了解，增强了实践能力。 24the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 参考文献 [1]( 熊伟 候传教. Multisim7电路设计及仿真应用[M]. 清华大学出版社，2005 [2]( 阳昌汉. 高频电子线路[M]. 高等教育出版社，2006 [3]( 吴运昌. 模拟集成电路原理与应用[M]. 华南理工大学出版社，2000 [4]( 沈伟慈. 通信电路[M]. 西安电子科技大学出版社，2004 [5]( 李争. 低噪声电荷泵锁相电路设计理论与技术，北京交通大学.硕士学位论文，2007 [6]( 郑继禹, 张厥盛, 万心平. 锁相环原理与应用[M]. 人民邮电出版社，1984 [7]( Floyd M.Gardner,Phase lock Techniques(Second Edition),Publication:New York,John Wiley,1979. [8]( Roland E.Best,Phase-locked Loops Design,Simulation and Application,清华大学出版社，2003 [9]( 张辉，曹丽娜.. 现代通信原理与技术[M]. 西安电子科技大学出版社，2002 [10](郑继禹, 张厥盛, 万心平. 锁相技术[M]. 西安电子科技大学出版社，1994 [11] 谢自美.电子线路综合设计.华中科技大学出版社,2006.6 [12] Best,Roland E.,Phase—Looked Loop Theory,Design and Applications McGRAW—Hill,1984 [13] 沈伟慈.通信电路.西安电子科技大学出版社，2004 25 附录:(外文翻译) Bridging the Gap between the Analog and Digital Worlds Most applications require the co-existence of analog and digital functionality, and the benefits of combining this functionality on a single chip are significant. Such mixed-signal integration, however, also presents significant challenges. Furthermore, digital and analog developments tend to evolve at differing rates, yet mixed-signal solutions for markets such as industrial, automotive and medical, must remain available over significant time periods. The latest mixed-signal semiconductor processes are helping to address some of these issues, and this article will look at some of the issues designers should consider when specifying integrated mixed-signal solutions. Mixed-signal solution for the real world System designers often partition the digital portion from the analog section of a given design for a variety of reasons: the availability of mixing components for the two technologies, the complexity of the digital design or again because of the existence of pure digital processing parts as standard products. Placing the analog elements in an integrated circuit definitively allows the system designer to optimize the costs of its entire module. This integration approach is usually difficult for advanced markets such as telecommunications or computers, but makes sense for more mature or conservative markets such as automotive, medical and industrial. For most of these mature market’s applications, digital functions are finding their way onto what once were pure analog designs. Adding digital functions to an analog design is helped in part by the development of new process technologies that can handle both short-channel, fast-switching digital transistors as well as high-voltage analog transistors. For example, AMI Semiconductor’s latest mixed-signal technology offers digital and analog integration capabilities on the same design platform. The I3T technology family is based on standard CMOS 0.35 µm, limiting the maximum gate voltage to 3.3 V. Some consider this technology outdated, from a pure digital designer’s point of view, but it is at the forefront for the automotive, industrial and medical markets. This list of optional features that enables the design of real SoCs includes high voltage 26the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 interfacing up to 80 V, microprocessing capabilities up to 32 bits, wireless capabilities up to 22.8 GHz, and dense logic design up to 15 K gates/mm. Beside these capabilities, NVM 2integration is possible: EPROM up to 4 Kbytes, Flash memory up to half a megabit or On-Time-Programmable (OTP) cells for application calibrations. The ability to integrate all these features on a chip gives the customer the possibility to be independent from the obsolescence of the stand-alone NVM market, which is more or less driven by the computer market. This advantage is quite relevant when we consider the cost of re-qualifying a module for the OEMs in automotive, for instance. It also makes sense when considering the long lifespan of the applications embedded into cars, the industrial environment or medical self-treatment devices where patient cost is an important consideration. Nevertheless bridging the gap from digital to analog on a single chip does not occur without issues. Clocking noise from high-speed digital circuits, for instance, often interferes with noise-sensitive analog functions. In addition, switching currents from high-power analog functions can interfere with low-voltage digital processors. The goal is to protect low-voltage transistors from the electric field effects of voltages that are 10 to 30 times higher. These important issues are not without solutions. For example, one of the latest releases in the I3T family, the I3T50 DTI, uses a deep trench isolation technique. This technique uses a series of isolating trenches that bury deep into the IC substrate; effectively creating on-chip “pockets” where noise and power supply parameters are carefully controlled. On top of its protection skills, the deep trench technology also helps to minimize die area by allowing dense packing of high-voltage analog pockets with low-voltage regions. You can obtain improvements in die area of 10 to 60 percent over designs that use standard junction isolation techniques. As mentioned earlier, the reason that system designers are using deep sub-micron technologies in those markets is often linked to the availability of devices in those technologies, not the complexity of the application itself. The complexity can be handled in many cases by an 8-bit microcontroller, or 32-bit for high-end applications. Products such as the 0.35 µm I3T are able to manage the integration at a reasonable cost. A typical application diagram of a real mixed-signal SoC is shown in Figure 1.9. 27 Basically, the chip integrates the system functionality from the sensor to the actuator, going through some digital processing. Conventional mixed-signal technology allows analog control and signal processing functions such as amplifiers, analog-to-digital converters (ADCs) and filters to be Figure 1.9 Mixed-signal SoC diagram combined with digital functionality such as microcontrollers, memory, timers and logic control functions on a single, customized chip. All signals that process an algorithm or arithmetic calculation are digital, so conversion of analog to digital signals is mandatory when submitting data for comparison or processing by via a microcontroller, while conversion from digital output signals to analog high-voltage signals is required to drive an actuator or a load. The most recent mixed-signal technology AMIS developed, significantly simplifies the implementation of such driver functionality by allowing much higher voltage functionality to be integrated into an IC alongside the relatively low voltages required for conventional mixed-signal functions. This high-voltage mixed-signal technology is particularly relevant to automotive electronics applications where higher voltage outputs — to drive a motor or actuate a relay — need to be combined with analog signal conditioning functions and complex digital processing. A growing trend in mixed-signal circuit design is to add some type of central processing circuit to the analog circuits. For many applications the suitable choice of processing intelligence is an 8-bit microcontroller core such as an 8051 or 6502. 8 bits remains the most popular choice as this type of SoC is not intended to replace complex high-end central microcontrollers but more decentralized or slave applications such as sensor conditioning circuitry with local (as close to the sensor as possible) simple intelligence to control relays or motors. An automotive example would be the lateral actuation of a car’s headlamps when the steering wheel is turned to improve the driver’s safety and improve field of vision. The sensor 2input would come from the steering angle via a serial link (most of the time with a LIN or IC protocol) and the SoC would be close to the motor with an on-board set of algorithms to command the motor’s movement. For higher end applications that require more calculation power, the move to ARM processors is possible. This creates a high-end solution (up to date for the mature markets) 28the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 which could last over the application’s lifespan because the microcontroller would be a small part of an integrated circuit that emulates the module’s functionalities. In order to understand how larger geometries can be better suited for some mixed-signal applications, one needs to understand all of the characteristics involved. Below we will discuss seven key characteristics, however this is by no means comprehensive. Gate and memory size in mixed-signal applications generally drive cost. Gate and memory size drive cost because most mixed-signal devices are core limited. This can be quite different than an all-digital circuit. Many times, the all-digital device will have so many I/Os that the number of pads on the device determines the periphery and therefore the area. This is rarely the case for mixed-signal devices. For the most part digital cells scale pretty closely to the expected area savings. One would expect a 0.25-micron cell to be 51 percent smaller than a 0.35-micron cell of equivalent function. This is illustrated by the following formula: 2(0.25)0.0625 Size Ratio ,,,51%20.1225(0.35) While this holds for digital cells we will see that analog cells are quite a different story. Therefore the amount of digital content (including memory) is the key in determining the best technology for the application. 2. Parasitic lessens as the geometry decreases. This is good news for both the digital and analog designer. Understandably this will translate into high bandwidths and data rates. While the magnitude of the parasitic capacitance per gate or resistance of the interconnection is most assuredly lower as geometry decreases, it is also less predictable. This can cause analog modeling problems and highlights the need for careful understanding of the parasitic. 3. The trans-conductance characteristic is the relationship between a drain current and the voltage across the gate and source. As the geometry decreases the trans-conductance gets higher. This is good news for both analog and digital domains in that smaller conductance interacts with capacitance to create 29 smaller bandwidths and therefore lower data rates. It is well understood that as geometry decreases the voltage limits of the device decrease as well. In the pure digital world this is beneficial in several ways: less power and less radiated emissions. The only downside is the need for multiple voltage rails on most digital circuits. In the analog domain, the power savings is there but reduced range of operation makes the design task harder. It is quite common for analog designers to bias their circuits at V + 2V Ton and V , (V + 2V). Unfortunately, the threshold voltage, V, does not scale with the ddTonT geometry. In other words, the operating range of voltages gets smaller as the technology shrinks. This means the analog portions of a circuit must be more tightly controlled which translates to larger, better matched transistors. 4. Channel resistance gets lower as the technology shrinks. While this may sound like a good thing, and for digital circuits it generally is, this translates to transistors with lower gain in the analog domain. Lower gain may mean more stages in the circuit. 5. The linearity of smaller geometries also becomes a factor in analog designs. Often non-linearity problems are solved by increasing the size of the circuit. An example of this can be seen in D/A and A/D converters where the performance of the converter is very much proportional to the size of the circuit. 6. Noise in circuits implemented in smaller technologies can cause problems for analog designers. This is usually worsened by the fact that there is usually a large and fast digital circuit that is generating much of the noise. The smaller operating voltage range works against the designer as well. Signal to noise ratio in the analog circuit gets worse because the signal levels go down but the noise levels may actually go up. 7. Analog circuit modeling in smaller geometries is problematic. Much of this is due to the lower levels of predictability and the nature of the parasitic. Some of it is due to the maturity of the technology as well. This, of course, will improve as the technology develops. 30the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 Because of these items listed above it is important to understand that as the process geometry shrinks, the analog actually gets bigger, and definitely harder. This has to be compensated by increasing the sizes of the transistors, capacitors and resistors used. Moving to smaller technologies should only be done when the performance requirements of the application demand it. For most mixed-signal SoC devices this will be driven by the digital gate count and the amount of memory in the design. Only when there is significant digital content should you consider smaller technologies. Conclusion The latest generation of mixed-signal process technologies has moved well into the deep sub-micron world where adding digital circuits and cores to an analog ASIC has become a cost-effective approach. With the addition of digital process capability and the digital processing horsepower that becomes available, many analog functions are being converted to digital signals earlier in the signal path. The advantage of this approach is that digital filters and digital control elements are not sensitive to drift inaccuracies caused by aging, process changes or temperature changes. The result is a much more robust design than an analog-only approach. 中文译文: 桥接模拟与数字世界之间的鸿沟 大多数应用程序要求模拟和数字功能的并存，把此功能结合在单一芯片上的好处是 31 很明显的。然而，这样的混合信号集成也向人们提出了重大挑战。此外，数字和模拟功能往往以不同的速度进行发展，但混合信号在如工业，汽车和医疗行业的解决方案在关键时期必须保持是能用的。最新的混合信号半导体工艺正在着力解决这些问题，本文将着重于当具体指定集成混合信号解决方案时设计者应考虑的一些问题。 在现实世界中混合信号的解决方案 系统设计人员经常从一个给定设计的模拟区域中进行数字区域的分区，这样做有多种原因:这两种技术混合组件的可用性，数字化设计的复杂性或作为 标准 excel标准偏差excel标准偏差函数exl标准差函数国标检验抽样标准表免费下载红头文件格式标准下载 产品的纯数字处理部分的存在。在集成电路里配置模拟器件确实能让系统设计师降低整个模块的成本。 此集成方法在诸如信或计算机等先进领域通常是难以实现的，但对于更成熟的或传统的市场，如汽车，医疗和工业是有实际意义的。对于这些成熟市场的大部分应用，数字化功能研究者正在寻找曾是纯模拟设计的方法。添加数字功能到模拟设计，部分上帮助了开发新的工艺技术，该工艺可以处理短信道，快速转换数字晶体管和高电压模拟晶体管。例如，AMI半导体公司最新的混合信号技术提供了在相同的设计平台上的数字和模拟集成功能。 I3T技术系列是基于0.35微米的补充金属氧化物半导体(晶体管型)的。有些人认为从一个纯粹的数字设计师的角度来看，这项技术已经过时，但它却是处在汽车，工业和医疗行业的最前沿的技术。 这种可选特性使真正的片上系统的设计能实现以下功能，包括高电压接口可达80伏，微处理性能可达32位，无线性能可达2.8千兆/赫兹，以及复杂逻辑设计可达每平方15 000个门电路。除了这些功能之外，使非易失性存储器的融合成为可能:电可擦可编程只读存储器可达4 千字节，快闪记忆体高达半兆位或生产一次性编程(OTP)的应用程序。能够在一个芯片上集成所有这些功能使客户有可能免受独立非易失性存储器市场过时的影响，该市场或多或少会受电脑市场的驱动。例如，当我们考虑汽车原始设备制造商的重新排位模块的成本时，这样做的好处是非常明显的。当考虑嵌入到汽车的应用模块的寿命长度时，当病人在工业环境下或医学自我治疗设备上的花费是一个重要的考虑因素时，这也是很有意义的。 不过从数字到模拟的鸿沟缩小在单一芯片上时必定会有问题发生。例如，来自高速数字电路上时钟的噪声会干扰模拟功能的敏感区域。此外，高功率模拟功能的开关电流可干扰低压数字处理器。我们的目标是保护低压晶体管电场效应的电压从10至高于30倍变化。 这些重要的问题不是没有解决方案的。例如，一个I3T家庭使用的最新版本，I3T50的贸工部，使用的是深沟槽隔离技术。这种技术采用了一系列深入到IC基板的隔离壕沟，有效地创建了片上的用于细致地控制噪声和电源参数的“口袋”。 32the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 深槽技术除具保护功能外，也有助于减少晶片面积，方法是应用低压地区的高电压模拟口袋的密集包装工艺。可以通过使用标准结隔离技术获得超过预计的10,至60,的使用面积。 如前所述，系统设计师使用这些市场中的深亚微米技术的原因是常连接这些技术的设备的可用性，而不是应用程序本身的复杂性。在许多情况下，由一个8位微控制器，或32位高端应用程序可解决应用程序本身的复杂性。作为0.35微米I3T的产品是能够管理一个成本合理的集成环境的。如图1.9所示为一个现实的混合信号片上系统的典型应用框图。 图1.9 混合信号片上系统的框图 基本上，该芯片通过一些数字化处理，集成了从传感器到执行机构系统的功能。传统的混合信号技术允许如放大器，模数转换器(ADC)和过滤器等模拟控制和信号处理功能与如微控制器，存储器，定时器和在一个单一的、定制的芯片上的逻辑控制功能等数字功能相结合，处理算法或数学计算的所有信号都是以数字方式进行的，所以当通过微控制器提交用于比较或处理的数据时，所有信号的模拟向数字转换都是强制性的。但是模拟高压信号转换成数字输出信号时需要驱动器或负载。最近期的混合信号技术AMIS的发展，大大简化了这种驱动功能的实施。该技术是通过允许更高电压功能集成到具有要求相对较低电压的传统混合信号功能的一个IC上。这种高压混合信号技术与汽车电子应用尤为相关，该领域需要更高的输出电压，用于驱动电机或继电器，将模拟信号调节功能和复杂的数字处理结合起来。 混合信号电路设计的发展趋势是添加一些中央处理电路的类型到模拟电路。对于许多应用程序，如8051或6502的8位微控制器核是智能处理器的合适选择。 8位仍然是最流行的选择，因为片上系统的这种类型并不是要取代复杂的高端中央微处理器，而是将更多的权力下放或控制如在本地的(尽可能接近传感器)传感器调制电路的简单智能的应用去控制继电器或马达。一个汽车的例子是当转动方向盘以提高驾驶员的安全和改善视野时，车的大灯会横向发光。当通过串行链路(在执行LIN或I2C 协议 离婚协议模板下载合伙人协议 下载渠道分销协议免费下载敬业协议下载授课协议下载 的大部分时间)时，传感器的输入来自转向角传感器输入，片上系统将与具有控制电机运动的一套板上算法相近。 33 对于需要更多计算能力的高端应用，转移到ARM处理器是有可能的。这将创建一个高端的解决方案(最新的成熟市场)，这方案持续时间将超出应用程序的寿命，因为微控制器将是一个具有模拟模块功能的集成电路的一小部分。 为了了解多大的几何区域能更适合一些混合信号应用，人们需要了解其涉及的所有特征。下面我们将讨论七个关键特征，然而，这绝对不是全面的。 1(混合信号应用器件的门和内存大小影响成本。 门和内存大小影响成本是因为大多数混合信号器件的内核是被限制的。这与全数字电路是大不相同的。很多时候，全数字化的设备将有很多的输入输出设备，这些设备上的垫的数量决定了外围数量，也因此决定了区域大小。这对混合信号设备来说是很少见的情况。对于数字单元块中的大部分区域来说，能够非常接近预期的节约面积。人们期望，0.25微米的单元能够比具有等效功能的0.35微米单元小51,。如下列公式所示: 2(0.25)0.0625 比例大小 ,,,51%2(0.35)0.1225 即使这归数字单元持有，但我们看到的模拟单元将是一个完全不同的区域。因此，数字内容(包括内存)的数量对确定应用程序的最好技术是很关键的。 2(因为几何寄生而减缓降低。 这对数字和模拟设计师来说都是好消息。这转化为高带宽和高数据传输速率是可以理解的。虽然每门电路或互连电阻的寄生电容的大小在几何跌幅里是最稳较低的，但它也较难预测。这可能会导致模拟建模问题和加强对仔细了解寄生的需要。 3(跨导的特点是跨栅极和源极之间的漏电流和电压的关系。 因为几何降低而跨导越高。这对模拟和数字域都是好消息，在域里小电导与电容相互作用以创建更小的带宽，因此也降低数据率。 众所周知，几何降低也能降低设备的电压限。在纯数字的世界，有几种有益的方式:降低功率和减少辐射。唯一的缺点是在大多数数字电路里需要多个电压轨。在模拟域，积蓄力量是有，但操作范围的减少使设计任务更加艰难。对模拟设计师来说，偏置电路在V + 2V和V(V + 2V)之间是相当普遍的。不幸的是，阈值电压V与几何规TonddTonT模不匹配。换句话说，因为工艺减缩使得电压的操作范围变小。这意味着电路的模拟部分必须更严格的控制，使其转化为更大型、更匹配晶体管。 34the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 4(因为工艺减缩使通道电阻更低。 虽然这听起来像是一件好事，而且对于数字电路，在模拟域，它一般能将晶体管增益降低。但在电路中，低增益可能意味着多个阶段。 5(更小几何尺寸的线性也成为模拟设计中的一个考虑因素。 通常非线性问题都通过电路规模的增长而解决的。从这样的一个例子可以看出，对于D / A和A / D转换器，其性能对电路的规模非常重要。 6(对模拟设计者来说，以更小规模工艺实现电路而产生的噪声能够引发问题。 通常由于产生更多噪音的大型和高速数字电路使情况更糟。较小的工作电压范围，对设计师也是挑战。在模拟电路，由于信号电平降低，信噪比变得更糟，但噪音电平实际上可能上升。 7(更小规模的模拟电路模型是有问题的。 这在很大程度上是由于较低水平的可预测性和寄生的性质，也有些是由于技术的成熟引起的。这当然随着技术的发展而提高。 因为上面列出的这些项目对理解几何过程缩小是很重要的，实际上，模拟规模变得更大，更难。这必须通过增加要使用的晶体管，电容器和电阻的大小来补偿。移动较小的技术时，只有当应用程序的性能有要求时，才转向使用小规模工艺。对于大多数的混合信号片上系统器件，将受设计中数字电路门数和内存容量的驱动。只在有重要的数字内容，你才应该考虑小型化工艺。 结论 新一代的混合信号处理技术已远远进入深亚微米世界，在这世界里，添加数字电路和内核到模拟专用集成电路已经成为一种成本效益法。 随着数字化进程能力的增强和数字化处理马力逐渐变得易于使用，早在信号路径中，许多模拟功能被转换成数字信号。这种方法的优点是，数字滤波器和数字控制元件 35 对由老化引起的漂移误差，工艺变化或温度变化已经再不敏感。其结果是产生一个比模 拟方法更健壮的设计。 Phase-locked loop A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. This circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop. Frequency is the derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input 36the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis. Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to recover a signal from a noisy communication channel, generate stable frequencies at a multiple of an input frequency (frequency synthesis), or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz. Practical analogies Automobile race analogy For a practical idea of what is going on, consider an auto race. There are many cars, and each of them wants to go around the track as fast as possible. Each lap corresponds to a complete cycle, and each car will complete dozens of laps per hour. The number of laps per hour (a speed) corresponds to an angular velocity (i.e. a frequency), but the number of laps (a distance) corresponds to a phase (and the conversion factor is the distance around the track loop). During most of the race, each car is on its own and is trying to beat every other car on the course, and the phase of each car varies freely. However, if there is an accident, a pace car comes out to set a safe speed. None of the race cars are permitted to pass the pace car (or the race cars in front of them), but each of the race cars wants to stay as close to the pace car as it can. While it is on the track, the pace car is a reference, and the race cars become phase-locked loops. Each driver will measure the phase difference (a distance in laps) between him and the pace car. If the driver is far away, he will increase his engine speed to close the gap. If he's too close to the pace car, he will slow down. The result is all the race cars lock on to the phase of the pace car. The cars travel around the track in a tight group that is a small fraction of a lap. Clock analogy 37 Phase can be proportional to time, so a phase difference can be a time difference. Clocks are, with varying degrees of accuracy, phase-locked (time-locked) to a master clock. Left on its own, each clock will mark time at slightly different rates. A wall clock, for example, might be fast by a few seconds per hour compared to the reference clock at NIST. Over time, that time difference would become substantial. To keep his clock in synch, each week the owner compares the time on his wall clock to a more accurate clock (a phase comparison), and he resets his clock. Left alone, the wall clock will continue to diverge from the reference clock at the same few seconds per hour rate. Some clocks have a timing adjustment (a fast-slow control). When the owner compared his wall clock's time to the reference time, he noticed that his clock was too fast. Consequently, he could turn the timing adjust a small amount to make the clock run a little slower. If things work out right, his clock will be more accurate. Over a series of weekly adjustments, the wall clock's notion of a second would agree with the reference time (within the wall clock's stability). An early mechanical version of a phase-locked loop was used in 1921 in the Shortt-Synchronome clock. Structure and function Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. Both analog and digital PLL circuits include four basic elements: ?Phase detector, ?Low-pass filter, ?Variable-frequency oscillator, and ?feedback path (which may include a frequency divider). Performance parameters ?Type and order 38the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 ?Lock range: The frequency range the PLL is able to stay locked. Mainly defined by the VCO range. ?Capture range: The frequency range the PLL is able to lock-in, starting from unlocked condition. This range is usually smaller than the lock range and will depend e.g. on phase detector. ?Loop bandwidth: Defining the speed of the control loop. ?Transient response: Like overshoot and settling time to a certain accuracy (like 50ppm). ?Steady-state errors: Like remaining phase or timing error ?Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple. ?Phase-noise: Defined by noise energy in a certain frequency band (like 10kHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth, etc. General parameters: Such as power consumption, supply voltage range, output amplitude, ? etc. Applications Phase-locked loops are widely used for synchronization purposes; in space communications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency. Other applications include: ?Demodulation of both FM and AM signals ?Recovery of small signals that otherwise would be lost in noise (lock-in amplifier) 39 ?Recovery of clock timing information from a data stream such as from a disk drive ?Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships ?DTMF decoders, modems, and other tone decoders, for remote control and telecommunications Clock recovery Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator. Typically, some sort of redundant encoding is used, such as 8b/10b encoding. Deskewing If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a delay-locked loop (DLL) is frequently used. Clock generation Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz. Spread spectrum 40the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on the emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast FM radio channels, which have a bandwidth of several tens of kilohertz. Clock distribution Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched. PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference. Jitter and noise reduction One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset (also called the steady-state phase error). The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible. 41 Phase noise is another type of jitter observed in PLLs, and is caused by the oscillator itself and by elements used in the oscillator's frequency control circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic (ECL) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic (TTL) or CMOS. Frequency Synthesis In digital wireless communication systems (GSM, CDMA etc.), PLLs are used to provide the local oscillator for up-conversion during transmission and down-conversion during reception. In most cellular handsets this function has been largely integrated into a single integrated circuit to reduce the cost and size of the handset. However, due to the high performance required of base station terminals, the transmission and reception circuits are built with discrete components to achieve the levels of performance required. GSM local oscillator modules are typically built with a frequency synthesizer integrated circuit and discrete resonator VCOs. Frequency synthesizer manufacturers include Analog Devices, National Semiconductor and Texas Instruments. VCO manufacturers include Sirenza, Z-Communications, Inc. (Z-COMM). Phase-locked loop block diagram A phase detector compares two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a VCO which creates an output phase. The output is fed through an optional divider back to the input of the system, producing a negative feedback loop. If the output phase drifts, the error signal will increase, driving the VCO phase in the opposite direction so as to reduce the error. Thus the output phase is locked to the phase at the other input. This input is called the reference. Analog phase locked loops are generally built with an analog phase detector, low pass filter and VCO placed in a negative feedback configuration. A digital phase locked loop uses a digital phase detector; it may also have a divider in the feedback path or in the reference path, or both, in order to make the PLL's output signal frequency a rational multiple of the reference frequency. A non-integer multiple of the reference frequency can also be created by replacing 42the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 the simple divide-by-N counter in the feedback path with a programmable pulse swallowing counter. This technique is usually referred to as a fractional-N synthesizer or fractional-N PLL. The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. If the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator so that it speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the control voltage to slow down the oscillator. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs. Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system. 43 中文译文: 锁相环 一个锁相环或锁相回路(PLL)是一个产生相位与输入“参考”信号相位相关的输出信号的相位控制系统。它是一种由可变频率振荡器和相位检测器组成的电子电路。此电路输入信号的相位与它的输出振荡器产生的信号的相位相比较，以调整其振荡器的频率保持相位匹配。来自相位检测器的信号用于控制反馈环路中的振荡器。 频率是相位的阶段衍生。保持锁相阶段的输入和输出相位意味着保持锁相阶段的输入和输出频率。因此，锁相环可以跟踪输入信号频率，或者可以产生是输入频率的倍数的频率。前者用于解调，后者用于间接频率合成。 锁相环被广泛运用在广播，通信，计算机及其他电子领域。它们可以在噪音信道恢复信号，产生多个输入频率的稳定频率(频率合成)，或在如微处理器等的数字逻辑设计中分布时钟定时频率。因为单一的集成电路可以提供一个完整的锁相环模块，所以该技术被广泛应用于现代电子设备中，实现输出频率从一赫兹到千兆赫兹。 实践类比 汽车比赛的比喻 对于一个正在进行的实际的想法，类比于汽车比赛。有很多车，每个人都希望尽可能快的在轨道绕行。每圈对应一个完整的周期，每辆车将每小时完成几十圈。每小时的圈数(速度)对应角速度(即频率)，但轨道(距离)对应相位(转换因子是围绕轨道环的距离)。 44the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 在比赛期间，每辆车在自己的轨道上，并试图击败在场上的其他汽车，每辆汽车的位置不同。 然而，如果发生意外，一辆开路车以安全的速度出来。没有赛车允许开路车(或在他们面前的赛车)通过，但每个赛车要尽可能接近开路车。即使在赛道上，开路车只是一个参考，赛车成为锁相环。每个司机将测量他和开路车之间的相位差(圈中的距离)。如果司机发现很远，他会增加他的发动机转速，以缩小差距。如果他离开路车距离太近，他将减速。结果是所有赛车与开路车相位锁定。车在一圈的一个小部分绕行。 时钟的比喻 相位时间成正比，所以相位可以是一个时间差。钟表以不同程度的精确性，相位锁定于(锁定时间)主时钟。 离开自己的位置，每个时钟将会以略有不同的比率记录时间。例如，墙上的时钟与NIST的参考时钟相比，可能每小时快几秒钟。随着时间的推移，将成为巨大的时间差。 为了保持时钟同步，主人每星期将挂钟时间与更精确的时钟比较(相位比较)，将他的时钟校准。除此之外，挂钟与参考时钟将以每小时相同的秒数继续偏离。 有些钟表有计时调整(快慢控制)。当主人将他的挂钟时间与参考时间相比时，他发现，他的时钟太快了。因此，他可以打开计时机调整器进行微调使时钟运行速度稍慢。如果操作顺利实施，他的时钟将更加准确。通过每周一系列的调整，挂钟的秒数将与参考时间一致(在挂钟的稳定能力之内)。 锁相环的较早机械版本在1921年用于肖特时钟同步。 结构和功能 锁相环机制可以实现模拟或数字电路。这两种实现使用相同的基本结构。模拟和数字锁相环电路都包括四个基本要素: •相位检测器， •低通滤波器， •可变频率振荡器， •反馈路径(其中可能包括一个分频器)。 45 性能参数 •类型和顺序 •锁定范围:锁相环的频率范围能够保持锁定，主要是由VCO的范围限定的。 •捕获范围:锁相环的频率范围从解锁的条件出发能够进行锁定。这个范围通常是小于 锁定范围的，并取决于相位检测器等。 •环路带宽:定义控制回路的速度。 •瞬态响应:如过冲和稳定时间以达到一定的精度(如50PPM)。 •稳态误差:如其余相位或计时误差。 •输出频谱纯度:如从某一个VCO调谐电压纹波产生的边带。 •相位噪声:噪声能量定义在某个频段(如10kHz的载波偏移)。高度依赖VCO相位 噪声，锁相环带宽等。 •通用参数:如功耗，电源电压范围，输出幅度等。 应用 锁相环广泛用于同步，用于相干解调和阈值的扩展空间通信，位同步，符号同步。锁相环也可用于解调调频信号。在无线电发射器，锁相环用于合成参考频率整数倍的新频率，和参考频率的稳定性相同。 其他应用包括: •FM和AM信号的解调。 •恢复小信号，否则就会使信号淹没于噪声中(锁相放大器)。 •如从一个磁盘驱动器的数据流中恢复时钟计时信息。 •微处理器中的时钟乘法器，允许内部处理器元素的运行速度比外部连接器快，同时 保持精确的时序关系。 •DTMF的解码器，调制解调器，其他音解码器，用于远程控制和通讯。 时钟恢复 一些数据流，尤其是被发送的高速串行数据流(如来自磁盘驱动器磁头的原始数据流)没有同步时钟。接收器从一个大致参考频率出发产生时钟，然后与锁相环数据流中的时钟转换为相位一致的。这一过程被称为时钟恢复。为了这个方案去工作，数据流必须有足够频繁的转换来纠正任何锁相环振荡器的漂移。通常情况下，使用一些如8b/10b编码的冗余编码。 46the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 抗扭曲 如果时钟与数据并行发送，时钟可以用于数据采样。因为时钟在驱动采样数据的触发器之前必须接收和放大，这将导致在检测时钟边沿和接收数据窗口之间的有限，过程，温度和电压依赖性的延迟。这个延迟限制发送数据的频率。消除这种延迟的方法之一，是包括在接收端纠偏锁相环。因此，每个数据触发器的时钟与接收时钟相匹配。这种类型的应用程序是锁相环的一种特殊形式，称为延迟锁相环(DLL)，是经常用的。 时钟发生器 许多电子系统包含以数百兆赫兹运作的各种处理器。通常情况下，时钟给这些处理器提供来自锁相环的时钟发生器，它乘以一个低频率的参考时钟(通常是50或100 MHz)以达到处理器的工作频率。乘法因子可以很大以防工作频率是几千兆赫兹和参考晶体仅仅是几十或几百兆赫兹。 扩频 所有电子系统都会产生一些不需要的无线电频率能量。各监管机构(如美国FCC)提出限制排放能源和由它造成的任何干扰。发出的噪音一般出现在尖锐的谱峰(通常是在该设备的工作频率和几个谐波中)。系统设计师可以使用扩频锁相环通过在较大部分的频谱上传播能量而干扰高Q接收机。例如，通过改变运行频率的少量升降(约1,)，在数百兆赫兹运行的设备可以传播其干扰，甚至可以越过数兆赫兹的频谱，从而大大降低了有几十千赫兹的带宽的调频广播频道的可见噪音量。 时钟分配 通常情况下，参考时钟进入芯片和驱动器锁相环(PLL)，然后驱动系统的时钟分布。通常时钟分配平衡，使时钟在每一个端点同时到达。这些端点之一是锁相环的反馈输入。 锁相环的功能是比较分布时钟和传入的参考时钟的，相位和输出频率一直变化直到基准和反馈时钟的相位和频率匹配。 锁相环无处不在，它们跨越区域调整系统中的时钟，，以及在单个芯片的一小部分的时钟。有时参考时钟实际上不是一个纯粹的时钟，而是具有足够转换的数据流，转换是锁相环能够从数据流中恢复定期时钟。有时参考时钟与通过时钟分配的驱动时钟的频 47 率相同，其他时间的分布时钟会有多个合理的参考时钟。 减少抖动和噪声 锁相环的一个可取性质是参考和反馈时钟边沿非常密切的协调起来。当锁相环被锁定时，在两个信号的相位之间的平均时间差被称为静态相位偏移(也称为稳态相位误差)。这些相位之间的差值被称为跟踪抖动。理想的情况下，静态相位偏移应该是零，跟踪抖动尽可能低。 相位噪声是观测锁相环的抖动的另一种类型，该抖动由振荡器自身和使用的振荡器频率控制电路元件引起的。有些工艺在这方面的性能比别的工艺好。最好的数字锁相环与发射极耦合逻辑(ECL)器件构建在一起，以高功耗为代价。为了保持锁相环电路低相位噪声，最好是避免如晶体管 —晶体管逻辑(TTL)或CMOS等饱和的逻辑系列。 频率合成 在数字无线通信系统(GSM，CDMA等)中，锁相环为传输过程中上转换和接收过程中下转提供本地振荡器。在大多数蜂窝手机里，此功能已在很大程度上被集成到一个单一的集成电路，用以降低手机的成本和规模。然而，由于基站终端所需的高性能，传输和接收电路用分立元件搭建以实现所需的性能水平。 GSM本地振荡器模块通常内置频率合成器集成电路和分立的谐振器VCOs。频率合成器制造商包括ADI 导体和德州仪器。VCO的制造商包括Sirenza公司，Z-Communications公司(Z-COMM)。 锁相环框图 相位检测器比较两个输入信号，并产生一个成正比相位差的错误信号。错误信号通过低通滤波并用来驱动创建输出相位的VCO。输出通过可选分频器回送到系统的输入，产生一个负反馈回路。如果输出相位漂移，误差信号就会增加，相反方向驱动VCO相位以减少错误。因此，输出相位被锁定在其他输入相位。这输入被称为参考输入。 模拟锁相环一般用模拟相位检波器建立，低通滤波器和压控振荡器置于一个负反馈配置器。数字锁相环采用了数字鉴相器，在反馈路径或参考路径里它也可能有分频器，为了使锁相环的输出信号频率的参考频率有合理的增大，非整数倍的参考频率也可以由替代具有脉冲吞吐可编程计数器的反馈回路里的N分频计数器创建。这种技术通常被称为小数N分频合成器或锁相环。 振荡器产生一个周期的输出信号。假设最初的振荡器是以几乎相同频率的信号作为参考信号。如果相位落后于来自参考振荡器的相位，鉴相器控制振荡器的电压改变以便 48the fruits of reform and development. Four, strengthen organizational leadership,nsure that the "two" education carried out f keys", gather the most widelyForce, drawing maximum concentric circles, unite and lead the people to create more and betterg the Internet and doing mass work well, follow the mass line, "face to face", and "key oto organize the masses to the masses. To insist on effective methods of mass work in traditional, more should be good at usin 兰州理工大学毕业设计 加速。同样，如果相位超出参考相位，鉴相器会改变控制电压减缓振荡器的频率。由于最初的振荡器频率可能远远高于参考频率，实用鉴相器也可能响应频率的差异，所以增加允许输入的锁定范围。 根据不同的应用，无论是控制振荡器的输出，或是控制到达振荡器的信号，提供有用的锁相环系统的输出。 致谢 行文至此，我的这篇论文已接近尾声;岁月如梭，我四年的大学时光也即将敲响结束的钟声。离别在即，站在人生的又一个转折点上，心中难免思绪万千，一种感恩之情油然而生。生我者父母。感谢生我养我，含辛茹苦的父母。是你们为我的学习创造了条件;是你们一如既往的站在我的身后默默的支持着我。没有你们就不会有我的今天。谢谢你们，我的父亲母亲～ 在这四年中，老师的谆谆教导、同学的互帮互助使我在专业技术和为人处事方面都得到了很大的提高。感谢湖南商学院在我四年的大学生活当中对我的教育与培养，感谢湖南商学院信息学院的所有专业老师，没有你们的辛勤劳动，就没有我们今日的满载而归，感谢大学四年曾经帮助过我的所有同学。在制作毕业设计过程中我曾经向老师们和同学们请教过不少的问题，。在此我向你们表示最衷心的感谢。 最后尤其要感谢我们的指导老师何老师和王老师对我悉心的指导，感谢何老师和王老师在做毕业设计过程中给我的帮助。正是有了何老师的热情解答、指导以及王老师细心的帮我审查文档才使我的毕业设计能较为顺利的完成。在设计过程中所学到的东西是这次毕业设计的最大收获和财富，使我终身受益。 49