3D IC 的TSV集成–现有工艺及未来展望

13DICIntegrationwithTSV–CurrentProgressandFutureOutlookShanGao,Dim-LeeKwongInstituteofMicroelectronics,A*STAR(AgencyforScience,TechnologyandResearch)Singapore9September,2010SEMI大半导体产业网www.semi.org.cnƒIntroductionƒ3DIC integration and main applicationƒProducts to be commercializedƒTechnologies and key challenges for 3DIC with TSVƒCurrent progress in 3D TSV developmentƒOutlookOverviewSEMI大半导体产业网www.semi.org.cnWhy3DIC?-Pre-positioningStrategyforMorethanMooreENABLERDiscrete2-DIntegrationHighDensityMemoryLowPowerLogicHighPerformanceLogicHighSpeedMemoryRadioPhotonicsPowerRegulatorSensorsPhotonicsSensorsI/OHighDensitymemoryHigh SpeedMemoryHigh Perf.LogicLow PowerLogicPowerReg.Radio3-DIntegrationSEMI大半导体产业网www.semi.org.cn3DTSVApplicationStatusSEMI大半导体产业网www.semi.org.cn3DTSVMarketDriversSEMI大半导体产业网www.semi.org.cn•Logic + memory application to drive >30% of the 3D TSV packagingmarket by 2015•CIS, MEMS, SENSOR to drive 30% of market share•Memory + Memory stacking combined DRAM & NAND drive 20%3DTSVPackagingMarketForecastSEMI大半导体产业网www.semi.org.cnSubstrate•Mechanical simulation for low stress•Thermal simulation for low chip temperature•Electrical simulation for Signal Integrity (SI), Power Integrity (PI)•Electrical test, Reliability test and FMEAModeling&CharacterizationMicro-bumpingWaferLevelRDLWaferThinningTSVFabricationC2W/C2CBondingCu-CuWaferBonding•Temporary bonding/debonding adhesive•Plating chemicals for high AR (>10) TSV filling•CMP slurries for high removal rate (5µm/min) •Low curing temperature dielectric (< 180ºC)•Small gap wafer level underfills (<10µm)•Low stress/warpage wafer level encapsulantsDevelopmentofMaterials3DICStructure3DICTechnologyDevelopmentinIMESEMI大半导体产业网www.semi.org.cnVia‐First(TSV Interposer)Via‐First(TSV Interposer)Via‐Middle(Logic, Memory)Via‐Middle(Logic, Memory)Via‐Last (B2T)(CIS, Memory)Via‐Last (B2T)(CIS, Memory)TSV ETCHTSV PhotoFEOLTSV CLEANTSV CVDTSV PVDTSV ECPTSV CMPTSV ETCHTSV PhotoTSV CLEANTSV CVDTSV PVDTSV ECPTSV CMPTSV ETCHBOND & THINTSV LTCVDCONTACT ETCHTSV PHOTOTSV PVDTSV ECPDEBONDBEOLSiRDL & BUMPTSV CLEANBOND & THINBS VIA REVEALBS RDL/BUMPCHIP STACKASSY & TESTFEOLBEOLSiFEOLBEOLSi3DTSVIntegrationProcessFlowSEMI大半导体产业网www.semi.org.cnKey challenges:•Conformal dielectric step coverage and Barrier / Cu seed step coverage•Void free electroplating, Cu ProtrusionOn‐going Research:•Via size 2um/AR10, < 10um pitchDescriptionEstablished in IMEDielectric coverage~10% for AR10Barrier metal and seed step coverage~5%  for AR10Electro‐plated viaØ5um/AR10, 15um pitchWafer / TSV  thickness50umVia etchingBarrier/Seed/Cu FillingCu CMPDielectric LayerTSVFabricationProcessSEMI大半导体产业网www.semi.org.cnTSVFabricationProcessChallengesSEMI大半导体产业网www.semi.org.cn•Cu protrusion (hundreds to thousands Å) may attack M1 and ILD layer•Double CMP and Heat Treatment method have been reported for via‐middle process –but these are typically high temperature processes •Low temperature ILD process for Cu BEOL can minimize Cu protrusion for interposer application –process development neededProcessChallengess–CuProtrusionSEMI大半导体产业网www.semi.org.cn•Need carrier wafer for chip bonding•Lower density integration•No need carrier wafer•High density integration•Work only between 1stand 2ndwafer bonding only, the 3rdwafer stack back to “Face to back”Interconnection–Cu-CuWaferBondingOn‐going Research: •Cu‐Cu W2W bonding: Temperature 300oC, Pitch 15umSEMI大半导体产业网www.semi.org.cnKey challenges:•Low bonding temperature, Fine pitch and High reliability Cu pillar + Thin solder layerMicro‐bumpIMC based interconnectionDescriptionSpecificationBonding TemperatureMicro‐bump180°CCu pillar with lead free solder260°CBump materialAuInSn, InSnBump Pitch25umSi ChipSi chipOn‐going Research: •Composite joint for C2C, C2W bonding,  Bump Pitch: 15umInterconnection-FinePitchMicro-BumpSEMI大半导体产业网www.semi.org.cn3M –Laser released adhesiveBSI –Thermal plastic adhesiveTMAT –Mechanically released adhesiveTOK ‐Chemical released adhesiveThinWaferHandling-TemporallyBonding/DebondingSEMI大半导体产业网www.semi.org.cnKey challenges:•Multiple chip stacking with low stand‐off interconnection•Low warpage wafer level encapsulationOn‐going Research: •C2W bonding : 10 chips•Interconnection: RDLless and Bumpless Micro‐jointC2C & C2W BondingWafer Level UnderfillingWafer Level MoldingChuckBase WaferBase WaferDescriptionSpecificationBonding method (C2W, C2C)Thermo‐compressionStand‐off Low Temperature Solder (180°C)5umCu pillar with leadfree solder (260°C)15umChipStackingProcessSEMI大半导体产业网www.semi.org.cnSubstrateReliabilityChallengesStress concentration, Cracks  around TSVsIMC, fatigue failure of microbumpsMoisture induced delamination, corrosionHot Spot in Chip & Thermal ManagementElectromigration in Microbumps & TSVsSEMI大半导体产业网www.semi.org.cn[]110x[]001'y[]101y[]010'xR1R4R3R2Stress sensor for process development Comb & Triple Tracks Sensor for moisture ingress & corrosionn-wellpsubstrateN++P+implantn-wellN++P+implantThermal chip designCrack sensor chip designSensorChipDesignForReliabilitySEMI大半导体产业网www.semi.org.cnIntegrated single or two phase liquid cooling for high power chips in 3DIC‐Chip carrier with fluidic and electrical paths by  C2C bonding‐3D electrical and fluidic interconnection using silicon interposerHeat ExchangerMini PumpPCBSilicon carrierFluidic adaptorTSVElectrical I/OFluidic InletMicro ChannelsSeal ring0.010.020.030.040.050.060.070.080.090.0100.0110.00102030405060708090100ChipHeatDissipation(W/cm2)Avg.ChipTemperature(°C)Chipwith400Bumps(MeasuredData)Chipwith2500Bumps(SimulationData)AvgCoolingLiquidTempIntegratedCoolingSolutionOn‐going Research: •Two Phase Boiling CoolingSEMI大半导体产业网www.semi.org.cnIdentify & establishment –300mm line through consortium efforts1stYearProcess & Characterization studies on 300mm wafer2ndYear3rdYearPhase‐1 (18 months)Phase‐2 (18 months)Process & Reliability studiesApplication: Mobile Devices•One Logic Chip & Six Memory ChipsConsortium Deliverables:•Phase‐1: Design Guidelines & Process Development•Phase‐2: Full Functional Device DemonstrationDesign & Modeling StudiesSingapore3DTSVConsortiumSEMI大半导体产业网www.semi.org.cn201020112012201320143DStacking(C2C,C2W,W2W)Design,Simulation&CharacterizationWaferLevelRDL&Micro-bumpingTSVFabricationWaferHandling&ThinningHighfreq.(upto80GHz)TSVElectricalCharacterization(Φ<2um,D<20um)Thermo-MechanicalsimulationDynamictwo-phaseflowsimulationViaLastΦ5um,D50umSub-micronViaΦ1um,D10umViaMiddleΦ2um,D20umC2C/C2Wbondingwithsolder(10chips)W2WCu-CuBonding(Padsize:5um,pitch:10um,Bondingtemp.:<200◦C)12”50umthickness12”20umthickness12”10umthickness8”50umthicknessCuInSnsolder:180◦C,Size:8um,Pitch:15umLine/Space:10um/10umLine/Space:15um/15umSensor+MixedSignalPMIC+Memory+RFICSensor+Memory+FPGAIME3DICDevelopmentRoadmapSEMI大半导体产业网www.semi.org.cnƒInfrastructure availability and supply chainƒI/O standardization between interfacesƒThermal management and interconnect reliabilityƒShift in the Design/Test method paradigm and system co‐design3DICProductDevelopmentChallengesSEMI大半导体产业网www.semi.org.cnThank you for your attention!SEMI大半导体产业网www.semi.org.cn