通过TM320F28xx-28xxxDSC设计模拟接口的概述(Rev.A)

TMS320F28xx/28xxx DSCs 模拟接口设计综述 应用 报告 软件系统测试报告下载sgs报告如何下载关于路面塌陷情况报告535n,sgs报告怎么下载竣工报告下载 ZHCA063–2008年5月 摘要 本应用报告提供了一个TMS320F28xx/28xxx 数字信号控制器的设计参考指南，主要 内容 财务内部控制制度的内容财务内部控制制度的内容人员招聘与配置的内容项目成本控制的内容消防安全演练内容 有：模数转 换器的配置、设定相关的寄存器、响应对应的中断和电路板设计参考等。本指导 书 关于书的成语关于读书的排比句社区图书漂流公约怎么写关于读书的小报汉书pdf 对于第一次接触 TMS320C2000™数字信号处理器(DSP)，和很少使用模拟器件的软件 工程 路基工程安全技术交底工程项目施工成本控制工程量增项单年度零星工程技术标正投影法基本原理 师来说是很有用的。本指导书包 含了许多系统设计时需要考虑的难点问题，主要有：采样频率的设定、高效地从数字信号变换到系统数据 存储器的输入通道序列、输入驱动电路和滤波电路、电源供给和校准等。为了更好地利用数字信号控制器 (DSC)——TMS320F28xx/28xxxx系列中的模数转换器(ADC)来进行设计，我们从不同文档中节选许多信息 编成方便的设计指南。相关的代码是在F280x eZdsp™开发板上运行的，这些代码也可以广泛作为使用此 ADC新设计的软件框架。 在本指导书中涉及到的附属项目和源代码在下面的地址中都能下载: http://www-s.ti.com/sc/techlit/spraap6.zip 目录 1 简介 2 2 模数转换模块的结构和描述 3 3 模数转换器的准备和运行 4 4 F2823x和F2833x系列的DMA功能和校准功能 12 5 原理图和布线设计 16 6 模数转换器的校准 18 7 附加支持 18 8 参考文献 19 附录 A F280xx和F281x的差异 20 Pradeep Shinde 图目录 1 模数转换器简化模块图 3 2 TMS320F280xx芯片的模数转换器引脚连接原理图 5 3 模拟输入引脚的阻抗模式(F280xx) 5 4 典型的模数转换器输入引脚缓冲/驱动电路 6 5 模数转换器的时钟级联 8 6 连续模式下的同步和采样频率 9 7 通过PIE多路使用模数转换器中断 11 8 简化的硬件状态机 14 9 地址控制器 14 10 设计例子1: 放置器件 17 11 设计例子2:走线/铺铜 17 12 模数转换器转换传递函数关系 18 表目录 A-1 F280xx 和 F281x 外设差异 20 TMS320F28xx/28xxx DSCs模拟接口设计综述 1ZHCA063–2008年5月 www.ti.com.cn TMS320F28xx/28xxx DSCs模拟接口设计综述2 ZHCA063–2008年5月 简介 TMS320F28x DSC’s具有16-通道，12-位的模数转换器，可以让设计者像使用多种嵌入式设备一样，直接把 模拟信号连接到处理芯片上。在TMS320F28xxDSCs上，增强型ADC外设具有12位分辨率，并且能获得每秒 加速到12.5兆(MSPS)的采样速度（一般的芯片是6.25 MSPS和 3.75 MSPS），并且通过流水线结构可以监控 模拟信号（如图1）。另外的特性，例如16通道的多路复用、自动定序，双采样和保持(S/H)电路和多路中断 表，这些都使得使用者在嵌入式控制和数据记录应用中非常方便。为了发挥外设接口的灵活性，必须正确配 置ADC，可以通过建立和配置不同的电路得到具体的方法。为了实现最佳性能，必须理解和设置需要的采样 比、利用自动定序器来定位通道，同时进行中断配置以读取结果。本文已经包含了利用DSP/BIOS™的软件核 函数（TI为TMS320™DSP设计的实时操作系统）的 方案 气瓶 现场处置方案 .pdf气瓶 现场处置方案 .doc见习基地管理方案.doc关于群访事件的化解方案建筑工地扬尘治理专项方案下载 ，此指导书也讨论了电路板设计的一些问题和系统设 计时需要注意的事项。 TMS320F281x, TMS320F280xx, TMS320F2804x和较新的TMS320F2832x系列上的ADC外设基本上具有 相同的结构，而F280xx和F281x系列芯片上ADC的外设在规格上，具有很少不同的参数，这些在附件A中 都有详细说明。本应用报告采用F280xx设备的信息，利用不同的图解走查了相关的设置。附属的代码也是 针对F280xx芯片的，但是也可以移植到F281x芯片上。更多的细节可以参考数据转换手册 (SLAA013) [1]和 TMS320F2809，TMS320F2808，TMS320F2806，TMS320F2802，TMS320F2801，TMS320C2802， TMS320C2801和TMS320F2801x DSP数据手册(SPRS230) [2]。 如果想得到更多组件信息和寄存器细节可以 参考TMS320x280x, 2801x, 2804x 模数转换器（ADC）参考指南 (SPRU716) [4], TMS320x2833x 模数转换器 模式(ADC) Module (SPRU812) [18]和TMS320x281x DSP模数转换器参考指南(SPRU060) [5]. 更多关于系统 控制和中断参考的信息，可以参考缓冲运算放大器到ADC电路集(SLOA098) [6]。 如果你对ADC的参数和术语不是很熟悉，那么参考数字转换器(SLAA013) [1]。 1 简介 TMS320F28xx/28xxx DSCs模拟接口设计综述 3ZHCA063–2008年5月 www.ti.com.cn 2 Architecture and Description of ADC Module Ch�Set�(CONV00) Ch�Set�(CONV01) Ch�Set�(CONV02) Ch�Set�(CONV03) Ch�Set�(CONV07) State Pointer MAX�CONV1 Ch�Set�(CONV08) Ch�Set�(CONV09) Ch�Set�(CONV10) Ch�Set�(CONV11) Ch�Set�(CONV15) State Pointer MAX�CONV2 Sequence Arbiter 12-Bit A/D Converter SOC EOC S/H-A S/H-B MUX Select ADCINA0 ADCINA1 ADCINA7 MUX Select ADCINB0 ADCINB1 ADCINB7 4 SOC1 EOC1 44 Note:�Possible�values: Channel�Select�=�0-15 MAX�CONV1�=�0-7 MAX�CONV2�=�0-7 Software ePWM_SOC_A External�Pin (XINT2_ADCSOC) Start-of-sequence Trigger SEQ1 SEQ2 SOC2 EOC2 M UX 12 ADCRESULT0 ADCRESULT1 ADCRESULT7 12Result Select Result MUX ADCRESULT8 ADCRESULT9 ADCRESULT15 12Result Select Result MUX12 12 Software ePWM_SOC_B Start-of-sequence Trigger ADC�start�of�conversion�(SOC)�trigger�sources 4 Analog�MUX 2.1 Main Blocks and Their Functionality www.ti.com Architecture and Description of ADC Module Figure 1 illustrates a simplified block diagram of the ADC architecture. Figure 1. Simplified Block Diagram of ADC Module Two sets (A and B) of 8-channel multiplexers expand the analog input capacity to 16 channels. Each MUX block is followed by its own sample-and-hold circuit (S/H-A and S/H-B). This arrangement of dual-MUX and S/H circuits makes simultaneous sampling possible. For example, one channel each from the A and B block are sampled at the same instance, reading V and I values to calculate instantaneous power. There is a single 12-bit ADC core, which is a pipeline analog-to-digital converter. The sequencer arbiter keeps track of the input signals connected to the ADC, including the simultaneous mode. Dual auto-sequencers (SEQ1 and SEQ2) bring flexibility by randomly selecting the sequence in which the ADC input channels connect to the ADC core. This helps by considerably reducing CPU overhead for repetitive ADC operation. Each 8-state sequencer can be used independently to convert up to eight channels in the preset sequence, and Sequencer1 and Sequencer2 can be cascaded to form a single 16-channel sequencer. SPRAAP6A–May 2008 An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs 3 Submit Documentation Feedback 2 模数转换器模块的结构和描述 图1 显示了ADC结构的精简模块图 图1. ADC结构的精简模块图 2.1 主要模块和它们的功能 两个8通道的多路复用器(A和B)扩展了模拟输入到16位通道，每一个MUX模块都有它自己的采样保值电路(S/ H-A和S/H-B)，这种双MUX和S/H使同时采样成为可能，例如，从A和B模块的每一个通道在同一个实体中采 样，读取电压和电流值，然后计算出瞬时功率。 12位的ADC核是模数转换器的管路。序列发生器仲裁保持输入信号与ADC相接，包括在同步模式下。 双自动序列发生器(SEQ1和SEQ2 )可以随机选择序列，决定哪一个ADC通道和ADC的核相连接，这样就减少 了重复ADC操作带来的CPU过热问题。每8个状态的序列发生器在预订的程序单独转换成8个通道，并且序列 发生器1和序列发生器2可以级联形成单16通道的序列发生器。 模数转换模块的结构和描述 www.ti.com.cn TMS320F28xx/28xxx DSCs模拟接口设计综述4 ZHCA063–2008年5月 可以利用ADCMAXCONV寄存器设置每个序列的转换数目（每个序列发生器上限是8个，如果级联的就是 16）。图1显示了四个不同的外置信号，它们可以作为序列发生器1(SEQ1)的开始转换(SOC)的触发器，也可 以利用软件或脉冲宽度调制(PWM) 设置序列发生器2(SEQ2)的触发器。 该模块有16个结果寄存器(ADCRESULT0 – ADCRESULT15)，这些寄存器在开始转换成系统存储之前，保存 着模数转换器的计数，任何输入通道(ADCINxx)，在序列里都可能被分配给每一次转换，这样就可以很方便 重复或者跳过任何通道和通道数在ADCRESULTn寄存器中的序列。 每一个序列的结束(EOS)都会产生三个不同的中断信号ADCINT，SEQ1INT和SEQ2INT，这些中断信号可以 把从结果寄存器中的数据转移到系统存储器中。有关ADC的操作的中断服务程序(ISR)只有CPU可以干涉， 这样在完成转换中就减少了CPU的消耗。更多的有关自动转换序列的细节，可以参考TMS320x280x, 2801x, 2804x DSP 模数转换器参考指南(SPRU716) [4]和TMS320x281x DSP模数转换器参考指南(SPRU060) [5]. 关键说明 在进行设置之前，首先要审查一下说明，必须确保你对这些数据转换的术语比较熟悉，在这个简短关键要注 意的是，采样频率和输入模拟信号的范围，增益和偏离误差是下一阶段要考虑的重要参数，必须对它们进行 有效地处理才能使系统正常。 在F280x/F280xx 芯片上的最大采样频率是12.5/6.25/3.75 MSPS 而F281x 芯片为12.5 MSPS。 在F280x/F2801x芯片上最大模数转换器的时钟为25/12.5/6.25 MHz 而在F281x芯片上为25 MHz 输入信号的范围是 0 V to 3.0 V，偏移误差和增益误差与其它的模数转换器一样。 更多的细节可以参考其它详细说明，或参考下列芯片的电气部分：TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, 和TMS320F2801x DSPs 数据手册 (SPRS230) [2], TMS320F2810,TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811,TMS320C2812 数字信号处理数据手册 (SPRS174) [3] 和TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 数字信号控制数据手册(SPRS439) [19]. • • • 2.2 硬件设置 在ADC硬件设计方面，有两个主要的方面： 为了实现ADC的一定功能，添加的无源器件。 处理模拟输入信号的电路。在第5部分有许多有关完成原理图和电路板设计的内容 • • 3.1 ADC的设定和操作 在这一部分将要讨论设计问题。在硬件方面，需要考虑的是外围被动器件，也就是为了实现一些功能而添加 的器件，同样为实现功能的模拟输入信号与ADC输入引脚相连接的问题也是非常重要的。电源供电和外部参 考电压在3.2.2部分讨论。 3 模数转换器的准备和运行 TMS320F28xx/28xxx DSCs模拟接口设计综述 5ZHCA063–2008年5月 www.ti.com.cn 3.1.1 Required External Components for the ADC ADCINA[7:0] ADCINB[7:0] ADCLO ADCREFIN ADCRESEXT ADCREFP ADCREFM VDD1A18 VDD2A18 VSS1AGND VSS2AGND VDDA2 VSSA2 VDDAIO VSSAIO Analog�Input�0�V�to�3�V�with�respect�to ADCLO Connect�to�analog�ground Float�or�ground�if�internal�reference�is�used 2.2�µF(A) 2.2�µF(A) 22�K� ADC Analog�Power�Pin�(1.8�V) ADC Analog�Power�Pin�(1.8�V) ADCREFP and ADCREFM should�not�be�loaded�by external�circuitry ADC Analog�Ground�Pin ADC Analog�Ground�Pin ADC Analog�Power�Pin�(3.3�V) ADC Analog�Ground�Pin ADC Analog�Power�Pin�(3.3�V) ADC Analog�I/O�Ground�Pin ADC�16-Channel Analog�Inputs ADC�External�Current Bias�Resistor ADC�Reference�Positive�Output ADC�Reference�Medium�Output ADC�Power ADC Analog�and Reference�I/O�Power 3.1.2 Analog Input Signal Interface Source Signal AC R8 ADCIN0 C 10�pF p R 1�k on � C 1.64�pF h 28x�DSP Switch www.ti.com ADC Set-Up and Operation Few external components are required for biasing of internal band gap reference and filtering noise on reference voltage signals. Figure 2, reproduced from F280xx data sheets, shows these parts and their connections. Figure 2. ADC Pin Connections for TMS320F280xx These pins must be connected as shown above. The F281x devices require different values for these parts (Appendix A). The next step is to design the hardware interface connecting the input analog signals to the ADCINxx pins. Note that each input analog signal sees the load from the ADCIN pin as shown in Figure 3. Ch is the sample capacitor and Ron is the ON resistance of the multiplexer path. Cp is the parasitic capacitance associated with the ADCIN pin. Figure 3. Analog Input Impedance Model (F280xx) SPRAAP6A–May 2008 An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs 5 Submit Documentation Feedback 3.1.1 Required External Components for the ADC ADCINA[7:0] ADCINB[7:0] ADCLO ADCREFIN ADCRESEXT ADCREFP ADCREFM VDD1A18 VDD2A18 VSS1AGND VSS2AGND VDDA2 VSSA2 VDDAIO VSSAIO Analog�Input�0�V�to�3�V�with�respect�to ADCLO Connect�to�analog�ground Float�or�ground�if�internal�reference�is�used 2.2�µF(A) 2.2�µF(A) 22�K� ADC Analog�Power�Pin�(1.8�V) ADC Analog�Power�Pin�(1.8�V) ADCREFP and ADCREFM should�not�be�loaded�by external�circuitry ADC Analog�Ground�Pin ADC Analog�Ground�Pin ADC Analog�Power�Pin�(3.3�V) ADC Analog�Ground�Pin ADC Analog�Power�Pin�(3.3�V) ADC Analog�I/O�Ground�Pin ADC�16-Channel Analog�Inputs ADC�External�Current Bias�Resistor ADC�Reference�Positive�Output ADC�Reference�Medium�Output ADC�Power ADC Analog�and Reference�I/O�Power 3.1.2 Analog Input Signal Interface Source Signal AC R8 ADCIN0 C 10�pF p R 1�k on � C 1.64�pF h 28x�DSP Switch www.ti.com ADC Set-Up and Operation Few external components are required for biasing of internal band gap reference and filtering noise on reference voltage signals. Figure 2, reproduced from F280xx data sheets, shows these parts and their connections. Figure 2. ADC Pin Connections for TMS320F280xx These pins must be connected as shown above. The F281x devices require different values for these parts (Appendix A). The next step is to design the hardware interface connecting the input analog signals to the ADCINxx pins. Note that each input analog signal sees the load from the ADCIN pin as shown in Figure 3. Ch is the sample capacitor and Ron is the ON resistance of the multiplexer path. Cp is the parasitic capacitance associated with the ADCIN pin. Figure 3. Analog Input Impedance Model (F280xx) SPRAAP6A–May 2008 An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs 5 Submit Documentation Feedback 模数转换器需要的外部器件 为了偏置内部带宽间隔的参考和实现参考电压信号的滤波，需要添加一些外部器件。图2，显示了F280xx数 据手册中这一部分的连接和器件。 3.1.1 图2. TMS320F280xx芯片的ADC的引脚连接 这些引脚必须按照上面图来连接，对于F281x芯片需要不同的值，在附件A中可以看到。 模拟信号输入接口 这一步是设计输入模拟信号和ADCINxx引脚连接的硬件接口，需要注意的是，每一个输入的模拟信号都被看 作是ADCIN引脚的负载，如图3所示，Ch是采样电容，Ron是多路复用的导通电阻，Cp是和ADCIN引脚连接的 寄生电容。 3.1.2 图3. 模拟输入阻抗模型 (F280xx) 模数转换器的准备和运行 www.ti.com.cn TMS320F28xx/28xxx DSCs模拟接口设计综述6 ZHCA063–2008年5月 _ +VIN RIN CIN S1 RSW S2 CSH VSH VPSOp Amp tV (t) = V ( - e )c IN � 3.2 Software Setup ADC Set-Up and Operation www.ti.com For every conversion, the S/H switch is closed for a period equivalent to (ACQ_PS + 1) × ADCCLK cycles. During this period, the sample capacitor Ch is charged to the voltage on the ADCIN pin that is connected through MUX. The source impedance of this analog signal should be as low as possible and remain stable when it is being sampled. The external driver and filter circuit has to be designed considering the above circuit and component values. The higher the source impedance, the higher the ACQ_PS (sample time) value number should be set. The goal is to charge the S/H capacitor to the voltage equal to the VIN value; with less than one-half least significant bit (LSB) in error. It is a good practice to use an op-amp driver circuit for signal conditioning of input analog signals and as a buffer. It provides low/stable output impedance and can be configured as filter or level shifter; it also protects the ADC inputs. Figure 4 shows a commonly used ADC driver circuit configuration for DC and low-frequency signals. The voltage range of an analog signal should be restricted between 0 V and 3.0 V. Note: First, the analog signals travel through a multiplexer network. Any voltage out of 0 V-3.0 V range will bias the multiplexer in an undesired way, giving incorrect values for other channels as long as the out-of-range voltage remains. For achieving good accuracy, the sample capacitor should be charged to within LSB of the final value. Figure 4. Typical Buffer/Driver Circuit for ADCIN The op-amp isolates the ADC and acts as a low-impedance source to charge the sample capacitor; it can be configured as a unity gain buffer. External RIN and CIN form a low-pass filter. RIN isolates the ADC from the amplifier during sampling; CIN helps in signal stability. VPS is the residue from a previous sample. Ideally it would be zero, but if you are sampling back-to-back, it approaches the previously sampled value. RSW is the on-resistance of MUX. During acquisition, S1 is closed, S2 is open. The sampling capacitor CSH (1.64 pF) is charged through the switch resistor RSW (1 kΩ) and RIN (should not exceed 50 Ω, typically). The action of charging the capacitor is shown in following equation. For the internal RC circuit formed by RSW and CSH, the settling time is 9 ns. It is much smaller than the minimum sampling window of 40 ns at 12.5 MSPS; however, this time period is much longer for the external RC circuit. It should be met by a higher value for ACQ_PS and/or lower sampling frequency, and meet your design's sample rate requirement. Suggestions for Op-amp are TI's OPA340 and OPA350; being single supply, precision parts. The ADC has to be configured first to comply with system requirements. Those requirements include sampling rate, selection, sequencing the input channels, ADC interrupt management, etc. This is achieved through various setup registers. The associated code file includes the complete setup procedure. 6 An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs SPRAAP6A–May 2008 Submit Documentation Feedback 首先模拟信号穿过多路复用网络，任何超过0 V-3.0 V范围的电压会产生不可想象的偏移，只要电 压值超过范围，其他通道的值就是错误的。 注释： 对每一次转换，取样/保持开关在(ACQ_PS + 1) × ADCCLK时间内是关闭的，在这段时间内，采样电容Ch在 充电，电容上的电压即ADCIN引脚上电压，并且这个引脚和MUX连接。模拟信号上的源阻抗应该尽量低并且 当开始采样的时候保持稳定。外部驱动和滤波电路必须按照上面的电路和器件的数值来进行设计。源阻抗越 高，就需要把ACQ_PS(采样时间)的值设置越高，目的是要改变采样/保持电容的电压和VIN值相等，不过同时 会带来小于1/2LSB错误信号。 利用运算放大器驱动电路对输入模拟信号进行处理同时作为缓冲，是一个很好方法，它提供了低而稳定的输 出阻抗，并且可以配置成滤波器或电平移动电路，同时还可以保护ADC的输入。图4显示了一般针对直流、 低频信号ADC驱动电路的配置，模拟信号的电压范围被严格控制在0V到3.0 V。 为了得到准确地好的结果，采样电容应该控制在最终LSB值的有效范围内。 运算放大器独立于模数转换器，对采样电容来说是一个低阻抗源，可以配置成一个整体的增益缓冲。外部 RIN，CIN引脚形成了低通滤波，独立于ADC的RIN在采样期间是起放大作用的，CIN有助于信号的稳定。 VPS是上次采样值，理想情况下是零，如果反复采样的话，就可能是上次采样的值。RSW是MUX的导通电阻， 在采集时，S1关闭，S2打开。采集电容CSH(1.64 pF)通过开关电阻RSW (1 kW)和RIN (通常不会超过50 W)进行 充电。充电电容按照下面的公式计算。 对于由RSW 和CSH构成的RC电路来说，置位的时间是9ns，这个时间远远小于在12.5MSPS条件下的最小采样 窗口40 ns的时间，然而，这个时间远远大于外部的RC电路所消耗的时间。为了满足ACQ_PS或低采样频率， 同时满足设计时采样率的需要，置位时间应该设置为较高的值。 建议的运算放大器采用TI公司的 OPA340和OPA350，它们由单电源供电，具有很高的精度。 _ +VIN RIN CIN S1 RSW S2 CSH VSH VPSOp Amp tV (t) = V ( - e )c IN � 3.2 Software Setup ADC Set-Up and Operation www.ti.com For every conversion, the S/H switch is closed for a period equivalent to (ACQ_PS + 1) × ADCCLK cycles. During this period, the sample capacitor Ch is charged to the voltage on the ADCIN pin that is connected through MUX. The source impedance of this analog signal should be as low as possible and remain stable when it is being sampled. The external driver and filter circuit has to be designed considering the above circuit and component values. The higher the source impedance, the higher the ACQ_PS (sample time) value number should be set. The goal is to charge the S/H capacitor to the voltage equal to the VIN value; with less than one-half least significant bit (LSB) in error. It is a good practice to use an op-amp driver circuit for signal conditioning of input analog signals and as a buffer. It provides low/stable output impedance and can be configured as filter or level shifter; it also protects the ADC inputs. Figure 4 shows a commonly used ADC driver circuit configuration for DC and low-frequency signals. The voltage range of an analog signal should be restricted between 0 V and 3.0 V. Note: First, the analog signals travel through a multiplexer network. Any voltage out of 0 V-3.0 V range will bias the multiplexer in an undesired way, giving incorrect values for other channels as long as the out-of-range voltage remains. For achieving good accuracy, the sample capacitor should be charged to within LSB of the final value. Figure 4. Typical Buffer/Driver Circuit for ADCIN The op-amp isolates the ADC and acts as a low-impedance source to charge the sample capacitor; it can be configured as a unity gain buffer. External RIN and CIN form a low-pass filter. RIN isolates the ADC from the amplifier during sampling; CIN helps in signal stability. VPS is the residue from a previous sample. Ideally it would be zero, but if you are sampling back-to-back, it approaches the previously sampled value. RSW is the on-resistance of MUX. During acquisition, S1 is closed, S2 is open. The sampling capacitor CSH (1.64 pF) is charged through the switch resistor RSW (1 kΩ) and RIN (should not exceed 50 Ω, typically). The action of charging the capacitor is shown in following equation. For the internal RC circuit formed by RSW and CSH, the settling time is 9 ns. It is much smaller than the minimum sampling window of 40 ns at 12.5 MSPS; however, this time period is much longer for the external RC circuit. It should be met by a higher value for ACQ_PS and/or lower sampling frequency, and meet your design's sample rate requirement. Suggestions for Op-amp are TI's OPA340 and OPA350; being single supply, precision parts. The ADC has to be configured first to comply with system requirements. Those requirements include sampling rate, selection, sequencing the input channels, ADC interrupt management, etc. This is achieved through various setup registers. The associated code file includes the complete setup procedure. 6 An Overview of Designing Analog Interface With TMS320F28xx/28xxx DSCs SPRAAP6A–May 2008 Submit Documentation Feedback 软件设置 首先要按照系统的需要，设置ADC的相关配置，包括采样频率、选取输入序列通道和ADC中断管理等。上述 操作需要通过一些寄存器来设置，附件的代码文件包含了完整的设定程序。 3.2 图4. ADCIN典型的缓冲/驱动电路 模数转换器的准备和运行 TMS320F28xx/28xxx DSCs模拟接口设计综述 7ZHCA063–2008年5月 www.ti.com.cn 设置ADC寄存器 最基础的设置是采样速率、选择/设置自动序列、选择采样的模式、选择开始转换信号和设置序列发生器的通 道。例如第16位结果寄存器存有这样一个值，目的是为了使输入通道按照你想要的顺序，同时为了记住每个 序列需要转换的数量。这一部分讨论了如何设置这些参数，解释了EOS的中断，这些中断是为了CPU以最小 的代价同步把ADC计数从结果寄存器中传到系统数据存储器(RAM)中。ADC的操作是在后台执行，没有消耗 任何CPU，主要是因为自动时钟的功能。如果想得到更详细的ADC外设寄存器的信息可以参考F281x芯片的 TMS320x281x DSP 模数转换器(ADC) 参考指南(SPRU060) [5] 和针对F280xx 芯片的TMS320x280x, 2801x, 2804x模数转换器参考指南(ADC) (SPRU716) [4]。 3.2.1 ADC 上电和参考电压的选择 在所有的F28xx/F28xxx芯片的复位时，ADC内部带隙和参考电路都处于电源关闭状态。 ADC模块的时钟输入是无效的。带隙是参考电路和模数转换器可以一起上电，在关闭时，可以同时关掉。然 而，对F281x芯片，带隙参考需要首先上电，紧接着是ADC复位上电。 内部带隙参考电压的电路有百万分之50 (PPM)/℃的温度稳定性。如果系统需要更精确的温度变化时，则需要 采用具有很大温度稳定性的外部电压参考源。外部电压参考源电路在转换期间提供了足够的驱动和低噪声环 境，典型的原理图在TMS320x281x DSP 模数转换器参考指南（SPRU060) [5]，中可以看到。 模数转换器的上电顺序如下： 1. 使能模数转换器时钟。设置 PCLKCR1寄存器的ADCENCLK位= 1。 2. 如果需要，设置外部VREF。 对于F280xx设备，ADCREFIN输入电压(1.024 V, 1.500 V, 或 2.048 V)代替了内部BG电压。内部BG电压是用来 产生REFP/REFM信号，在模数转换器转换期间要使用到。 ADCREFSEL寄存器的两个REF_SEL位的值设置如下: = 00内部参考电压(默认) = 01外部参考电压2.048 V = 10外部参考电压1.500 V = 11外部参考电压1.024 V F281x 设备:让EXTREF (ADCCTRL3) = 1逻辑上不连接REFP/REFM，用户可使用外部参考电压。如果 ADCREFP引脚接2.0 V，ADCREFM引脚接1.0 V， ADCREFP – ADCREFM 之间的电势差应该是1.00 ± 0.01 V。 3.2.2 对于F280xx和F281x芯片，不管外部参考电压是多少，ADC模拟输入的电压范围仍然是0 V to 3 V注释： 在ADC上电之后，对F280xx芯片允许有5 ms延时 (对F281x芯片有10 ms延时) ，这样以便于REFP 和REFN引脚上的外部电容在适当时充电，在这段期间ADC的计数是不准确的。 注释： 3. 给ADC上电，需要设置ADCTRL3寄存器中的ADCBGRFDN和ADCPWDN位= 1。 模数转换器的准备和运行 www.ti.com.cn TMS320F28xx/28xxx DSCs模拟接口设计综述8 ZHCA063–2008年5月 3.2.3 Setting the ADC Clock Frequency and Sampling Rate No�PLL PLL HISPCP HSPCLK ADCENCLK PCLKCR[3] ADCLKPS CPS ADC�CLK ACQ_PS SH Clock/ Pulse XCLKIN ADC Set-Up and Operation www.ti.com With up to 16 analog input signals, the sampling rate can be decided based on the signal with the highest frequency per the Nyquist theory or any other system-level considerations. The parameters used in the sample rate calculations are the ADC clock and the sample time (acquisition) window. Also, setting of the sampling mode (simultaneous or sequential) affects the sample rate, due to specific architecture. N