半导体Flow

0.15um製程Flow的簡介0.15um製程Flow簡介0.15um製程Flow簡介PeripheryCellSenseAmplifierCell–儲存電荷:Storagenode/NmosS/A–放大器與解碼器:Nmos/PmosPeriphery–控制電路:Nmos/Pmos2.non-dopeda-SiDeposition(520oC,200+-20Ao)3.CVD-Si3N4Deposition(750oC,1200+-50Ao)6.Si3N4DryEtching(RIE)1F5.Photolithography17.PRRemoval(ASH)8.TrenchEtching(-3000Ao,Si3N4Mask)Wafer9.TrenchInnerWallOxidation(11000C,90min,254+-22Ao,O2)10.HDP-CVDP-SiO2Fill(5200+-300Ao)11.SiO2Sintering(11000C,Ar)4.PlasmaARCDeposition(480+-30Ao)0.15um製程Flow簡介1.PadOxidation(820oC,170+-8Ao)1IWafer1.Photolithography32.P-Implant(2.6MeV,1E13)3.P.R.Removal(Wet)4.PAnneal(900oC,60min,N2)PadOxidationPoly-Si0.15um製程Flow簡介2IWafer1.Photolithography42.N-WellP-Implant(600KeV,1E13)3.C.CP-Implant(300KeV,6E12)4.PTSAs-Implant(180KeV,6E12)PadOxidationPoly-Si5.CDB-Implant(15KeV,4.5E12)6.P.R.Removal(Wet)0.15um製程Flow簡介3IWafer1.Photolithography52.P-WellB-Implant(250KeV,1E13)3.C.CB-Implant(120KeV,6E12)4.CDB-Implant(70KeV,3.8E12)PadOxidationPoly-SiB(CD)N-Well5.P.R.Removal(Wet)0.15um製程Flow簡介4IWaferPadOxidationPoly-SiB(CD)N-WellP-WellP-Well1.Photolithography62.P-WellB-Implant(700KeV,1E13)3.CCB-Implant(140KeV,3E12)4.PTSB-Implant(30KeV,3E12)5.CDB-Implant(15KeV,7.6E12)6.P.R.Removal(Wet)0.15um製程Flow簡介1DWaferPadOxidationPoly-SiN-WellP-WellP-WellB(CD)B(CD)B(CC)B(CC)1.Photolithography72.PTSB-Implant(70KeV,1.12E13)3.CDB-Implant(30KeV,2E12)4.P.R.Removal(Wet)5.LampAnneal(8500C,30sec,N2)B(CD)0.15um製程Flow簡介TGCD=0.3um0.178um0.28um0.35umN_Well(PMOS)M/CPer.NMOSArrayNMOS(P_Well)S/A(P_Well)2I(I3B01)4I(I4BCA)15KeV/4.6E1215KeV/8.4E124I(I4BSA)1D(I5BV1)30KeV/3E1230KeV/2E124I(I4BD1)+1D(I5BH1)3I(I4BD1)70KeV/3.4E1270KeV/1.16E1370KeV/3.4E123I(I4B01-2)3I(I4B01-2)120KeV/6E12120KeV/6E122I(I3AP1)180KeV/6E123I(I4B01-1)3I(I4B01-1)250KeV/1E13250KeV/1E132I(I3P01)600KeV/1E134I(I4BWA)700KeV/1E131I(I2PI1)2.6MKeV/1E13N_WellN_WellBottomN-Well(1I)N_WellPeripheryS/AM/CP_Well0.178um0.30um0.35um0.28um0.30umP_WellP_Well2I2I2I3I3I4I1D0.15umImp示意圖0.15um製程Flow簡介TGWaferPadOxidationPoly-SiN-WellP-WellP-Well1.LightEtchPadOxidation2.Oxidation(ISSG,10500C,72+-3Ao)In-situ-steam-generationTDDB(TimeDependentDielectricBreakdown)CCS(Constantcurrentstress)test3.a-SiDeposition(5200C,600+-30Ao)4.CVDWSiDeposition(1000+-80Ao)5.TEOSDeposition(670oC,750Ao)7.PlasmaARCDeposition(1st:200+-30Aohighk;2st:250+-30Aolowk)降低反射率8.Photolithography86.SiNDeposition(750oC,700+-35Ao)9.SiN/TEOSEtch10.P.R.Removal(ASH)11.WSi/PolyEtch(SiNMask)B(CC)0.15um製程Flow簡介TGWsiTGAEI1TGAEI2Bin12failmapComment:TGSiNDA706iscommonalitymachineandtheparticleinducethe432WLfail0.15um製程Flow簡介0.15um256M(2)TGSiNDA706432WLfail1NWaferPadOxidationPoly-SiN-WellP-WellP-Well1.LampAnneal(O2/N2,950oC,30sec)2.LampAnneal(Oxidation)(O2,1100oC,25sec)ImproveHardcarrier(GIDLcontrol)GateinducedDrainLeak3.P-Implant(N-,15KeV,1E13)B(CC)0.15um製程Flow簡介2NWaferPadOxidationPoly-SiN-WellP-WellP-Well1.SiNDeposition(750oC,300+-15Ao)2.SiNE/B(O2,300Ao,stoponoxidation)3.P-Implant(N-,20KeV,1E13)4.Photolithography95.As-Implant(N+,50KeV,2.5E15)6.P.R.Removal(Asher)LDD製程(LightlyDopedSourceDrain)0.15um製程Flow簡介2PWaferPadOxidationPoly-SiN-WellP-WellP-Well1.Photolithography102.BF2-Implant(P+,20KeV,2.26E15)3.P.R.Removal(Asher)/WL此道光阻較難去除becauseAs/BF2imp)0.15um製程Flow簡介1B-10.15um製程Flow簡介BSWaferPadOxidationPoly-SiN-WellP-WellP-Well2.BPTEOSDeposition(450oC,4600+-150Ao)3.OxideReflow(RTO,950oC,O2,30sec,4500+-400Ao)(防止void)4.ARCCoating(180oC,60sec,900Ao)5.Photolithography116.OxidationSACEtch(C4F8)SAC(selfalignmentcontact)7.P.R.Removal(Asher,1000W,200oC,90sec)8.SiNEtch11.Poly-SiE/B(Remain:3800+-300Ao)12.CMP(900+-150Ao,Remain:2900+-300Ao)10.a-SiDeposition(520oC,3000+-150Ao)0.15um製程Flow簡介1.SiNDeposition(750oC,150+-15Ao)(防止B/Pdiffusion)9.P-Implant(SAC,30KeV,1.5E13)0.15umS9Y7000ASCUnopencenterfailFBMmapWT830mapDescription:Sufferlots:BP650/675/991/918/BR187/653/118/456/150/163/501……..AlwaysCeramicEQ(BSSACEtch)hadthisissue原因判明:BSSACEtchCeramicEQcentertemperatureishigherAction:BSSiNetchadd3”(14”changeto17”)0.15um製程Flow簡介0.15umS9YPX202/203DistortionFBMmapWT830map原因判明:PX202/203marginnotenoughAction:1F~TGSGSCancel0.15um製程Flow簡介BinmapX’section原因判明:DT002BTRBAction:1.CheckDT002BEQstatus2.再次確認BPTEOSB/P%BSDT002BBPTEOSVoid0.15um製程Flow簡介1BWaferPadOxidationPoly-SiN-WellP-WellP-Well2.TEOSSinter(N2,800oC10mins)3.ARCCoating(180oC,60sec,900Ao)4.Photolithography125.RELACS(113oC,70sec)6.OxidationDryEtch(C4F8)7.P.R.Removal(Asher,1000W,200oC,90sec)11.P.R.Removal(Asher)12.OxideAnneal(N2,700oC,25min)不可使用高溫否則BPTEOSB/P%willshift8.P-Implant(SAC,25KeV,1.2E14)10.BF2-Implant(SAC,40KeV,5E15)9.Photolithography130.15um製程Flow簡介1.TEOSDeposition(670oC,2000+-100Ao)AfterPhotoRELACSCoatingMixingBakeAfterRELACSDevelopingResistRELACSmaterialHolePatternShrinkDevelop&RinseResistWaferCross-linkedlayerAcidHolePatternRELACS處理 流程 快递问题件怎么处理流程河南自建厂房流程下载关于规范招聘需求审批流程制作流程表下载邮件下载流程设计 :1.根據一般的PhotoProcess所形成的PatterHole。2.在RELACSPatter上,將RELACS劑Spincoating,形成RELACS層。3.訂定溫度時間進行加熱處理,讓RELACS所殘存的酸成份在上層劑中撗散,而且在上層中與觸媒產生架橋反應,並在ResistHolePatter內側形成非水溶性之架橋膜。4.再用純水及IPA洗淨,並將架橋膜去除,即得到Size縮小的HolePattern。Crack發生之成因ModeI：在RELACSPROCESS的熱處理過程，經過昇溫或冷卻過程時，光阻與與RELACS形成框壁，會因熱膨脹率差異之原因，而發生龜裂之現象。ModeII：光阻本身的溶劑揮發時，會因收縮應力而產生微裂，而其微裂程度可能是KLA檢測不出的微小程度，但之後在RELACSPROCESS時，會因上記應力而完全龜裂，或是被滲入溶解。ModeIII：RELACS的顯影液10%IPA，揮發時，造成應力不均，而產生Crack之現象。綜合以上推斷，Crack發生在Stress接受不均等的地方。@purpose:ETRONhighlightNSJ(64M)producthad1B-CRACKissue.And,INTpointoutthe1B-CRACKalwayshappenedintheareabetweenPADandPAD.Andtheselotsarereworklots.SoYEDCompare1B_crackbetweenreworklotsandnoreworklots.reworkNSJw/oreworkreworkS9Yw/oreworkCode111(跨電位)Code11(沒跨電位)CP560:20CN632:20CP117:02CN800:20NSJ1BcrackissueBLWaferPadOxidationPoly-SiN-WellP-WellP-Well2.LampAnneal(N2,425oC,60sec)3.CoRemoval4.LampAnneal(N2,770oC,30sec)(降低阻值因為會影響到SACimp的As）5.Ti/TiNSputter(Ti=120+-10Ao,TiN=300+-10Ao)6.LampAnneal(N2,740oC,30sec)7.WDeposition(430oC,1000+-100Ao)8.SiNDeposition(700oC,700+-35Ao)10.Photolithography1411.SiNDryEtch12.P.R.Removal13.WEtch0.15um製程Flow簡介1.Co/TiNSputter(Co=800+-40Ao,Ti/N=450+-45Ao)9.PlasmaARCDeposition(1st:480+-30Ao,2st:250+-30Ao)2BWaferPadOxidationPoly-SiN-WellP-WellP-Well2.TEOSDeposition(O2,670oC,8000+-400Ao)3.OxDryEtch(E/B,700oC,5000Ao)4.PlasmaARCDeposition(480+-30A)6.RELACS5.Photolithography147.OXDryEtch8.PRRemoval9.SiNDeposition(700oC,250+-30Ao)10.SiNDryEtch(E/B)0.15um製程Flow簡介1.SiNDeposition(700oC,100+-10Ao)(因為下一道製程含O2且高溫)2BOverlayMargin:C/2=(A-D-B)/23.SiO2DryEtched-back(-1000A)4.SiNDeposition(600±50A)1Setchstoplayer6.OxideSinter(7000C,N2,25min)1SCMP1S5.BPTEOSDeposition(P/B=7.5/2.2,2000±500A)7.BARCCoating(900A,1800C,60sec)9.Ar-Implantation(50KeV,1.0E16)(為增加電容）Space:0.195shrinkto0.15P.RShrink/P.Rhard10.SiO2DryEtching(stoponSiN)11.PRRemoval12.SiNDryEtch(E/B)0.15um製程Flow簡介1.P-dopeda-SiDeposistion(2000±100A)2.a-SiDryEtched-back8.Photolithography150.165umcellstructure0.15umcellstructure0.13umcellstructure0.15um製程Flow簡介Fab8A256(2)1SKuru2FailureAnalysisReportDescription: LasttwoweeksKuru2totalsuffered51lots(Yieldloss~0.4%)andthisweekKuru2suffered18lots(Yieldloss~0.2%).IFKuru2failat#14,#16,#18majoris1SKuru2(inthreeweeks,suffer~46lot).ThelotBU592LY~71.3%,C12~11.2%.FromWTbinmap,Wepickup#16(WY~56%,C12~28.6%)todoKuru2PFAanalysis.(1SKuru2,BSKuru2in2001)Summary: ThelotBU592,baseonSEMcross-sectionimages,1SKuru2failurewasSNdeformation.SEMCross-Section:yawshannormalSN-SNshortKuru2-SNdeformation0.15um製程Flow簡介SEMCross-Section:BLdirectionCantdirectionSN-SNshortSN-SNshort0.15um製程Flow簡介1.CVD-SiNDeposition(6500C,55±3A)2.Oxidation(7000C,40±3A)3.P-dopeda-SiDeposition(5200C,1000±50A)4.LampAnnealing(8000C,10sec)6.a-SiDryEtchingCP5.Photolithography177.PRRemoval0.15um製程Flow簡介1.CVD-SiO2(TEOS)Deposition(5000±300A)2.CMP(1000±50A)3.CVD-SiO2(TEOS)Deposition(1000±100A)4.OxideAnnealing(7000C,15min)6.Photolithography181C5.BARCCoating(900A)7.TEOSDryEtching8.PRRemoval1.LampAnnealing(7400C,N2,30sec)skipwillpeeling2.Sputter(SE/Ti/TiN=300±30/500±50/300±30)3.LampAnnealing(7400C,N2,30sec)4.WDeposition(4000±300A)6.Sputter(Ti/TiN/AlCu/TiN=25/400/4000±200/280A)1M5.WEtched-back(stoponTEOS)7.Photolithography199.PRRemoval8.Al/CuEtching1MCircleP/D@ringtype:(改善中)原因判明:1MArcTiNthicknessisnotenoughAction:1MArcTiN230A400APage33of50PSCConfidential0.15um製程Flow簡介BadTiNstepcoverageduetolargeAlCugrainPRReactwithPRordeveloperandcan’tberemoveduringetchingRootCauseandCountermeasurePage34of500.15um製程Flow簡介▲1TDryEtchO.E50%70%▲1TAshtime212”84”▲1TNewmasksingleviapairvia1TWmissing:(改善濟)對策:1Tloop條件變更(改善濟)0.15um製程Flow簡介1.P-SiNDeposition(7800±1000A)2.H2Sinter(4000C,H2,60min)3.PolyimideCoating(9±1.5um)PI1E-8Torr0.15um製程Flow簡介