CSE 466 Communication 1
Serial Peripheral Interface
Common serial interface on many microcontrollers
Simple 8-bit exchange between two devices
Master initiates transfer and generates clock signal
Slave device selected by master
One-byte at a time transfer
Data protocols are defined by application
Must be in agreement across devices
CSE 466 Communication 2
SPI Block Diagram
8-bits transferred in each direction every time
Master generates clock
MOSI: “Master Out Slave In”; MISO: “Master In Slave Out”
Connect MOSI to MOSI and MISO to MISO
Very clean terminology, unlike “TX” and “RX” which are easy to confuse
Slave Select (SS) used to select one of many slaves
Terminology varies:
Instead of SS, “Chip Select” (CS)
Instead of MOSI and MISO, SIMOD and SOMI
Hack: using SPI as a bus
CSE 466 Communication 3
Configuration details to watch out for
CPHA (Clock PHase) aka ~CKPH (MSP430 terminology)
= 0 or =1, determines when data goes on bus relative to clock
CPOL (Clock POLarity) aka CKPL (MSP430)
=0 clock idles low between transfers
=1 clock idles high between transfers
This leads to 4 SPI clock modes
CSE 466 Communication 4
Mode CPOL/CKPL CPHA/ ~CKPH
0 0 0
1 0 1
2 1 0
3 1 1
NB: on this slide,
~ means negation,
i.e. same as overbar
Takeaway message: make sure master and slave are configured the
same way!
SPI properties
Pros
Simplest way to connect 1 peripheral to a micro
Fast (10s of Mbits/s, not on MSP) because all lines
actively driven, unlike I2C
Clock does not need to be precise
Nice for connecting 1 slave
Cons
No built-in acknowledgement of data
Not very good for multiple slaves
Requires 4 wires
3 wire variants exist…some get rid of full duplex and share a
data line, some get rid of slave select
CSE 466 Communication 5
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CSE 466 Communication 7
Inter-Integrated Circuit Bus (I2C)
Supports data transfers
10 kbit / s slow mode
100 kbit / s standard mode
400 kbit / s fast mode
1 Mbit /s fast mode plus
3.4Mbit / s high speed mode
Philips (and others) provide many devices
microcontrollers with built-in interface
A/D and D/A converters
parallel I/O ports
memory modules
LCD drivers
real-time clock/calendars
DTMF decoders
frequency synthesizers
video/audio processors
CSE 466 Communication 8
+Vcc
device
1
device
2
device
n
SCL
SDA
Inter-Integrated Circuit Bus (I2C)
Modular connections on a printed circuit board
Multi-point connections (needs addressing)
Synchronous transfer (but adapts to slowest device)
Similar to TWI (Two-Wire Interface) on Atmegas
Pull up resistors pull lines high
Devices on bus go from “high impedance” to ground to generate a low on bus
1 Master (generates clock, initiates communication)
Up to 112 slaves (7 bit IDs, 16 reserved)
CSE 466 Communication 9
SDA
SCL
START STOP
Serial data format
SDA going low while SCL high signals start of data
SDA going high while SCL high signals end of data
SDA can change when SCL low
SCL high (after start and before end) signals that a data bit can be read
CSE 466 Communication 10
SDA
SCL
1 3 4 5 6 7 8 ack2
Byte transfer
Byte followed by a 1 bit acknowledge from receiver
Open-collector (open drain) wires
sender allows SDA to rise
receiver pulls low to acknowledge after 8 bits
Multi-byte transfers
first byte contains address of receiver
all devices check address to determine if following data is for them
second byte usually contains address of sender
CSE 466 Communication 11
CSE 466 Communication 12
Ethernet
Inspired by early wireless network: “Aloha” network from U. Hawaii
Local area network
“Classic”: 10Mbps serially on shielded co-axial cable
“Switched”: 100Mbps, 1000Mbps, 10,000Mbps
Developed by Xerox in late 70s
still most common LAN
High-level protocols to ensure reliable data transmission
CSMA-CD: carrier sense multiple access with collision detection
CSE 466 Communication 13
Ethernet
RJ-45
BNC
Bayonet
Navy
Connector
10: 10 Mbps
100: 100 Mbps
BASE: Baseband signaling
(not modulated RF, like the 100s
MHz signals on your TV cable)
5: 500m max range
2: 200m max range
T: Twisted pair
CSE 466 Communication 14
0 1 0 1 0 01 1 0
Serial data format
Manchester encoding
signal and clock on one wire (XORed together)
"0" = low-going transition
"1" = high-going transition
preamble at beginning of data packet contains alternating 1s and 0s
10MHz square wave for 6.4us….allows rcv to synch clock to tx
preamble is 64 bits long: 10101. . . 01011
Extra 1 signals Start Of Frame (SOF)
CSE 466 Communication 15
preamble 8 bytes: 7x10101010 + 10101011
destination address (6 bytes)
source address (6 bytes)
Type/length (2 bytes)
data (46-1500 bytes)
Checksum [CRC!] (4 bytes) computed from data
Ethernet packet
Packet size: 64 bytes (min!) to 1518 bytes + 8 bytes of preamble
CSE 466 Communication 16
Arbitration
CSMA/CD
“Carrier Sense Multiple Access with Collision Detection”
Wait for line to be quiet for a while then transmit
detect collision
average value on wire should be exactly between 1 and 0
if not, then two transmitters are trying to transmit data
If collision, stop transmitting
wait a random amount of time and try again
if collide again, pick a random number
from a larger range (2x) and try again
Exponential backoff on collision detection
“Random exponential backoff” or “binary exponential backoff”
Key innovation in Ethernet…Bob Metcalf’s thesis at Harvard
Try up to 16 times before reporting failure
CSE 466 Communication 17
EtherCAT
“Ethernet for Control Automation Technology”
Ethernet with
Short update times (cycle times)
Low communication jitter
Low hardware costs
Not currently very well-known, but
Used in Willow Garage PR2 robot!
CSE 466 Communication 18
EtherCAT based!
How it works
Master/Slave, Master/Master, and Slave/Slave (via Master)
supported
Master side: conventional Ethernet MAC HW
i.e., plug an EtherCAT network into the back of your laptop!
Need alternate driver SW
Slave side: custom hardware
Ethernet packets ingested & regenerated by slaves
(This would not be possible in classic bus-style Ethernet)
Slave can extract or insert “EtherCAT datagrams” into the data portion of the
Ethernet packet
Slave has to replace Ethernet CRC if it adds an EtherCAT datagram to the
Ethernet Frame
CSE 466 Communication 19
Master:
How it works
To master, it looks like there is just one Ethernet device out there (even if
there are multiple EtherCAT slaves)
In each slave, processing is done by dedicated hardware
Ensures fast, real-time behavior
“Telegrams” processed directly “on the fly”
Many EtherCAT datagrams fit in a single Ethernet packet
Many devices can be addresses in a single EtherCAT datagram
Frame overhead is amortized over many messages, improving net efficiency
CSE 466 Communication 20
Slaves:
EtherCAT Datagrams
CSE 466 Communication 21
Research examples using these comms
schemes---Pretouch sensing
We will see E-Field Sensing, USB Virtual
COM, I2C, SPI, and EtherCAT in action
CSE 466 Communication 22
Same sensing technique you are using in lab
An Electric Field Pretouch System for
Grasping and Co-Manipulation,
ICRA-2010.
B. Mayton, L. LeGrand, J.R. Smith
PC
FTDI
AVR
(Palm)
AVR
(Fing. 2)
AVR
(Fing. 1)
AVR
(Fing. 3)
USB
Asynch. serial
I2C bus
I2C slave I2C slave I2C slave
I2C master
Seashell Effect Pretouch
CSE 466 Communication 24
Movies
shown
here
CSE 466 Communication 25
HW Architecture
Integrating w/ Willow Garage PR2 Motor Control Board
CSE 466 Communication 26
EtherCAT
ASIC
FPGA
Our sensor HW: mic, op-amp, micro w/ ADC, SPI interface
To integrate our new sensor into PR2 robot, replace PPS sensor, use SPI
PicoBlaze soft microcontroller implemented in FPGA
Program PicoBlaze in Pico asm to talk to our new sensor over SPI
even though byte-level SPI is standard, at a higher level our data
format is different, so we need to reprogram the SPI master
to change from PPS sensor to our mic sensor
PicoBlaze
Soft processor from Xilinx
What is it?
Configuration of FPGA gates to implement a microcontroller within FPGA fabric
Specs
8 bit SPI master peripheral
2x 8bit timers to allow easy comms timing
512 byte double-buffer for sending sensor data to computer
Why soft processor?
Easier to program than FPGA
Faster to reprogram: seconds vs minutes
Safe: cannot brick the MCB with a bad PicoBlaze program…can easily brick MCB
with bad FPGA code
Why PicoBlaze?
Free license from Xilinx to use on Xilinx FPGAs
Very small
Simple, predictable timing (2 clock cycles per instruction)
CSE 466 Communication 27
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